1 //===-- NEONPreAllocPass.cpp - Allocate adjacent NEON registers--*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #define DEBUG_TYPE "neon-prealloc"
12 #include "ARMInstrInfo.h"
13 #include "llvm/CodeGen/MachineInstr.h"
14 #include "llvm/CodeGen/MachineInstrBuilder.h"
15 #include "llvm/CodeGen/MachineRegisterInfo.h"
16 #include "llvm/CodeGen/MachineFunctionPass.h"
20 class NEONPreAllocPass : public MachineFunctionPass {
21 const TargetInstrInfo *TII;
22 MachineRegisterInfo *MRI;
26 NEONPreAllocPass() : MachineFunctionPass(ID) {}
28 virtual bool runOnMachineFunction(MachineFunction &MF);
30 virtual const char *getPassName() const {
31 return "NEON register pre-allocation pass";
35 bool FormsRegSequence(MachineInstr *MI,
36 unsigned FirstOpnd, unsigned NumRegs,
37 unsigned Offset, unsigned Stride) const;
38 bool PreAllocNEONRegisters(MachineBasicBlock &MBB);
41 char NEONPreAllocPass::ID = 0;
44 static bool isNEONMultiRegOp(int Opcode, unsigned &FirstOpnd, unsigned &NumRegs,
45 unsigned &Offset, unsigned &Stride) {
46 // Default to unit stride with no offset.
69 case ARM::VLD2LNq16odd:
70 case ARM::VLD2LNq32odd:
92 case ARM::VLD3LNq16odd:
93 case ARM::VLD3LNq32odd:
115 case ARM::VLD4LNq16odd:
116 case ARM::VLD4LNq32odd:
138 case ARM::VST2LNq16odd:
139 case ARM::VST2LNq32odd:
161 case ARM::VST3LNq16odd:
162 case ARM::VST3LNq32odd:
184 case ARM::VST4LNq16odd:
185 case ARM::VST4LNq32odd:
227 NEONPreAllocPass::FormsRegSequence(MachineInstr *MI,
228 unsigned FirstOpnd, unsigned NumRegs,
229 unsigned Offset, unsigned Stride) const {
230 MachineOperand &FMO = MI->getOperand(FirstOpnd);
231 assert(FMO.isReg() && FMO.getSubReg() == 0 && "unexpected operand");
232 unsigned VirtReg = FMO.getReg();
234 assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
235 "expected a virtual register");
237 unsigned LastSubIdx = 0;
239 MachineInstr *RegSeq = 0;
240 for (unsigned R = 0; R < NumRegs; ++R) {
241 const MachineOperand &MO = MI->getOperand(FirstOpnd + R);
242 assert(MO.isReg() && MO.getSubReg() == 0 && "unexpected operand");
243 unsigned VirtReg = MO.getReg();
244 assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
245 "expected a virtual register");
246 // Feeding into a REG_SEQUENCE.
247 if (!MRI->hasOneNonDBGUse(VirtReg))
249 MachineInstr *UseMI = &*MRI->use_nodbg_begin(VirtReg);
250 if (!UseMI->isRegSequence())
252 if (RegSeq && RegSeq != UseMI)
254 unsigned OpIdx = 1 + (Offset + R * Stride) * 2;
255 if (UseMI->getOperand(OpIdx).getReg() != VirtReg)
256 llvm_unreachable("Malformed REG_SEQUENCE instruction!");
257 unsigned SubIdx = UseMI->getOperand(OpIdx + 1).getImm();
259 if (LastSubIdx != SubIdx-Stride)
262 // Must start from dsub_0 or qsub_0.
263 if (SubIdx != (ARM::dsub_0+Offset) &&
264 SubIdx != (ARM::qsub_0+Offset))
271 // In the case of vld3, etc., make sure the trailing operand of
272 // REG_SEQUENCE is an undef.
274 unsigned OpIdx = 1 + (Offset + 3 * Stride) * 2;
275 const MachineOperand &MO = RegSeq->getOperand(OpIdx);
276 unsigned VirtReg = MO.getReg();
277 MachineInstr *DefMI = MRI->getVRegDef(VirtReg);
278 if (!DefMI || !DefMI->isImplicitDef())
284 unsigned LastSrcReg = 0;
285 SmallVector<unsigned, 4> SubIds;
286 for (unsigned R = 0; R < NumRegs; ++R) {
287 const MachineOperand &MO = MI->getOperand(FirstOpnd + R);
288 assert(MO.isReg() && MO.getSubReg() == 0 && "unexpected operand");
289 unsigned VirtReg = MO.getReg();
290 assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
291 "expected a virtual register");
292 // Extracting from a Q or QQ register.
293 MachineInstr *DefMI = MRI->getVRegDef(VirtReg);
294 if (!DefMI || !DefMI->isCopy() || !DefMI->getOperand(1).getSubReg())
296 VirtReg = DefMI->getOperand(1).getReg();
297 if (LastSrcReg && LastSrcReg != VirtReg)
299 LastSrcReg = VirtReg;
300 const TargetRegisterClass *RC = MRI->getRegClass(VirtReg);
301 if (RC != ARM::QPRRegisterClass &&
302 RC != ARM::QQPRRegisterClass &&
303 RC != ARM::QQQQPRRegisterClass)
305 unsigned SubIdx = DefMI->getOperand(1).getSubReg();
307 if (LastSubIdx != SubIdx-Stride)
310 // Must start from dsub_0 or qsub_0.
311 if (SubIdx != (ARM::dsub_0+Offset) &&
312 SubIdx != (ARM::qsub_0+Offset))
315 SubIds.push_back(SubIdx);
319 // FIXME: Update the uses of EXTRACT_SUBREG from REG_SEQUENCE is
320 // currently required for correctness. e.g.
321 // %reg1041<def> = REG_SEQUENCE %reg1040<kill>, 5, %reg1035<kill>, 6
322 // %reg1042<def> = EXTRACT_SUBREG %reg1041, 6
323 // %reg1043<def> = EXTRACT_SUBREG %reg1041, 5
324 // VST1q16 %reg1025<kill>, 0, %reg1043<kill>, %reg1042<kill>,
325 // reg1042 and reg1043 should be replaced with reg1041:6 and reg1041:5
327 // We need to change how we model uses of REG_SEQUENCE.
328 for (unsigned R = 0; R < NumRegs; ++R) {
329 MachineOperand &MO = MI->getOperand(FirstOpnd + R);
330 unsigned OldReg = MO.getReg();
331 MachineInstr *DefMI = MRI->getVRegDef(OldReg);
332 assert(DefMI->isCopy());
333 MO.setReg(LastSrcReg);
334 MO.setSubReg(SubIds[R]);
336 // Delete the EXTRACT_SUBREG if its result is now dead.
337 if (MRI->use_empty(OldReg))
338 DefMI->eraseFromParent();
344 bool NEONPreAllocPass::PreAllocNEONRegisters(MachineBasicBlock &MBB) {
345 bool Modified = false;
347 MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
348 for (; MBBI != E; ++MBBI) {
349 MachineInstr *MI = &*MBBI;
350 unsigned FirstOpnd, NumRegs, Offset, Stride;
351 if (!isNEONMultiRegOp(MI->getOpcode(), FirstOpnd, NumRegs, Offset, Stride))
353 if (FormsRegSequence(MI, FirstOpnd, NumRegs, Offset, Stride))
356 MachineBasicBlock::iterator NextI = llvm::next(MBBI);
357 for (unsigned R = 0; R < NumRegs; ++R) {
358 MachineOperand &MO = MI->getOperand(FirstOpnd + R);
359 assert(MO.isReg() && MO.getSubReg() == 0 && "unexpected operand");
360 unsigned VirtReg = MO.getReg();
361 assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
362 "expected a virtual register");
364 // For now, just assign a fixed set of adjacent registers.
365 // This leaves plenty of room for future improvements.
366 static const unsigned NEONDRegs[] = {
367 ARM::D0, ARM::D1, ARM::D2, ARM::D3,
368 ARM::D4, ARM::D5, ARM::D6, ARM::D7
370 MO.setReg(NEONDRegs[Offset + R * Stride]);
373 // Insert a copy from VirtReg.
374 BuildMI(MBB, MBBI, DebugLoc(), TII->get(TargetOpcode::COPY),MO.getReg())
375 .addReg(VirtReg, getKillRegState(MO.isKill()));
377 } else if (MO.isDef() && !MO.isDead()) {
378 // Add a copy to VirtReg.
379 BuildMI(MBB, NextI, DebugLoc(), TII->get(TargetOpcode::COPY), VirtReg)
380 .addReg(MO.getReg());
388 bool NEONPreAllocPass::runOnMachineFunction(MachineFunction &MF) {
389 TII = MF.getTarget().getInstrInfo();
390 MRI = &MF.getRegInfo();
392 bool Modified = false;
393 for (MachineFunction::iterator MFI = MF.begin(), E = MF.end(); MFI != E;
395 MachineBasicBlock &MBB = *MFI;
396 Modified |= PreAllocNEONRegisters(MBB);
402 /// createNEONPreAllocPass - returns an instance of the NEON register
403 /// pre-allocation pass.
404 FunctionPass *llvm::createNEONPreAllocPass() {
405 return new NEONPreAllocPass();