1 //===-- NEONPreAllocPass.cpp - Allocate adjacent NEON registers--*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #define DEBUG_TYPE "neon-prealloc"
12 #include "ARMInstrInfo.h"
13 #include "llvm/CodeGen/MachineInstr.h"
14 #include "llvm/CodeGen/MachineInstrBuilder.h"
15 #include "llvm/CodeGen/MachineFunctionPass.h"
19 class NEONPreAllocPass : public MachineFunctionPass {
20 const TargetInstrInfo *TII;
24 NEONPreAllocPass() : MachineFunctionPass(&ID) {}
26 virtual bool runOnMachineFunction(MachineFunction &MF);
28 virtual const char *getPassName() const {
29 return "NEON register pre-allocation pass";
33 bool PreAllocNEONRegisters(MachineBasicBlock &MBB);
36 char NEONPreAllocPass::ID = 0;
39 static bool isNEONMultiRegOp(int Opcode, unsigned &FirstOpnd, unsigned &NumRegs,
40 unsigned &Offset, unsigned &Stride) {
41 // Default to unit stride with no offset.
78 case ARM::VLD2LNq16odd:
79 case ARM::VLD2LNq32odd:
98 case ARM::VLD3q16_UPD:
99 case ARM::VLD3q32_UPD:
106 case ARM::VLD3q8odd_UPD:
107 case ARM::VLD3q16odd_UPD:
108 case ARM::VLD3q32odd_UPD:
123 case ARM::VLD3LNq16odd:
124 case ARM::VLD3LNq32odd:
142 case ARM::VLD4q8_UPD:
143 case ARM::VLD4q16_UPD:
144 case ARM::VLD4q32_UPD:
151 case ARM::VLD4q8odd_UPD:
152 case ARM::VLD4q16odd_UPD:
153 case ARM::VLD4q32odd_UPD:
168 case ARM::VLD4LNq16odd:
169 case ARM::VLD4LNq32odd:
205 case ARM::VST2LNq16odd:
206 case ARM::VST2LNq32odd:
224 case ARM::VST3q8_UPD:
225 case ARM::VST3q16_UPD:
226 case ARM::VST3q32_UPD:
233 case ARM::VST3q8odd_UPD:
234 case ARM::VST3q16odd_UPD:
235 case ARM::VST3q32odd_UPD:
250 case ARM::VST3LNq16odd:
251 case ARM::VST3LNq32odd:
269 case ARM::VST4q8_UPD:
270 case ARM::VST4q16_UPD:
271 case ARM::VST4q32_UPD:
278 case ARM::VST4q8odd_UPD:
279 case ARM::VST4q16odd_UPD:
280 case ARM::VST4q32odd_UPD:
295 case ARM::VST4LNq16odd:
296 case ARM::VST4LNq32odd:
337 bool NEONPreAllocPass::PreAllocNEONRegisters(MachineBasicBlock &MBB) {
338 bool Modified = false;
340 MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
341 for (; MBBI != E; ++MBBI) {
342 MachineInstr *MI = &*MBBI;
343 unsigned FirstOpnd, NumRegs, Offset, Stride;
344 if (!isNEONMultiRegOp(MI->getOpcode(), FirstOpnd, NumRegs, Offset, Stride))
347 MachineBasicBlock::iterator NextI = llvm::next(MBBI);
348 for (unsigned R = 0; R < NumRegs; ++R) {
349 MachineOperand &MO = MI->getOperand(FirstOpnd + R);
350 assert(MO.isReg() && MO.getSubReg() == 0 && "unexpected operand");
351 unsigned VirtReg = MO.getReg();
352 assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
353 "expected a virtual register");
355 // For now, just assign a fixed set of adjacent registers.
356 // This leaves plenty of room for future improvements.
357 static const unsigned NEONDRegs[] = {
358 ARM::D0, ARM::D1, ARM::D2, ARM::D3,
359 ARM::D4, ARM::D5, ARM::D6, ARM::D7
361 MO.setReg(NEONDRegs[Offset + R * Stride]);
364 // Insert a copy from VirtReg.
365 TII->copyRegToReg(MBB, MBBI, MO.getReg(), VirtReg,
366 ARM::DPRRegisterClass, ARM::DPRRegisterClass);
368 MachineInstr *CopyMI = prior(MBBI);
369 CopyMI->findRegisterUseOperand(VirtReg)->setIsKill();
372 } else if (MO.isDef() && !MO.isDead()) {
373 // Add a copy to VirtReg.
374 TII->copyRegToReg(MBB, NextI, VirtReg, MO.getReg(),
375 ARM::DPRRegisterClass, ARM::DPRRegisterClass);
383 bool NEONPreAllocPass::runOnMachineFunction(MachineFunction &MF) {
384 TII = MF.getTarget().getInstrInfo();
386 bool Modified = false;
387 for (MachineFunction::iterator MFI = MF.begin(), E = MF.end(); MFI != E;
389 MachineBasicBlock &MBB = *MFI;
390 Modified |= PreAllocNEONRegisters(MBB);
396 /// createNEONPreAllocPass - returns an instance of the NEON register
397 /// pre-allocation pass.
398 FunctionPass *llvm::createNEONPreAllocPass() {
399 return new NEONPreAllocPass();