1 //===-- NEONPreAllocPass.cpp - Allocate adjacent NEON registers--*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #define DEBUG_TYPE "neon-prealloc"
12 #include "ARMInstrInfo.h"
13 #include "llvm/CodeGen/MachineInstr.h"
14 #include "llvm/CodeGen/MachineInstrBuilder.h"
15 #include "llvm/CodeGen/MachineFunctionPass.h"
19 class VISIBILITY_HIDDEN NEONPreAllocPass : public MachineFunctionPass {
20 const TargetInstrInfo *TII;
24 NEONPreAllocPass() : MachineFunctionPass(&ID) {}
26 virtual bool runOnMachineFunction(MachineFunction &MF);
28 virtual const char *getPassName() const {
29 return "NEON register pre-allocation pass";
33 bool PreAllocNEONRegisters(MachineBasicBlock &MBB);
36 char NEONPreAllocPass::ID = 0;
39 static bool isNEONMultiRegOp(int Opcode, unsigned &FirstOpnd, unsigned &NumRegs,
40 unsigned &Offset, unsigned &Stride) {
41 // Default to unit stride with no offset.
230 bool NEONPreAllocPass::PreAllocNEONRegisters(MachineBasicBlock &MBB) {
231 bool Modified = false;
233 MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
234 for (; MBBI != E; ++MBBI) {
235 MachineInstr *MI = &*MBBI;
236 unsigned FirstOpnd, NumRegs, Offset, Stride;
237 if (!isNEONMultiRegOp(MI->getOpcode(), FirstOpnd, NumRegs, Offset, Stride))
240 MachineBasicBlock::iterator NextI = next(MBBI);
241 for (unsigned R = 0; R < NumRegs; ++R) {
242 MachineOperand &MO = MI->getOperand(FirstOpnd + R);
243 assert(MO.isReg() && MO.getSubReg() == 0 && "unexpected operand");
244 unsigned VirtReg = MO.getReg();
245 assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
246 "expected a virtual register");
248 // For now, just assign a fixed set of adjacent registers.
249 // This leaves plenty of room for future improvements.
250 static const unsigned NEONDRegs[] = {
251 ARM::D0, ARM::D1, ARM::D2, ARM::D3,
252 ARM::D4, ARM::D5, ARM::D6, ARM::D7
254 MO.setReg(NEONDRegs[Offset + R * Stride]);
257 // Insert a copy from VirtReg.
258 TII->copyRegToReg(MBB, MBBI, MO.getReg(), VirtReg,
259 ARM::DPRRegisterClass, ARM::DPRRegisterClass);
261 MachineInstr *CopyMI = prior(MBBI);
262 CopyMI->findRegisterUseOperand(VirtReg)->setIsKill();
265 } else if (MO.isDef() && !MO.isDead()) {
266 // Add a copy to VirtReg.
267 TII->copyRegToReg(MBB, NextI, VirtReg, MO.getReg(),
268 ARM::DPRRegisterClass, ARM::DPRRegisterClass);
276 bool NEONPreAllocPass::runOnMachineFunction(MachineFunction &MF) {
277 TII = MF.getTarget().getInstrInfo();
279 bool Modified = false;
280 for (MachineFunction::iterator MFI = MF.begin(), E = MF.end(); MFI != E;
282 MachineBasicBlock &MBB = *MFI;
283 Modified |= PreAllocNEONRegisters(MBB);
289 /// createNEONPreAllocPass - returns an instance of the NEON register
290 /// pre-allocation pass.
291 FunctionPass *llvm::createNEONPreAllocPass() {
292 return new NEONPreAllocPass();