1 //===---------------------------------------------------------------------===//
2 // Random ideas for the ARM backend.
3 //===---------------------------------------------------------------------===//
5 Reimplement 'select' in terms of 'SEL'.
7 * We would really like to support UXTAB16, but we need to prove that the
8 add doesn't need to overflow between the two 16-bit chunks.
10 * Implement pre/post increment support. (e.g. PR935)
11 * Coalesce stack slots!
12 * Implement smarter constant generation for binops with large immediates.
14 * Consider materializing FP constants like 0.0f and 1.0f using integer
15 immediate instructions then copy to FPU. Slower than load into FPU?
17 //===---------------------------------------------------------------------===//
19 Crazy idea: Consider code that uses lots of 8-bit or 16-bit values. By the
20 time regalloc happens, these values are now in a 32-bit register, usually with
21 the top-bits known to be sign or zero extended. If spilled, we should be able
22 to spill these to a 8-bit or 16-bit stack slot, zero or sign extending as part
25 Doing this reduces the size of the stack frame (important for thumb etc), and
26 also increases the likelihood that we will be able to reload multiple values
27 from the stack with a single load.
29 //===---------------------------------------------------------------------===//
31 The constant island pass is in good shape. Some cleanups might be desirable,
32 but there is unlikely to be much improvement in the generated code.
34 1. There may be some advantage to trying to be smarter about the initial
35 placement, rather than putting everything at the end.
37 2. There might be some compile-time efficiency to be had by representing
38 consecutive islands as a single block rather than multiple blocks.
40 3. Use a priority queue to sort constant pool users in inverse order of
41 position so we always process the one closed to the end of functions
42 first. This may simply CreateNewWater.
44 //===---------------------------------------------------------------------===//
46 Eliminate copysign custom expansion. We are still generating crappy code with
47 default expansion + if-conversion.
49 //===---------------------------------------------------------------------===//
51 Eliminate one instruction from:
53 define i32 @_Z6slow4bii(i32 %x, i32 %y) {
54 %tmp = icmp sgt i32 %x, %y
55 %retval = select i1 %tmp, i32 %x, i32 %y
71 //===---------------------------------------------------------------------===//
73 Implement long long "X-3" with instructions that fold the immediate in. These
74 were disabled due to badness with the ARM carry flag on subtracts.
76 //===---------------------------------------------------------------------===//
78 We currently compile abs:
79 int foo(int p) { return p < 0 ? -p : p; }
90 This is very, uh, literal. This could be a 3 operation sequence:
94 Which would be better. This occurs in png decode.
96 //===---------------------------------------------------------------------===//
98 More load / store optimizations:
99 1) Look past instructions without side-effects (not load, store, branch, etc.)
100 when forming the list of loads / stores to optimize.
102 2) Smarter register allocation?
103 We are probably missing some opportunities to use ldm / stm. Consider:
108 This cannot be merged into a ldm. Perhaps we will need to do the transformation
109 before register allocation. Then teach the register allocator to allocate a
110 chunk of consecutive registers.
112 3) Better representation for block transfer? This is from Olden/power:
123 If we can spare the registers, it would be better to use fldm and fstm here.
124 Need major register allocator enhancement though.
126 4) Can we recognize the relative position of constantpool entries? i.e. Treat
137 Then the ldr's can be combined into a single ldm. See Olden/power.
139 Note for ARM v4 gcc uses ldmia to load a pair of 32-bit values to represent a
140 double 64-bit FP constant:
150 5) Can we make use of ldrd and strd? Instead of generating ldm / stm, use
151 ldrd/strd instead if there are only two destination registers that form an
152 odd/even pair. However, we probably would pay a penalty if the address is not
153 aligned on 8-byte boundary. This requires more information on load / store
154 nodes (and MI's?) then we currently carry.
156 6) struct copies appear to be done field by field
157 instead of by words, at least sometimes:
159 struct foo { int x; short s; char c1; char c2; };
160 void cpy(struct foo*a, struct foo*b) { *a = *b; }
175 In this benchmark poor handling of aggregate copies has shown up as
176 having a large effect on size, and possibly speed as well (we don't have
177 a good way to measure on ARM).
179 //===---------------------------------------------------------------------===//
181 * Consider this silly example:
183 double bar(double x) {
208 Ignore the prologue and epilogue stuff for a second. Note
211 the copys to callee-save registers and the fact they are only being used by the
212 fmdrr instruction. It would have been better had the fmdrr been scheduled
213 before the call and place the result in a callee-save DPR register. The two
214 mov ops would not have been necessary.
216 //===---------------------------------------------------------------------===//
218 Calling convention related stuff:
220 * gcc's parameter passing implementation is terrible and we suffer as a result:
228 void foo(struct s S) {
229 printf("%g, %d\n", S.d1, S.s1);
232 'S' is passed via registers r0, r1, r2. But gcc stores them to the stack, and
233 then reload them to r1, r2, and r3 before issuing the call (r0 contains the
234 address of the format string):
239 stmia sp, {r0, r1, r2}
247 Instead of a stmia, ldmia, and a ldr, wouldn't it be better to do three moves?
249 * Return an aggregate type is even worse:
253 struct s S = {1.1, 2};
262 @ lr needed for prologue
263 ldmia r0, {r0, r1, r2}
264 stmia sp, {r0, r1, r2}
265 stmia ip, {r0, r1, r2}
270 r0 (and later ip) is the hidden parameter from caller to store the value in. The
271 first ldmia loads the constants into r0, r1, r2. The last stmia stores r0, r1,
272 r2 into the address passed in. However, there is one additional stmia that
273 stores r0, r1, and r2 to some stack location. The store is dead.
275 The llvm-gcc generated code looks like this:
277 csretcc void %foo(%struct.s* %agg.result) {
279 %S = alloca %struct.s, align 4 ; <%struct.s*> [#uses=1]
280 %memtmp = alloca %struct.s ; <%struct.s*> [#uses=1]
281 cast %struct.s* %S to sbyte* ; <sbyte*>:0 [#uses=2]
282 call void %llvm.memcpy.i32( sbyte* %0, sbyte* cast ({ double, int }* %C.0.904 to sbyte*), uint 12, uint 4 )
283 cast %struct.s* %agg.result to sbyte* ; <sbyte*>:1 [#uses=2]
284 call void %llvm.memcpy.i32( sbyte* %1, sbyte* %0, uint 12, uint 0 )
285 cast %struct.s* %memtmp to sbyte* ; <sbyte*>:2 [#uses=1]
286 call void %llvm.memcpy.i32( sbyte* %2, sbyte* %1, uint 12, uint 0 )
290 llc ends up issuing two memcpy's (the first memcpy becomes 3 loads from
291 constantpool). Perhaps we should 1) fix llvm-gcc so the memcpy is translated
292 into a number of load and stores, or 2) custom lower memcpy (of small size) to
293 be ldmia / stmia. I think option 2 is better but the current register
294 allocator cannot allocate a chunk of registers at a time.
296 A feasible temporary solution is to use specific physical registers at the
297 lowering time for small (<= 4 words?) transfer size.
299 * ARM CSRet calling convention requires the hidden argument to be returned by
302 //===---------------------------------------------------------------------===//
304 We can definitely do a better job on BB placements to eliminate some branches.
305 It's very common to see llvm generated assembly code that looks like this:
314 If BB4 is the only predecessor of BB3, then we can emit BB3 after BB4. We can
315 then eliminate beq and and turn the unconditional branch to LBB2 to a bne.
317 See McCat/18-imp/ComputeBoundingBoxes for an example.
319 //===---------------------------------------------------------------------===//
321 Register scavenging is now implemented. The example in the previous version
322 of this document produces optimal code at -O2.
324 //===---------------------------------------------------------------------===//
326 Pre-/post- indexed load / stores:
328 1) We should not make the pre/post- indexed load/store transform if the base ptr
329 is guaranteed to be live beyond the load/store. This can happen if the base
330 ptr is live out of the block we are performing the optimization. e.g.
342 In most cases, this is just a wasted optimization. However, sometimes it can
343 negatively impact the performance because two-address code is more restrictive
344 when it comes to scheduling.
346 Unfortunately, liveout information is currently unavailable during DAG combine
349 2) Consider spliting a indexed load / store into a pair of add/sub + load/store
350 to solve #1 (in TwoAddressInstructionPass.cpp).
352 3) Enhance LSR to generate more opportunities for indexed ops.
354 4) Once we added support for multiple result patterns, write indexed loads
355 patterns instead of C++ instruction selection code.
357 5) Use FLDM / FSTM to emulate indexed FP load / store.
359 //===---------------------------------------------------------------------===//
361 We should add i64 support to take advantage of the 64-bit load / stores.
362 We can add a pseudo i64 register class containing pseudo registers that are
363 register pairs. All other ops (e.g. add, sub) would be expanded as usual.
365 We need to add pseudo instructions (i.e. gethi / getlo) to extract i32 registers
366 from the i64 register. These are single moves which can be eliminated if the
367 destination register is a sub-register of the source. We should implement proper
368 subreg support in the register allocator to coalesce these away.
370 There are other minor issues such as multiple instructions for a spill / restore
373 //===---------------------------------------------------------------------===//
375 Implement support for some more tricky ways to materialize immediates. For
376 example, to get 0xffff8000, we can use:
381 //===---------------------------------------------------------------------===//
383 We sometimes generate multiple add / sub instructions to update sp in prologue
384 and epilogue if the inc / dec value is too large to fit in a single immediate
385 operand. In some cases, perhaps it might be better to load the value from a
386 constantpool instead.
388 //===---------------------------------------------------------------------===//
390 GCC generates significantly better code for this function.
392 int foo(int StackPtr, unsigned char *Line, unsigned char *Stack, int LineLen) {
396 while (StackPtr != 0 && i < (((LineLen) < (32768))? (LineLen) : (32768)))
397 Line[i++] = Stack[--StackPtr];
400 while (StackPtr != 0 && i < LineLen)
410 //===---------------------------------------------------------------------===//
412 This should compile to the mlas instruction:
413 int mlas(int x, int y, int z) { return ((x * y + z) < 0) ? 7 : 13; }
415 //===---------------------------------------------------------------------===//
417 At some point, we should triage these to see if they still apply to us:
419 http://gcc.gnu.org/bugzilla/show_bug.cgi?id=19598
420 http://gcc.gnu.org/bugzilla/show_bug.cgi?id=18560
421 http://gcc.gnu.org/bugzilla/show_bug.cgi?id=27016
423 http://gcc.gnu.org/bugzilla/show_bug.cgi?id=11831
424 http://gcc.gnu.org/bugzilla/show_bug.cgi?id=11826
425 http://gcc.gnu.org/bugzilla/show_bug.cgi?id=11825
426 http://gcc.gnu.org/bugzilla/show_bug.cgi?id=11824
427 http://gcc.gnu.org/bugzilla/show_bug.cgi?id=11823
428 http://gcc.gnu.org/bugzilla/show_bug.cgi?id=11820
429 http://gcc.gnu.org/bugzilla/show_bug.cgi?id=10982
431 http://gcc.gnu.org/bugzilla/show_bug.cgi?id=10242
432 http://gcc.gnu.org/bugzilla/show_bug.cgi?id=9831
433 http://gcc.gnu.org/bugzilla/show_bug.cgi?id=9760
434 http://gcc.gnu.org/bugzilla/show_bug.cgi?id=9759
435 http://gcc.gnu.org/bugzilla/show_bug.cgi?id=9703
436 http://gcc.gnu.org/bugzilla/show_bug.cgi?id=9702
437 http://gcc.gnu.org/bugzilla/show_bug.cgi?id=9663
439 http://www.inf.u-szeged.hu/gcc-arm/
440 http://citeseer.ist.psu.edu/debus04linktime.html
442 //===---------------------------------------------------------------------===//
444 gcc generates smaller code for this function at -O2 or -Os:
446 void foo(signed char* p) {
455 llvm decides it's a good idea to turn the repeated if...else into a
456 binary tree, as if it were a switch; the resulting code requires -1
457 compare-and-branches when *p<=2 or *p==5, the same number if *p==4
458 or *p>6, and +1 if *p==3. So it should be a speed win
459 (on balance). However, the revised code is larger, with 4 conditional
460 branches instead of 3.
462 More seriously, there is a byte->word extend before
463 each comparison, where there should be only one, and the condition codes
464 are not remembered when the same two values are compared twice.
466 //===---------------------------------------------------------------------===//
468 More register scavenging work:
470 1. Use the register scavenger to track frame index materialized into registers
471 (those that do not fit in addressing modes) to allow reuse in the same BB.
472 2. Finish scavenging for Thumb.
473 3. We know some spills and restores are unnecessary. The issue is once live
474 intervals are merged, they are not never split. So every def is spilled
475 and every use requires a restore if the register allocator decides the
476 resulting live interval is not assigned a physical register. It may be
477 possible (with the help of the scavenger) to turn some spill / restore
478 pairs into register copies.
480 //===---------------------------------------------------------------------===//
482 More LSR enhancements possible:
484 1. Teach LSR about pre- and post- indexed ops to allow iv increment be merged
486 2. Allow iv reuse even when a type conversion is required. For example, i8
487 and i32 load / store addressing modes are identical.
490 //===---------------------------------------------------------------------===//
494 int foo(int a, int b, int c, int d) {
495 long long acc = (long long)a * (long long)b;
496 acc += (long long)c * (long long)d;
497 return (int)(acc >> 32);
500 Should compile to use SMLAL (Signed Multiply Accumulate Long) which multiplies
501 two signed 32-bit values to produce a 64-bit value, and accumulates this with
504 We currently get this with v6:
528 This apparently occurs in real code.
530 //===---------------------------------------------------------------------===//
534 std::pair<unsigned, bool> full_add(unsigned a, unsigned b)
535 { return std::make_pair(a + b, a + b < a); }
536 bool no_overflow(unsigned a, unsigned b)
537 { return !full_add(a, b).second; }
575 //===---------------------------------------------------------------------===//