1 //===-- Thumb1FrameLowering.cpp - Thumb1 Frame Information ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Thumb1 implementation of TargetFrameLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "Thumb1FrameLowering.h"
15 #include "ARMMachineFunctionInfo.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/MachineModuleInfo.h"
20 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 Thumb1FrameLowering::Thumb1FrameLowering(const ARMSubtarget &sti)
25 : ARMFrameLowering(sti) {}
27 bool Thumb1FrameLowering::hasReservedCallFrame(const MachineFunction &MF) const{
28 const MachineFrameInfo *FFI = MF.getFrameInfo();
29 unsigned CFSize = FFI->getMaxCallFrameSize();
30 // It's not always a good idea to include the call frame as part of the
31 // stack frame. ARM (especially Thumb) has small immediate offset to
32 // address the stack frame. So a large call frame can cause poor codegen
33 // and may even makes it impossible to scavenge a register.
34 if (CFSize >= ((1 << 8) - 1) * 4 / 2) // Half of imm8 * 4
37 return !MF.getFrameInfo()->hasVarSizedObjects();
41 emitSPUpdate(MachineBasicBlock &MBB,
42 MachineBasicBlock::iterator &MBBI,
43 const TargetInstrInfo &TII, DebugLoc dl,
44 const ThumbRegisterInfo &MRI,
45 int NumBytes, unsigned MIFlags = MachineInstr::NoFlags) {
46 emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, TII,
51 void Thumb1FrameLowering::
52 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
53 MachineBasicBlock::iterator I) const {
54 const Thumb1InstrInfo &TII =
55 *static_cast<const Thumb1InstrInfo *>(STI.getInstrInfo());
56 const ThumbRegisterInfo *RegInfo =
57 static_cast<const ThumbRegisterInfo *>(STI.getRegisterInfo());
58 if (!hasReservedCallFrame(MF)) {
59 // If we have alloca, convert as follows:
60 // ADJCALLSTACKDOWN -> sub, sp, sp, amount
61 // ADJCALLSTACKUP -> add, sp, sp, amount
62 MachineInstr *Old = I;
63 DebugLoc dl = Old->getDebugLoc();
64 unsigned Amount = Old->getOperand(0).getImm();
66 // We need to keep the stack aligned properly. To do this, we round the
67 // amount of space needed for the outgoing arguments up to the next
68 // alignment boundary.
69 unsigned Align = getStackAlignment();
70 Amount = (Amount+Align-1)/Align*Align;
72 // Replace the pseudo instruction with a new instruction...
73 unsigned Opc = Old->getOpcode();
74 if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
75 emitSPUpdate(MBB, I, TII, dl, *RegInfo, -Amount);
77 assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
78 emitSPUpdate(MBB, I, TII, dl, *RegInfo, Amount);
85 void Thumb1FrameLowering::emitPrologue(MachineFunction &MF,
86 MachineBasicBlock &MBB) const {
87 assert(&MBB == &MF.front() && "Shrink-wrapping not yet implemented");
88 MachineBasicBlock::iterator MBBI = MBB.begin();
89 MachineFrameInfo *MFI = MF.getFrameInfo();
90 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
91 MachineModuleInfo &MMI = MF.getMMI();
92 const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
93 const ThumbRegisterInfo *RegInfo =
94 static_cast<const ThumbRegisterInfo *>(STI.getRegisterInfo());
95 const Thumb1InstrInfo &TII =
96 *static_cast<const Thumb1InstrInfo *>(STI.getInstrInfo());
98 unsigned ArgRegsSaveSize = AFI->getArgRegsSaveSize();
99 unsigned NumBytes = MFI->getStackSize();
100 assert(NumBytes >= ArgRegsSaveSize &&
101 "ArgRegsSaveSize is included in NumBytes");
102 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
103 DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
104 unsigned FramePtr = RegInfo->getFrameRegister(MF);
105 unsigned BasePtr = RegInfo->getBaseRegister();
108 // Thumb add/sub sp, imm8 instructions implicitly multiply the offset by 4.
109 NumBytes = (NumBytes + 3) & ~3;
110 MFI->setStackSize(NumBytes);
112 // Determine the sizes of each callee-save spill areas and record which frame
113 // belongs to which callee-save spill areas.
114 unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
115 int FramePtrSpillFI = 0;
117 if (ArgRegsSaveSize) {
118 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -ArgRegsSaveSize,
119 MachineInstr::FrameSetup);
120 CFAOffset -= ArgRegsSaveSize;
121 unsigned CFIIndex = MMI.addFrameInst(
122 MCCFIInstruction::createDefCfaOffset(nullptr, CFAOffset));
123 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
124 .addCFIIndex(CFIIndex)
125 .setMIFlags(MachineInstr::FrameSetup);
128 if (!AFI->hasStackFrame()) {
129 if (NumBytes - ArgRegsSaveSize != 0) {
130 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -(NumBytes - ArgRegsSaveSize),
131 MachineInstr::FrameSetup);
132 CFAOffset -= NumBytes - ArgRegsSaveSize;
133 unsigned CFIIndex = MMI.addFrameInst(
134 MCCFIInstruction::createDefCfaOffset(nullptr, CFAOffset));
135 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
136 .addCFIIndex(CFIIndex)
137 .setMIFlags(MachineInstr::FrameSetup);
142 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
143 unsigned Reg = CSI[i].getReg();
144 int FI = CSI[i].getFrameIdx();
150 if (STI.isTargetMachO()) {
161 FramePtrSpillFI = FI;
169 if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPUSH) {
171 if (MBBI != MBB.end())
172 dl = MBBI->getDebugLoc();
175 // Determine starting offsets of spill areas.
176 unsigned DPRCSOffset = NumBytes - ArgRegsSaveSize - (GPRCS1Size + GPRCS2Size + DPRCSSize);
177 unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize;
178 unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size;
179 bool HasFP = hasFP(MF);
181 AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) +
183 AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
184 AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
185 AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
186 NumBytes = DPRCSOffset;
188 int FramePtrOffsetInBlock = 0;
189 unsigned adjustedGPRCS1Size = GPRCS1Size;
190 if (tryFoldSPUpdateIntoPushPop(STI, MF, std::prev(MBBI), NumBytes)) {
191 FramePtrOffsetInBlock = NumBytes;
192 adjustedGPRCS1Size += NumBytes;
196 if (adjustedGPRCS1Size) {
197 CFAOffset -= adjustedGPRCS1Size;
198 unsigned CFIIndex = MMI.addFrameInst(
199 MCCFIInstruction::createDefCfaOffset(nullptr, CFAOffset));
200 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
201 .addCFIIndex(CFIIndex)
202 .setMIFlags(MachineInstr::FrameSetup);
204 for (std::vector<CalleeSavedInfo>::const_iterator I = CSI.begin(),
205 E = CSI.end(); I != E; ++I) {
206 unsigned Reg = I->getReg();
207 int FI = I->getFrameIdx();
214 if (STI.isTargetMachO())
226 unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset(
227 nullptr, MRI->getDwarfRegNum(Reg, true), MFI->getObjectOffset(FI)));
228 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
229 .addCFIIndex(CFIIndex)
230 .setMIFlags(MachineInstr::FrameSetup);
236 // Adjust FP so it point to the stack slot that contains the previous FP.
238 FramePtrOffsetInBlock += MFI->getObjectOffset(FramePtrSpillFI)
239 + GPRCS1Size + ArgRegsSaveSize;
240 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tADDrSPi), FramePtr)
241 .addReg(ARM::SP).addImm(FramePtrOffsetInBlock / 4)
242 .setMIFlags(MachineInstr::FrameSetup));
243 if(FramePtrOffsetInBlock) {
244 CFAOffset += FramePtrOffsetInBlock;
245 unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createDefCfa(
246 nullptr, MRI->getDwarfRegNum(FramePtr, true), CFAOffset));
247 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
248 .addCFIIndex(CFIIndex)
249 .setMIFlags(MachineInstr::FrameSetup);
252 MMI.addFrameInst(MCCFIInstruction::createDefCfaRegister(
253 nullptr, MRI->getDwarfRegNum(FramePtr, true)));
254 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
255 .addCFIIndex(CFIIndex)
256 .setMIFlags(MachineInstr::FrameSetup);
259 // If offset is > 508 then sp cannot be adjusted in a single instruction,
260 // try restoring from fp instead.
261 AFI->setShouldRestoreSPFromFP(true);
265 // Insert it after all the callee-save spills.
266 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -NumBytes,
267 MachineInstr::FrameSetup);
269 CFAOffset -= NumBytes;
270 unsigned CFIIndex = MMI.addFrameInst(
271 MCCFIInstruction::createDefCfaOffset(nullptr, CFAOffset));
272 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
273 .addCFIIndex(CFIIndex)
274 .setMIFlags(MachineInstr::FrameSetup);
278 if (STI.isTargetELF() && HasFP)
279 MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() -
280 AFI->getFramePtrSpillOffset());
282 AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
283 AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
284 AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
286 // Thumb1 does not currently support dynamic stack realignment. Report a
287 // fatal error rather then silently generate bad code.
288 if (RegInfo->needsStackRealignment(MF))
289 report_fatal_error("Dynamic stack realignment not supported for thumb1.");
291 // If we need a base pointer, set it up here. It's whatever the value
292 // of the stack pointer is at this point. Any variable size objects
293 // will be allocated after this, so we can still use the base pointer
294 // to reference locals.
295 if (RegInfo->hasBasePointer(MF))
296 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), BasePtr)
299 // If the frame has variable sized objects then the epilogue must restore
300 // the sp from fp. We can assume there's an FP here since hasFP already
301 // checks for hasVarSizedObjects.
302 if (MFI->hasVarSizedObjects())
303 AFI->setShouldRestoreSPFromFP(true);
306 static bool isCSRestore(MachineInstr *MI, const MCPhysReg *CSRegs) {
307 if (MI->getOpcode() == ARM::tLDRspi &&
308 MI->getOperand(1).isFI() &&
309 isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs))
311 else if (MI->getOpcode() == ARM::tPOP) {
312 // The first two operands are predicates. The last two are
313 // imp-def and imp-use of SP. Check everything in between.
314 for (int i = 2, e = MI->getNumOperands() - 2; i != e; ++i)
315 if (!isCalleeSavedRegister(MI->getOperand(i).getReg(), CSRegs))
322 void Thumb1FrameLowering::emitEpilogue(MachineFunction &MF,
323 MachineBasicBlock &MBB) const {
324 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
325 assert((MBBI->getOpcode() == ARM::tBX_RET ||
326 MBBI->getOpcode() == ARM::tPOP_RET) &&
327 "Can only insert epilog into returning blocks");
328 DebugLoc dl = MBBI->getDebugLoc();
329 MachineFrameInfo *MFI = MF.getFrameInfo();
330 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
331 const ThumbRegisterInfo *RegInfo =
332 static_cast<const ThumbRegisterInfo *>(STI.getRegisterInfo());
333 const Thumb1InstrInfo &TII =
334 *static_cast<const Thumb1InstrInfo *>(STI.getInstrInfo());
336 unsigned ArgRegsSaveSize = AFI->getArgRegsSaveSize();
337 int NumBytes = (int)MFI->getStackSize();
338 assert((unsigned)NumBytes >= ArgRegsSaveSize &&
339 "ArgRegsSaveSize is included in NumBytes");
340 const MCPhysReg *CSRegs = RegInfo->getCalleeSavedRegs(&MF);
341 unsigned FramePtr = RegInfo->getFrameRegister(MF);
343 if (!AFI->hasStackFrame()) {
344 if (NumBytes - ArgRegsSaveSize != 0)
345 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, NumBytes - ArgRegsSaveSize);
347 // Unwind MBBI to point to first LDR / VLDRD.
348 if (MBBI != MBB.begin()) {
351 while (MBBI != MBB.begin() && isCSRestore(MBBI, CSRegs));
352 if (!isCSRestore(MBBI, CSRegs))
356 // Move SP to start of FP callee save spill area.
357 NumBytes -= (AFI->getGPRCalleeSavedArea1Size() +
358 AFI->getGPRCalleeSavedArea2Size() +
359 AFI->getDPRCalleeSavedAreaSize() +
362 if (AFI->shouldRestoreSPFromFP()) {
363 NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
364 // Reset SP based on frame pointer only if the stack frame extends beyond
365 // frame pointer stack slot, the target is ELF and the function has FP, or
366 // the target uses var sized objects.
368 assert(MF.getRegInfo().isPhysRegUsed(ARM::R4) &&
369 "No scratch register to restore SP from FP!");
370 emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::R4, FramePtr, -NumBytes,
372 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),
376 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),
380 if (MBBI->getOpcode() == ARM::tBX_RET &&
381 &MBB.front() != MBBI &&
382 std::prev(MBBI)->getOpcode() == ARM::tPOP) {
383 MachineBasicBlock::iterator PMBBI = std::prev(MBBI);
384 if (!tryFoldSPUpdateIntoPushPop(STI, MF, PMBBI, NumBytes))
385 emitSPUpdate(MBB, PMBBI, TII, dl, *RegInfo, NumBytes);
386 } else if (!tryFoldSPUpdateIntoPushPop(STI, MF, MBBI, NumBytes))
387 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, NumBytes);
391 bool IsV4PopReturn = false;
392 for (const CalleeSavedInfo &CSI : MFI->getCalleeSavedInfo())
393 if (CSI.getReg() == ARM::LR)
394 IsV4PopReturn = true;
395 IsV4PopReturn &= STI.hasV4TOps() && !STI.hasV5TOps();
397 // Unlike T2 and ARM mode, the T1 pop instruction cannot restore
398 // to LR, and we can't pop the value directly to the PC since
399 // we need to update the SP after popping the value. So instead
404 // If this would clobber a return value, then generate this sequence instead:
411 if (ArgRegsSaveSize || IsV4PopReturn) {
412 // Get the last instruction, tBX_RET
413 MBBI = MBB.getLastNonDebugInstr();
414 assert (MBBI->getOpcode() == ARM::tBX_RET);
415 DebugLoc dl = MBBI->getDebugLoc();
417 if (AFI->getReturnRegsCount() <= 3) {
418 // Epilogue: pop saved LR to R3 and branch off it.
419 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tPOP)))
420 .addReg(ARM::R3, RegState::Define);
422 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, ArgRegsSaveSize);
424 MachineInstrBuilder MIB =
425 BuildMI(MBB, MBBI, dl, TII.get(ARM::tBX))
426 .addReg(ARM::R3, RegState::Kill);
428 MIB.copyImplicitOps(&*MBBI);
429 // erase the old tBX_RET instruction
432 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr))
433 .addReg(ARM::R12, RegState::Define)
434 .addReg(ARM::R3, RegState::Kill));
436 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tPOP)))
437 .addReg(ARM::R3, RegState::Define);
439 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, ArgRegsSaveSize);
441 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr))
442 .addReg(ARM::LR, RegState::Define)
443 .addReg(ARM::R3, RegState::Kill));
445 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr))
446 .addReg(ARM::R3, RegState::Define)
447 .addReg(ARM::R12, RegState::Kill));
448 // Keep the tBX_RET instruction
453 bool Thumb1FrameLowering::
454 spillCalleeSavedRegisters(MachineBasicBlock &MBB,
455 MachineBasicBlock::iterator MI,
456 const std::vector<CalleeSavedInfo> &CSI,
457 const TargetRegisterInfo *TRI) const {
462 const TargetInstrInfo &TII = *STI.getInstrInfo();
464 if (MI != MBB.end()) DL = MI->getDebugLoc();
466 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(ARM::tPUSH));
468 for (unsigned i = CSI.size(); i != 0; --i) {
469 unsigned Reg = CSI[i-1].getReg();
472 // Add the callee-saved register as live-in unless it's LR and
473 // @llvm.returnaddress is called. If LR is returned for @llvm.returnaddress
474 // then it's already added to the function and entry block live-in sets.
475 if (Reg == ARM::LR) {
476 MachineFunction &MF = *MBB.getParent();
477 if (MF.getFrameInfo()->isReturnAddressTaken() &&
478 MF.getRegInfo().isLiveIn(Reg))
485 MIB.addReg(Reg, getKillRegState(isKill));
487 MIB.setMIFlags(MachineInstr::FrameSetup);
491 bool Thumb1FrameLowering::
492 restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
493 MachineBasicBlock::iterator MI,
494 const std::vector<CalleeSavedInfo> &CSI,
495 const TargetRegisterInfo *TRI) const {
499 MachineFunction &MF = *MBB.getParent();
500 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
501 const TargetInstrInfo &TII = *STI.getInstrInfo();
503 bool isVarArg = AFI->getArgRegsSaveSize() > 0;
504 DebugLoc DL = MI->getDebugLoc();
505 MachineInstrBuilder MIB = BuildMI(MF, DL, TII.get(ARM::tPOP));
508 bool NumRegs = false;
509 for (unsigned i = CSI.size(); i != 0; --i) {
510 unsigned Reg = CSI[i-1].getReg();
511 if (Reg == ARM::LR) {
512 // Special epilogue for vararg functions. See emitEpilogue
515 // ARMv4T requires BX, see emitEpilogue
516 if (STI.hasV4TOps() && !STI.hasV5TOps())
519 (*MIB).setDesc(TII.get(ARM::tPOP_RET));
520 MIB.copyImplicitOps(&*MI);
523 MIB.addReg(Reg, getDefRegState(true));
527 // It's illegal to emit pop instruction without operands.
529 MBB.insert(MI, &*MIB);
531 MF.DeleteMachineInstr(MIB);