1 //===-- Thumb1FrameLowering.cpp - Thumb1 Frame Information ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Thumb1 implementation of TargetFrameLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "Thumb1FrameLowering.h"
15 #include "ARMMachineFunctionInfo.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 bool Thumb1FrameLowering::hasReservedCallFrame(const MachineFunction &MF) const{
24 const MachineFrameInfo *FFI = MF.getFrameInfo();
25 unsigned CFSize = FFI->getMaxCallFrameSize();
26 // It's not always a good idea to include the call frame as part of the
27 // stack frame. ARM (especially Thumb) has small immediate offset to
28 // address the stack frame. So a large call frame can cause poor codegen
29 // and may even makes it impossible to scavenge a register.
30 if (CFSize >= ((1 << 8) - 1) * 4 / 2) // Half of imm8 * 4
33 return !MF.getFrameInfo()->hasVarSizedObjects();
37 emitSPUpdate(MachineBasicBlock &MBB,
38 MachineBasicBlock::iterator &MBBI,
39 const TargetInstrInfo &TII, DebugLoc dl,
40 const Thumb1RegisterInfo &MRI,
41 int NumBytes, unsigned MIFlags = MachineInstr::NoFlags) {
42 emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, TII,
47 void Thumb1FrameLowering::
48 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
49 MachineBasicBlock::iterator I) const {
50 const Thumb1InstrInfo &TII =
51 *static_cast<const Thumb1InstrInfo*>(MF.getTarget().getInstrInfo());
52 const Thumb1RegisterInfo *RegInfo =
53 static_cast<const Thumb1RegisterInfo*>(MF.getTarget().getRegisterInfo());
54 if (!hasReservedCallFrame(MF)) {
55 // If we have alloca, convert as follows:
56 // ADJCALLSTACKDOWN -> sub, sp, sp, amount
57 // ADJCALLSTACKUP -> add, sp, sp, amount
58 MachineInstr *Old = I;
59 DebugLoc dl = Old->getDebugLoc();
60 unsigned Amount = Old->getOperand(0).getImm();
62 // We need to keep the stack aligned properly. To do this, we round the
63 // amount of space needed for the outgoing arguments up to the next
64 // alignment boundary.
65 unsigned Align = getStackAlignment();
66 Amount = (Amount+Align-1)/Align*Align;
68 // Replace the pseudo instruction with a new instruction...
69 unsigned Opc = Old->getOpcode();
70 if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
71 emitSPUpdate(MBB, I, TII, dl, *RegInfo, -Amount);
73 assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
74 emitSPUpdate(MBB, I, TII, dl, *RegInfo, Amount);
81 void Thumb1FrameLowering::emitPrologue(MachineFunction &MF) const {
82 MachineBasicBlock &MBB = MF.front();
83 MachineBasicBlock::iterator MBBI = MBB.begin();
84 MachineFrameInfo *MFI = MF.getFrameInfo();
85 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
86 const Thumb1RegisterInfo *RegInfo =
87 static_cast<const Thumb1RegisterInfo*>(MF.getTarget().getRegisterInfo());
88 const Thumb1InstrInfo &TII =
89 *static_cast<const Thumb1InstrInfo*>(MF.getTarget().getInstrInfo());
91 unsigned Align = MF.getTarget().getFrameLowering()->getStackAlignment();
92 unsigned ArgRegsSaveSize = AFI->getArgRegsSaveSize(Align);
93 unsigned NumBytes = MFI->getStackSize();
94 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
95 DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
96 unsigned FramePtr = RegInfo->getFrameRegister(MF);
97 unsigned BasePtr = RegInfo->getBaseRegister();
99 // Thumb add/sub sp, imm8 instructions implicitly multiply the offset by 4.
100 NumBytes = (NumBytes + 3) & ~3;
101 MFI->setStackSize(NumBytes);
103 // Determine the sizes of each callee-save spill areas and record which frame
104 // belongs to which callee-save spill areas.
105 unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
106 int FramePtrSpillFI = 0;
109 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -ArgRegsSaveSize,
110 MachineInstr::FrameSetup);
112 if (!AFI->hasStackFrame()) {
114 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -NumBytes,
115 MachineInstr::FrameSetup);
119 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
120 unsigned Reg = CSI[i].getReg();
121 int FI = CSI[i].getFrameIdx();
129 FramePtrSpillFI = FI;
130 AFI->addGPRCalleeSavedArea1Frame(FI);
138 FramePtrSpillFI = FI;
139 if (STI.isTargetIOS()) {
140 AFI->addGPRCalleeSavedArea2Frame(FI);
143 AFI->addGPRCalleeSavedArea1Frame(FI);
148 AFI->addDPRCalleeSavedAreaFrame(FI);
153 if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPUSH) {
155 if (MBBI != MBB.end())
156 dl = MBBI->getDebugLoc();
159 // Determine starting offsets of spill areas.
160 unsigned DPRCSOffset = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize);
161 unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize;
162 unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size;
163 bool HasFP = hasFP(MF);
165 AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) +
167 AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
168 AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
169 AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
170 NumBytes = DPRCSOffset;
172 // Adjust FP so it point to the stack slot that contains the previous FP.
174 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tADDrSPi), FramePtr)
175 .addFrameIndex(FramePtrSpillFI).addImm(0)
176 .setMIFlags(MachineInstr::FrameSetup));
178 // If offset is > 508 then sp cannot be adjusted in a single instruction,
179 // try restoring from fp instead.
180 AFI->setShouldRestoreSPFromFP(true);
184 // Insert it after all the callee-save spills.
185 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -NumBytes,
186 MachineInstr::FrameSetup);
188 if (STI.isTargetELF() && HasFP)
189 MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() -
190 AFI->getFramePtrSpillOffset());
192 AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
193 AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
194 AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
196 // Thumb1 does not currently support dynamic stack realignment. Report a
197 // fatal error rather then silently generate bad code.
198 if (RegInfo->needsStackRealignment(MF))
199 report_fatal_error("Dynamic stack realignment not supported for thumb1.");
201 // If we need a base pointer, set it up here. It's whatever the value
202 // of the stack pointer is at this point. Any variable size objects
203 // will be allocated after this, so we can still use the base pointer
204 // to reference locals.
205 if (RegInfo->hasBasePointer(MF))
206 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), BasePtr)
209 // If the frame has variable sized objects then the epilogue must restore
210 // the sp from fp. We can assume there's an FP here since hasFP already
211 // checks for hasVarSizedObjects.
212 if (MFI->hasVarSizedObjects())
213 AFI->setShouldRestoreSPFromFP(true);
216 static bool isCalleeSavedRegister(unsigned Reg, const uint16_t *CSRegs) {
217 for (unsigned i = 0; CSRegs[i]; ++i)
218 if (Reg == CSRegs[i])
223 static bool isCSRestore(MachineInstr *MI, const uint16_t *CSRegs) {
224 if (MI->getOpcode() == ARM::tLDRspi &&
225 MI->getOperand(1).isFI() &&
226 isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs))
228 else if (MI->getOpcode() == ARM::tPOP) {
229 // The first two operands are predicates. The last two are
230 // imp-def and imp-use of SP. Check everything in between.
231 for (int i = 2, e = MI->getNumOperands() - 2; i != e; ++i)
232 if (!isCalleeSavedRegister(MI->getOperand(i).getReg(), CSRegs))
239 void Thumb1FrameLowering::emitEpilogue(MachineFunction &MF,
240 MachineBasicBlock &MBB) const {
241 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
242 assert((MBBI->getOpcode() == ARM::tBX_RET ||
243 MBBI->getOpcode() == ARM::tPOP_RET) &&
244 "Can only insert epilog into returning blocks");
245 DebugLoc dl = MBBI->getDebugLoc();
246 MachineFrameInfo *MFI = MF.getFrameInfo();
247 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
248 const Thumb1RegisterInfo *RegInfo =
249 static_cast<const Thumb1RegisterInfo*>(MF.getTarget().getRegisterInfo());
250 const Thumb1InstrInfo &TII =
251 *static_cast<const Thumb1InstrInfo*>(MF.getTarget().getInstrInfo());
253 unsigned Align = MF.getTarget().getFrameLowering()->getStackAlignment();
254 unsigned ArgRegsSaveSize = AFI->getArgRegsSaveSize(Align);
255 int NumBytes = (int)MFI->getStackSize();
256 const uint16_t *CSRegs = RegInfo->getCalleeSavedRegs();
257 unsigned FramePtr = RegInfo->getFrameRegister(MF);
259 if (!AFI->hasStackFrame()) {
261 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, NumBytes);
263 // Unwind MBBI to point to first LDR / VLDRD.
264 if (MBBI != MBB.begin()) {
267 while (MBBI != MBB.begin() && isCSRestore(MBBI, CSRegs));
268 if (!isCSRestore(MBBI, CSRegs))
272 // Move SP to start of FP callee save spill area.
273 NumBytes -= (AFI->getGPRCalleeSavedArea1Size() +
274 AFI->getGPRCalleeSavedArea2Size() +
275 AFI->getDPRCalleeSavedAreaSize());
277 if (AFI->shouldRestoreSPFromFP()) {
278 NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
279 // Reset SP based on frame pointer only if the stack frame extends beyond
280 // frame pointer stack slot, the target is ELF and the function has FP, or
281 // the target uses var sized objects.
283 assert(MF.getRegInfo().isPhysRegUsed(ARM::R4) &&
284 "No scratch register to restore SP from FP!");
285 emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::R4, FramePtr, -NumBytes,
287 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),
291 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),
295 if (MBBI->getOpcode() == ARM::tBX_RET &&
296 &MBB.front() != MBBI &&
297 prior(MBBI)->getOpcode() == ARM::tPOP) {
298 MachineBasicBlock::iterator PMBBI = prior(MBBI);
299 emitSPUpdate(MBB, PMBBI, TII, dl, *RegInfo, NumBytes);
301 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, NumBytes);
305 if (ArgRegsSaveSize) {
306 // Unlike T2 and ARM mode, the T1 pop instruction cannot restore
307 // to LR, and we can't pop the value directly to the PC since
308 // we need to update the SP after popping the value. Therefore, we
309 // pop the old LR into R3 as a temporary.
311 // Move back past the callee-saved register restoration
312 while (MBBI != MBB.end() && isCSRestore(MBBI, CSRegs))
314 // Epilogue for vararg functions: pop LR to R3 and branch off it.
315 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tPOP)))
316 .addReg(ARM::R3, RegState::Define);
318 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, ArgRegsSaveSize);
320 MachineInstrBuilder MIB =
321 BuildMI(MBB, MBBI, dl, TII.get(ARM::tBX_RET_vararg))
322 .addReg(ARM::R3, RegState::Kill);
324 MIB.copyImplicitOps(&*MBBI);
325 // erase the old tBX_RET instruction
330 bool Thumb1FrameLowering::
331 spillCalleeSavedRegisters(MachineBasicBlock &MBB,
332 MachineBasicBlock::iterator MI,
333 const std::vector<CalleeSavedInfo> &CSI,
334 const TargetRegisterInfo *TRI) const {
339 MachineFunction &MF = *MBB.getParent();
340 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
342 if (MI != MBB.end()) DL = MI->getDebugLoc();
344 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(ARM::tPUSH));
346 for (unsigned i = CSI.size(); i != 0; --i) {
347 unsigned Reg = CSI[i-1].getReg();
350 // Add the callee-saved register as live-in unless it's LR and
351 // @llvm.returnaddress is called. If LR is returned for @llvm.returnaddress
352 // then it's already added to the function and entry block live-in sets.
353 if (Reg == ARM::LR) {
354 MachineFunction &MF = *MBB.getParent();
355 if (MF.getFrameInfo()->isReturnAddressTaken() &&
356 MF.getRegInfo().isLiveIn(Reg))
363 MIB.addReg(Reg, getKillRegState(isKill));
365 MIB.setMIFlags(MachineInstr::FrameSetup);
369 bool Thumb1FrameLowering::
370 restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
371 MachineBasicBlock::iterator MI,
372 const std::vector<CalleeSavedInfo> &CSI,
373 const TargetRegisterInfo *TRI) const {
377 MachineFunction &MF = *MBB.getParent();
378 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
379 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
381 bool isVarArg = AFI->getArgRegsSaveSize() > 0;
382 DebugLoc DL = MI->getDebugLoc();
383 MachineInstrBuilder MIB = BuildMI(MF, DL, TII.get(ARM::tPOP));
386 bool NumRegs = false;
387 for (unsigned i = CSI.size(); i != 0; --i) {
388 unsigned Reg = CSI[i-1].getReg();
389 if (Reg == ARM::LR) {
390 // Special epilogue for vararg functions. See emitEpilogue
394 (*MIB).setDesc(TII.get(ARM::tPOP_RET));
395 MIB.copyImplicitOps(&*MI);
398 MIB.addReg(Reg, getDefRegState(true));
402 // It's illegal to emit pop instruction without operands.
404 MBB.insert(MI, &*MIB);
406 MF.DeleteMachineInstr(MIB);