1 //===-- Thumb1FrameLowering.cpp - Thumb1 Frame Information ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Thumb1 implementation of TargetFrameLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "Thumb1FrameLowering.h"
15 #include "ARMMachineFunctionInfo.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/MachineModuleInfo.h"
20 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 Thumb1FrameLowering::Thumb1FrameLowering(const ARMSubtarget &sti)
25 : ARMFrameLowering(sti) {}
27 bool Thumb1FrameLowering::hasReservedCallFrame(const MachineFunction &MF) const{
28 const MachineFrameInfo *FFI = MF.getFrameInfo();
29 unsigned CFSize = FFI->getMaxCallFrameSize();
30 // It's not always a good idea to include the call frame as part of the
31 // stack frame. ARM (especially Thumb) has small immediate offset to
32 // address the stack frame. So a large call frame can cause poor codegen
33 // and may even makes it impossible to scavenge a register.
34 if (CFSize >= ((1 << 8) - 1) * 4 / 2) // Half of imm8 * 4
37 return !MF.getFrameInfo()->hasVarSizedObjects();
41 emitSPUpdate(MachineBasicBlock &MBB,
42 MachineBasicBlock::iterator &MBBI,
43 const TargetInstrInfo &TII, DebugLoc dl,
44 const ThumbRegisterInfo &MRI,
45 int NumBytes, unsigned MIFlags = MachineInstr::NoFlags) {
46 emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, TII,
51 void Thumb1FrameLowering::
52 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
53 MachineBasicBlock::iterator I) const {
54 const Thumb1InstrInfo &TII =
55 *static_cast<const Thumb1InstrInfo *>(STI.getInstrInfo());
56 const ThumbRegisterInfo *RegInfo =
57 static_cast<const ThumbRegisterInfo *>(STI.getRegisterInfo());
58 if (!hasReservedCallFrame(MF)) {
59 // If we have alloca, convert as follows:
60 // ADJCALLSTACKDOWN -> sub, sp, sp, amount
61 // ADJCALLSTACKUP -> add, sp, sp, amount
62 MachineInstr *Old = I;
63 DebugLoc dl = Old->getDebugLoc();
64 unsigned Amount = Old->getOperand(0).getImm();
66 // We need to keep the stack aligned properly. To do this, we round the
67 // amount of space needed for the outgoing arguments up to the next
68 // alignment boundary.
69 unsigned Align = getStackAlignment();
70 Amount = (Amount+Align-1)/Align*Align;
72 // Replace the pseudo instruction with a new instruction...
73 unsigned Opc = Old->getOpcode();
74 if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
75 emitSPUpdate(MBB, I, TII, dl, *RegInfo, -Amount);
77 assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
78 emitSPUpdate(MBB, I, TII, dl, *RegInfo, Amount);
85 void Thumb1FrameLowering::emitPrologue(MachineFunction &MF) const {
86 MachineBasicBlock &MBB = MF.front();
87 MachineBasicBlock::iterator MBBI = MBB.begin();
88 MachineFrameInfo *MFI = MF.getFrameInfo();
89 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
90 MachineModuleInfo &MMI = MF.getMMI();
91 const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
92 const ThumbRegisterInfo *RegInfo =
93 static_cast<const ThumbRegisterInfo *>(STI.getRegisterInfo());
94 const Thumb1InstrInfo &TII =
95 *static_cast<const Thumb1InstrInfo *>(STI.getInstrInfo());
97 unsigned ArgRegsSaveSize = AFI->getArgRegsSaveSize();
98 unsigned NumBytes = MFI->getStackSize();
99 assert(NumBytes >= ArgRegsSaveSize &&
100 "ArgRegsSaveSize is included in NumBytes");
101 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
102 DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
103 unsigned FramePtr = RegInfo->getFrameRegister(MF);
104 unsigned BasePtr = RegInfo->getBaseRegister();
107 // Thumb add/sub sp, imm8 instructions implicitly multiply the offset by 4.
108 NumBytes = (NumBytes + 3) & ~3;
109 MFI->setStackSize(NumBytes);
111 // Determine the sizes of each callee-save spill areas and record which frame
112 // belongs to which callee-save spill areas.
113 unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
114 int FramePtrSpillFI = 0;
116 if (ArgRegsSaveSize) {
117 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -ArgRegsSaveSize,
118 MachineInstr::FrameSetup);
119 CFAOffset -= ArgRegsSaveSize;
120 unsigned CFIIndex = MMI.addFrameInst(
121 MCCFIInstruction::createDefCfaOffset(nullptr, CFAOffset));
122 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
123 .addCFIIndex(CFIIndex)
124 .setMIFlags(MachineInstr::FrameSetup);
127 if (!AFI->hasStackFrame()) {
128 if (NumBytes - ArgRegsSaveSize != 0) {
129 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -(NumBytes - ArgRegsSaveSize),
130 MachineInstr::FrameSetup);
131 CFAOffset -= NumBytes - ArgRegsSaveSize;
132 unsigned CFIIndex = MMI.addFrameInst(
133 MCCFIInstruction::createDefCfaOffset(nullptr, CFAOffset));
134 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
135 .addCFIIndex(CFIIndex)
136 .setMIFlags(MachineInstr::FrameSetup);
141 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
142 unsigned Reg = CSI[i].getReg();
143 int FI = CSI[i].getFrameIdx();
149 if (STI.isTargetMachO()) {
160 FramePtrSpillFI = FI;
168 if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPUSH) {
170 if (MBBI != MBB.end())
171 dl = MBBI->getDebugLoc();
174 // Determine starting offsets of spill areas.
175 unsigned DPRCSOffset = NumBytes - ArgRegsSaveSize - (GPRCS1Size + GPRCS2Size + DPRCSSize);
176 unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize;
177 unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size;
178 bool HasFP = hasFP(MF);
180 AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) +
182 AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
183 AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
184 AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
185 NumBytes = DPRCSOffset;
187 int FramePtrOffsetInBlock = 0;
188 unsigned adjustedGPRCS1Size = GPRCS1Size;
189 if (tryFoldSPUpdateIntoPushPop(STI, MF, std::prev(MBBI), NumBytes)) {
190 FramePtrOffsetInBlock = NumBytes;
191 adjustedGPRCS1Size += NumBytes;
195 if (adjustedGPRCS1Size) {
196 CFAOffset -= adjustedGPRCS1Size;
197 unsigned CFIIndex = MMI.addFrameInst(
198 MCCFIInstruction::createDefCfaOffset(nullptr, CFAOffset));
199 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
200 .addCFIIndex(CFIIndex)
201 .setMIFlags(MachineInstr::FrameSetup);
203 for (std::vector<CalleeSavedInfo>::const_iterator I = CSI.begin(),
204 E = CSI.end(); I != E; ++I) {
205 unsigned Reg = I->getReg();
206 int FI = I->getFrameIdx();
213 if (STI.isTargetMachO())
225 unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset(
226 nullptr, MRI->getDwarfRegNum(Reg, true), MFI->getObjectOffset(FI)));
227 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
228 .addCFIIndex(CFIIndex)
229 .setMIFlags(MachineInstr::FrameSetup);
235 // Adjust FP so it point to the stack slot that contains the previous FP.
237 FramePtrOffsetInBlock += MFI->getObjectOffset(FramePtrSpillFI)
238 + GPRCS1Size + ArgRegsSaveSize;
239 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tADDrSPi), FramePtr)
240 .addReg(ARM::SP).addImm(FramePtrOffsetInBlock / 4)
241 .setMIFlags(MachineInstr::FrameSetup));
242 if(FramePtrOffsetInBlock) {
243 CFAOffset += FramePtrOffsetInBlock;
244 unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createDefCfa(
245 nullptr, MRI->getDwarfRegNum(FramePtr, true), CFAOffset));
246 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
247 .addCFIIndex(CFIIndex)
248 .setMIFlags(MachineInstr::FrameSetup);
251 MMI.addFrameInst(MCCFIInstruction::createDefCfaRegister(
252 nullptr, MRI->getDwarfRegNum(FramePtr, true)));
253 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
254 .addCFIIndex(CFIIndex)
255 .setMIFlags(MachineInstr::FrameSetup);
258 // If offset is > 508 then sp cannot be adjusted in a single instruction,
259 // try restoring from fp instead.
260 AFI->setShouldRestoreSPFromFP(true);
264 // Insert it after all the callee-save spills.
265 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -NumBytes,
266 MachineInstr::FrameSetup);
268 CFAOffset -= NumBytes;
269 unsigned CFIIndex = MMI.addFrameInst(
270 MCCFIInstruction::createDefCfaOffset(nullptr, CFAOffset));
271 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
272 .addCFIIndex(CFIIndex)
273 .setMIFlags(MachineInstr::FrameSetup);
277 if (STI.isTargetELF() && HasFP)
278 MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() -
279 AFI->getFramePtrSpillOffset());
281 AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
282 AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
283 AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
285 // Thumb1 does not currently support dynamic stack realignment. Report a
286 // fatal error rather then silently generate bad code.
287 if (RegInfo->needsStackRealignment(MF))
288 report_fatal_error("Dynamic stack realignment not supported for thumb1.");
290 // If we need a base pointer, set it up here. It's whatever the value
291 // of the stack pointer is at this point. Any variable size objects
292 // will be allocated after this, so we can still use the base pointer
293 // to reference locals.
294 if (RegInfo->hasBasePointer(MF))
295 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), BasePtr)
298 // If the frame has variable sized objects then the epilogue must restore
299 // the sp from fp. We can assume there's an FP here since hasFP already
300 // checks for hasVarSizedObjects.
301 if (MFI->hasVarSizedObjects())
302 AFI->setShouldRestoreSPFromFP(true);
305 static bool isCSRestore(MachineInstr *MI, const MCPhysReg *CSRegs) {
306 if (MI->getOpcode() == ARM::tLDRspi &&
307 MI->getOperand(1).isFI() &&
308 isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs))
310 else if (MI->getOpcode() == ARM::tPOP) {
311 // The first two operands are predicates. The last two are
312 // imp-def and imp-use of SP. Check everything in between.
313 for (int i = 2, e = MI->getNumOperands() - 2; i != e; ++i)
314 if (!isCalleeSavedRegister(MI->getOperand(i).getReg(), CSRegs))
321 void Thumb1FrameLowering::emitEpilogue(MachineFunction &MF,
322 MachineBasicBlock &MBB) const {
323 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
324 assert((MBBI->getOpcode() == ARM::tBX_RET ||
325 MBBI->getOpcode() == ARM::tPOP_RET) &&
326 "Can only insert epilog into returning blocks");
327 DebugLoc dl = MBBI->getDebugLoc();
328 MachineFrameInfo *MFI = MF.getFrameInfo();
329 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
330 const ThumbRegisterInfo *RegInfo =
331 static_cast<const ThumbRegisterInfo *>(STI.getRegisterInfo());
332 const Thumb1InstrInfo &TII =
333 *static_cast<const Thumb1InstrInfo *>(STI.getInstrInfo());
335 unsigned ArgRegsSaveSize = AFI->getArgRegsSaveSize();
336 int NumBytes = (int)MFI->getStackSize();
337 assert((unsigned)NumBytes >= ArgRegsSaveSize &&
338 "ArgRegsSaveSize is included in NumBytes");
339 const MCPhysReg *CSRegs = RegInfo->getCalleeSavedRegs(&MF);
340 unsigned FramePtr = RegInfo->getFrameRegister(MF);
342 if (!AFI->hasStackFrame()) {
343 if (NumBytes - ArgRegsSaveSize != 0)
344 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, NumBytes - ArgRegsSaveSize);
346 // Unwind MBBI to point to first LDR / VLDRD.
347 if (MBBI != MBB.begin()) {
350 while (MBBI != MBB.begin() && isCSRestore(MBBI, CSRegs));
351 if (!isCSRestore(MBBI, CSRegs))
355 // Move SP to start of FP callee save spill area.
356 NumBytes -= (AFI->getGPRCalleeSavedArea1Size() +
357 AFI->getGPRCalleeSavedArea2Size() +
358 AFI->getDPRCalleeSavedAreaSize() +
361 if (AFI->shouldRestoreSPFromFP()) {
362 NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
363 // Reset SP based on frame pointer only if the stack frame extends beyond
364 // frame pointer stack slot, the target is ELF and the function has FP, or
365 // the target uses var sized objects.
367 assert(MF.getRegInfo().isPhysRegUsed(ARM::R4) &&
368 "No scratch register to restore SP from FP!");
369 emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::R4, FramePtr, -NumBytes,
371 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),
375 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),
379 if (MBBI->getOpcode() == ARM::tBX_RET &&
380 &MBB.front() != MBBI &&
381 std::prev(MBBI)->getOpcode() == ARM::tPOP) {
382 MachineBasicBlock::iterator PMBBI = std::prev(MBBI);
383 if (!tryFoldSPUpdateIntoPushPop(STI, MF, PMBBI, NumBytes))
384 emitSPUpdate(MBB, PMBBI, TII, dl, *RegInfo, NumBytes);
385 } else if (!tryFoldSPUpdateIntoPushPop(STI, MF, MBBI, NumBytes))
386 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, NumBytes);
390 bool IsV4PopReturn = false;
391 for (const CalleeSavedInfo &CSI : MFI->getCalleeSavedInfo())
392 if (CSI.getReg() == ARM::LR)
393 IsV4PopReturn = true;
394 IsV4PopReturn &= STI.hasV4TOps() && !STI.hasV5TOps();
396 // Unlike T2 and ARM mode, the T1 pop instruction cannot restore
397 // to LR, and we can't pop the value directly to the PC since
398 // we need to update the SP after popping the value. So instead
403 // If this would clobber a return value, then generate this sequence instead:
410 if (ArgRegsSaveSize || IsV4PopReturn) {
411 // Get the last instruction, tBX_RET
412 MBBI = MBB.getLastNonDebugInstr();
413 assert (MBBI->getOpcode() == ARM::tBX_RET);
414 DebugLoc dl = MBBI->getDebugLoc();
416 if (AFI->getReturnRegsCount() <= 3) {
417 // Epilogue: pop saved LR to R3 and branch off it.
418 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tPOP)))
419 .addReg(ARM::R3, RegState::Define);
421 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, ArgRegsSaveSize);
423 MachineInstrBuilder MIB =
424 BuildMI(MBB, MBBI, dl, TII.get(ARM::tBX))
425 .addReg(ARM::R3, RegState::Kill);
427 MIB.copyImplicitOps(&*MBBI);
428 // erase the old tBX_RET instruction
431 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr))
432 .addReg(ARM::R12, RegState::Define)
433 .addReg(ARM::R3, RegState::Kill));
435 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tPOP)))
436 .addReg(ARM::R3, RegState::Define);
438 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, ArgRegsSaveSize);
440 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr))
441 .addReg(ARM::LR, RegState::Define)
442 .addReg(ARM::R3, RegState::Kill));
444 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr))
445 .addReg(ARM::R3, RegState::Define)
446 .addReg(ARM::R12, RegState::Kill));
447 // Keep the tBX_RET instruction
452 bool Thumb1FrameLowering::
453 spillCalleeSavedRegisters(MachineBasicBlock &MBB,
454 MachineBasicBlock::iterator MI,
455 const std::vector<CalleeSavedInfo> &CSI,
456 const TargetRegisterInfo *TRI) const {
461 const TargetInstrInfo &TII = *STI.getInstrInfo();
463 if (MI != MBB.end()) DL = MI->getDebugLoc();
465 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(ARM::tPUSH));
467 for (unsigned i = CSI.size(); i != 0; --i) {
468 unsigned Reg = CSI[i-1].getReg();
471 // Add the callee-saved register as live-in unless it's LR and
472 // @llvm.returnaddress is called. If LR is returned for @llvm.returnaddress
473 // then it's already added to the function and entry block live-in sets.
474 if (Reg == ARM::LR) {
475 MachineFunction &MF = *MBB.getParent();
476 if (MF.getFrameInfo()->isReturnAddressTaken() &&
477 MF.getRegInfo().isLiveIn(Reg))
484 MIB.addReg(Reg, getKillRegState(isKill));
486 MIB.setMIFlags(MachineInstr::FrameSetup);
490 bool Thumb1FrameLowering::
491 restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
492 MachineBasicBlock::iterator MI,
493 const std::vector<CalleeSavedInfo> &CSI,
494 const TargetRegisterInfo *TRI) const {
498 MachineFunction &MF = *MBB.getParent();
499 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
500 const TargetInstrInfo &TII = *STI.getInstrInfo();
502 bool isVarArg = AFI->getArgRegsSaveSize() > 0;
503 DebugLoc DL = MI->getDebugLoc();
504 MachineInstrBuilder MIB = BuildMI(MF, DL, TII.get(ARM::tPOP));
507 bool NumRegs = false;
508 for (unsigned i = CSI.size(); i != 0; --i) {
509 unsigned Reg = CSI[i-1].getReg();
510 if (Reg == ARM::LR) {
511 // Special epilogue for vararg functions. See emitEpilogue
514 // ARMv4T requires BX, see emitEpilogue
515 if (STI.hasV4TOps() && !STI.hasV5TOps())
518 (*MIB).setDesc(TII.get(ARM::tPOP_RET));
519 MIB.copyImplicitOps(&*MI);
522 MIB.addReg(Reg, getDefRegState(true));
526 // It's illegal to emit pop instruction without operands.
528 MBB.insert(MI, &*MIB);
530 MF.DeleteMachineInstr(MIB);