1 //===-- Thumb1FrameLowering.cpp - Thumb1 Frame Information ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Thumb1 implementation of TargetFrameLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "Thumb1FrameLowering.h"
15 #include "ARMMachineFunctionInfo.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/MachineModuleInfo.h"
20 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 bool Thumb1FrameLowering::hasReservedCallFrame(const MachineFunction &MF) const{
25 const MachineFrameInfo *FFI = MF.getFrameInfo();
26 unsigned CFSize = FFI->getMaxCallFrameSize();
27 // It's not always a good idea to include the call frame as part of the
28 // stack frame. ARM (especially Thumb) has small immediate offset to
29 // address the stack frame. So a large call frame can cause poor codegen
30 // and may even makes it impossible to scavenge a register.
31 if (CFSize >= ((1 << 8) - 1) * 4 / 2) // Half of imm8 * 4
34 return !MF.getFrameInfo()->hasVarSizedObjects();
38 emitSPUpdate(MachineBasicBlock &MBB,
39 MachineBasicBlock::iterator &MBBI,
40 const TargetInstrInfo &TII, DebugLoc dl,
41 const Thumb1RegisterInfo &MRI,
42 int NumBytes, unsigned MIFlags = MachineInstr::NoFlags) {
43 emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, TII,
48 void Thumb1FrameLowering::
49 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
50 MachineBasicBlock::iterator I) const {
51 const Thumb1InstrInfo &TII =
52 *static_cast<const Thumb1InstrInfo*>(MF.getTarget().getInstrInfo());
53 const Thumb1RegisterInfo *RegInfo =
54 static_cast<const Thumb1RegisterInfo*>(MF.getTarget().getRegisterInfo());
55 if (!hasReservedCallFrame(MF)) {
56 // If we have alloca, convert as follows:
57 // ADJCALLSTACKDOWN -> sub, sp, sp, amount
58 // ADJCALLSTACKUP -> add, sp, sp, amount
59 MachineInstr *Old = I;
60 DebugLoc dl = Old->getDebugLoc();
61 unsigned Amount = Old->getOperand(0).getImm();
63 // We need to keep the stack aligned properly. To do this, we round the
64 // amount of space needed for the outgoing arguments up to the next
65 // alignment boundary.
66 unsigned Align = getStackAlignment();
67 Amount = (Amount+Align-1)/Align*Align;
69 // Replace the pseudo instruction with a new instruction...
70 unsigned Opc = Old->getOpcode();
71 if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
72 emitSPUpdate(MBB, I, TII, dl, *RegInfo, -Amount);
74 assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
75 emitSPUpdate(MBB, I, TII, dl, *RegInfo, Amount);
82 void Thumb1FrameLowering::emitPrologue(MachineFunction &MF) const {
83 MachineBasicBlock &MBB = MF.front();
84 MachineBasicBlock::iterator MBBI = MBB.begin();
85 MachineFrameInfo *MFI = MF.getFrameInfo();
86 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
87 MachineModuleInfo &MMI = MF.getMMI();
88 const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
89 const Thumb1RegisterInfo *RegInfo =
90 static_cast<const Thumb1RegisterInfo*>(MF.getTarget().getRegisterInfo());
91 const Thumb1InstrInfo &TII =
92 *static_cast<const Thumb1InstrInfo*>(MF.getTarget().getInstrInfo());
94 unsigned Align = MF.getTarget().getFrameLowering()->getStackAlignment();
95 unsigned ArgRegsSaveSize = AFI->getArgRegsSaveSize(Align);
96 unsigned NumBytes = MFI->getStackSize();
97 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
98 DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
99 unsigned FramePtr = RegInfo->getFrameRegister(MF);
100 unsigned BasePtr = RegInfo->getBaseRegister();
103 // Thumb add/sub sp, imm8 instructions implicitly multiply the offset by 4.
104 NumBytes = (NumBytes + 3) & ~3;
105 MFI->setStackSize(NumBytes);
107 // Determine the sizes of each callee-save spill areas and record which frame
108 // belongs to which callee-save spill areas.
109 unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
110 int FramePtrSpillFI = 0;
112 if (ArgRegsSaveSize) {
113 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -ArgRegsSaveSize,
114 MachineInstr::FrameSetup);
115 MCSymbol *SPLabel = MMI.getContext().CreateTempSymbol();
116 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::PROLOG_LABEL))
118 CFAOffset -= ArgRegsSaveSize;
120 MCCFIInstruction::createDefCfaOffset(SPLabel, CFAOffset));
123 if (!AFI->hasStackFrame()) {
125 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -NumBytes,
126 MachineInstr::FrameSetup);
127 MCSymbol *SPLabel = MMI.getContext().CreateTempSymbol();
128 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::PROLOG_LABEL))
130 CFAOffset -= NumBytes;
132 MCCFIInstruction::createDefCfaOffset(SPLabel, CFAOffset));
137 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
138 unsigned Reg = CSI[i].getReg();
139 int FI = CSI[i].getFrameIdx();
145 if (STI.isTargetMachO()) {
156 FramePtrSpillFI = FI;
164 if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPUSH) {
166 if (MBBI != MBB.end())
167 dl = MBBI->getDebugLoc();
170 // Determine starting offsets of spill areas.
171 unsigned DPRCSOffset = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize);
172 unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize;
173 unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size;
174 bool HasFP = hasFP(MF);
176 AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) +
178 AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
179 AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
180 AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
181 NumBytes = DPRCSOffset;
183 int FramePtrOffsetInBlock = 0;
184 unsigned adjustedGPRCS1Size = GPRCS1Size;
185 if (tryFoldSPUpdateIntoPushPop(STI, MF, prior(MBBI), NumBytes)) {
186 FramePtrOffsetInBlock = NumBytes;
187 adjustedGPRCS1Size += NumBytes;
191 MCSymbol *SPLabel = MMI.getContext().CreateTempSymbol();
192 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::PROLOG_LABEL)).addSym(SPLabel);
193 if (adjustedGPRCS1Size) {
194 CFAOffset -= adjustedGPRCS1Size;
196 MCCFIInstruction::createDefCfaOffset(SPLabel, CFAOffset));
198 for (std::vector<CalleeSavedInfo>::const_iterator I = CSI.begin(),
199 E = CSI.end(); I != E; ++I) {
200 unsigned Reg = I->getReg();
201 int FI = I->getFrameIdx();
208 if (STI.isTargetMachO())
220 MMI.addFrameInst(MCCFIInstruction::createOffset(SPLabel,
221 MRI->getDwarfRegNum(Reg, true),
222 MFI->getObjectOffset(FI) - ArgRegsSaveSize));
228 // Adjust FP so it point to the stack slot that contains the previous FP.
230 FramePtrOffsetInBlock += MFI->getObjectOffset(FramePtrSpillFI) + GPRCS1Size;
231 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tADDrSPi), FramePtr)
232 .addReg(ARM::SP).addImm(FramePtrOffsetInBlock / 4)
233 .setMIFlags(MachineInstr::FrameSetup));
234 MCSymbol *SPLabel = MMI.getContext().CreateTempSymbol();
235 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::PROLOG_LABEL))
237 if(FramePtrOffsetInBlock) {
238 CFAOffset += FramePtrOffsetInBlock;
240 MCCFIInstruction::createDefCfa(SPLabel,
241 MRI->getDwarfRegNum(FramePtr, true), CFAOffset));
244 MCCFIInstruction::createDefCfaRegister(SPLabel,
245 MRI->getDwarfRegNum(FramePtr, true)));
247 // If offset is > 508 then sp cannot be adjusted in a single instruction,
248 // try restoring from fp instead.
249 AFI->setShouldRestoreSPFromFP(true);
253 // Insert it after all the callee-save spills.
254 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -NumBytes,
255 MachineInstr::FrameSetup);
257 MCSymbol *SPLabel = MMI.getContext().CreateTempSymbol();
258 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::PROLOG_LABEL))
260 CFAOffset -= NumBytes;
262 MCCFIInstruction::createDefCfaOffset(SPLabel, CFAOffset));
266 if (STI.isTargetELF() && HasFP)
267 MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() -
268 AFI->getFramePtrSpillOffset());
270 AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
271 AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
272 AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
274 // Thumb1 does not currently support dynamic stack realignment. Report a
275 // fatal error rather then silently generate bad code.
276 if (RegInfo->needsStackRealignment(MF))
277 report_fatal_error("Dynamic stack realignment not supported for thumb1.");
279 // If we need a base pointer, set it up here. It's whatever the value
280 // of the stack pointer is at this point. Any variable size objects
281 // will be allocated after this, so we can still use the base pointer
282 // to reference locals.
283 if (RegInfo->hasBasePointer(MF))
284 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), BasePtr)
287 // If the frame has variable sized objects then the epilogue must restore
288 // the sp from fp. We can assume there's an FP here since hasFP already
289 // checks for hasVarSizedObjects.
290 if (MFI->hasVarSizedObjects())
291 AFI->setShouldRestoreSPFromFP(true);
294 static bool isCSRestore(MachineInstr *MI, const uint16_t *CSRegs) {
295 if (MI->getOpcode() == ARM::tLDRspi &&
296 MI->getOperand(1).isFI() &&
297 isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs))
299 else if (MI->getOpcode() == ARM::tPOP) {
300 // The first two operands are predicates. The last two are
301 // imp-def and imp-use of SP. Check everything in between.
302 for (int i = 2, e = MI->getNumOperands() - 2; i != e; ++i)
303 if (!isCalleeSavedRegister(MI->getOperand(i).getReg(), CSRegs))
310 void Thumb1FrameLowering::emitEpilogue(MachineFunction &MF,
311 MachineBasicBlock &MBB) const {
312 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
313 assert((MBBI->getOpcode() == ARM::tBX_RET ||
314 MBBI->getOpcode() == ARM::tPOP_RET) &&
315 "Can only insert epilog into returning blocks");
316 DebugLoc dl = MBBI->getDebugLoc();
317 MachineFrameInfo *MFI = MF.getFrameInfo();
318 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
319 const Thumb1RegisterInfo *RegInfo =
320 static_cast<const Thumb1RegisterInfo*>(MF.getTarget().getRegisterInfo());
321 const Thumb1InstrInfo &TII =
322 *static_cast<const Thumb1InstrInfo*>(MF.getTarget().getInstrInfo());
324 unsigned Align = MF.getTarget().getFrameLowering()->getStackAlignment();
325 unsigned ArgRegsSaveSize = AFI->getArgRegsSaveSize(Align);
326 int NumBytes = (int)MFI->getStackSize();
327 const uint16_t *CSRegs = RegInfo->getCalleeSavedRegs();
328 unsigned FramePtr = RegInfo->getFrameRegister(MF);
330 if (!AFI->hasStackFrame()) {
332 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, NumBytes);
334 // Unwind MBBI to point to first LDR / VLDRD.
335 if (MBBI != MBB.begin()) {
338 while (MBBI != MBB.begin() && isCSRestore(MBBI, CSRegs));
339 if (!isCSRestore(MBBI, CSRegs))
343 // Move SP to start of FP callee save spill area.
344 NumBytes -= (AFI->getGPRCalleeSavedArea1Size() +
345 AFI->getGPRCalleeSavedArea2Size() +
346 AFI->getDPRCalleeSavedAreaSize());
348 if (AFI->shouldRestoreSPFromFP()) {
349 NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
350 // Reset SP based on frame pointer only if the stack frame extends beyond
351 // frame pointer stack slot, the target is ELF and the function has FP, or
352 // the target uses var sized objects.
354 assert(MF.getRegInfo().isPhysRegUsed(ARM::R4) &&
355 "No scratch register to restore SP from FP!");
356 emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::R4, FramePtr, -NumBytes,
358 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),
362 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),
366 if (MBBI->getOpcode() == ARM::tBX_RET &&
367 &MBB.front() != MBBI &&
368 prior(MBBI)->getOpcode() == ARM::tPOP) {
369 MachineBasicBlock::iterator PMBBI = prior(MBBI);
370 if (!tryFoldSPUpdateIntoPushPop(STI, MF, PMBBI, NumBytes))
371 emitSPUpdate(MBB, PMBBI, TII, dl, *RegInfo, NumBytes);
372 } else if (!tryFoldSPUpdateIntoPushPop(STI, MF, MBBI, NumBytes))
373 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, NumBytes);
377 if (ArgRegsSaveSize) {
378 // Unlike T2 and ARM mode, the T1 pop instruction cannot restore
379 // to LR, and we can't pop the value directly to the PC since
380 // we need to update the SP after popping the value. Therefore, we
381 // pop the old LR into R3 as a temporary.
383 // Get the last instruction, tBX_RET
384 MBBI = MBB.getLastNonDebugInstr();
385 assert (MBBI->getOpcode() == ARM::tBX_RET);
386 // Epilogue for vararg functions: pop LR to R3 and branch off it.
387 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tPOP)))
388 .addReg(ARM::R3, RegState::Define);
390 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, ArgRegsSaveSize);
392 MachineInstrBuilder MIB =
393 BuildMI(MBB, MBBI, dl, TII.get(ARM::tBX_RET_vararg))
394 .addReg(ARM::R3, RegState::Kill);
396 MIB.copyImplicitOps(&*MBBI);
397 // erase the old tBX_RET instruction
402 bool Thumb1FrameLowering::
403 spillCalleeSavedRegisters(MachineBasicBlock &MBB,
404 MachineBasicBlock::iterator MI,
405 const std::vector<CalleeSavedInfo> &CSI,
406 const TargetRegisterInfo *TRI) const {
411 MachineFunction &MF = *MBB.getParent();
412 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
414 if (MI != MBB.end()) DL = MI->getDebugLoc();
416 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(ARM::tPUSH));
418 for (unsigned i = CSI.size(); i != 0; --i) {
419 unsigned Reg = CSI[i-1].getReg();
422 // Add the callee-saved register as live-in unless it's LR and
423 // @llvm.returnaddress is called. If LR is returned for @llvm.returnaddress
424 // then it's already added to the function and entry block live-in sets.
425 if (Reg == ARM::LR) {
426 MachineFunction &MF = *MBB.getParent();
427 if (MF.getFrameInfo()->isReturnAddressTaken() &&
428 MF.getRegInfo().isLiveIn(Reg))
435 MIB.addReg(Reg, getKillRegState(isKill));
437 MIB.setMIFlags(MachineInstr::FrameSetup);
441 bool Thumb1FrameLowering::
442 restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
443 MachineBasicBlock::iterator MI,
444 const std::vector<CalleeSavedInfo> &CSI,
445 const TargetRegisterInfo *TRI) const {
449 MachineFunction &MF = *MBB.getParent();
450 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
451 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
453 bool isVarArg = AFI->getArgRegsSaveSize() > 0;
454 DebugLoc DL = MI->getDebugLoc();
455 MachineInstrBuilder MIB = BuildMI(MF, DL, TII.get(ARM::tPOP));
458 bool NumRegs = false;
459 for (unsigned i = CSI.size(); i != 0; --i) {
460 unsigned Reg = CSI[i-1].getReg();
461 if (Reg == ARM::LR) {
462 // Special epilogue for vararg functions. See emitEpilogue
466 (*MIB).setDesc(TII.get(ARM::tPOP_RET));
467 MIB.copyImplicitOps(&*MI);
470 MIB.addReg(Reg, getDefRegState(true));
474 // It's illegal to emit pop instruction without operands.
476 MBB.insert(MI, &*MIB);
478 MF.DeleteMachineInstr(MIB);