1 //===- Thumb1InstrInfo.cpp - Thumb-1 Instruction Information --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Thumb-1 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "ARMInstrInfo.h"
16 #include "ARMGenInstrInfo.inc"
17 #include "ARMMachineFunctionInfo.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/ADT/SmallVector.h"
21 #include "Thumb1InstrInfo.h"
25 Thumb1InstrInfo::Thumb1InstrInfo(const ARMSubtarget &STI) : RI(*this, STI) {
28 unsigned Thumb1InstrInfo::getUnindexedOpcode(unsigned Opc) const {
33 Thumb1InstrInfo::BlockHasNoFallThrough(const MachineBasicBlock &MBB) const {
34 if (MBB.empty()) return false;
36 switch (MBB.back().getOpcode()) {
38 case ARM::tBX_RET_vararg:
50 bool Thumb1InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
51 MachineBasicBlock::iterator I,
52 unsigned DestReg, unsigned SrcReg,
53 const TargetRegisterClass *DestRC,
54 const TargetRegisterClass *SrcRC) const {
55 DebugLoc DL = DebugLoc::getUnknownLoc();
56 if (I != MBB.end()) DL = I->getDebugLoc();
58 if (DestRC == ARM::GPRRegisterClass) {
59 if (SrcRC == ARM::GPRRegisterClass) {
60 BuildMI(MBB, I, DL, get(ARM::tMOVgpr2gpr), DestReg).addReg(SrcReg);
62 } else if (SrcRC == ARM::tGPRRegisterClass) {
63 BuildMI(MBB, I, DL, get(ARM::tMOVtgpr2gpr), DestReg).addReg(SrcReg);
66 } else if (DestRC == ARM::tGPRRegisterClass) {
67 if (SrcRC == ARM::GPRRegisterClass) {
68 BuildMI(MBB, I, DL, get(ARM::tMOVgpr2tgpr), DestReg).addReg(SrcReg);
70 } else if (SrcRC == ARM::tGPRRegisterClass) {
71 BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg).addReg(SrcReg);
79 bool Thumb1InstrInfo::
80 canFoldMemoryOperand(const MachineInstr *MI,
81 const SmallVectorImpl<unsigned> &Ops) const {
82 if (Ops.size() != 1) return false;
84 unsigned OpNum = Ops[0];
85 unsigned Opc = MI->getOpcode();
89 case ARM::tMOVtgpr2gpr:
90 case ARM::tMOVgpr2tgpr:
91 case ARM::tMOVgpr2gpr: {
92 if (OpNum == 0) { // move -> store
93 unsigned SrcReg = MI->getOperand(1).getReg();
94 if (RI.isPhysicalRegister(SrcReg) && !isARMLowRegister(SrcReg))
95 // tSpill cannot take a high register operand.
97 } else { // move -> load
98 unsigned DstReg = MI->getOperand(0).getReg();
99 if (RI.isPhysicalRegister(DstReg) && !isARMLowRegister(DstReg))
100 // tRestore cannot target a high register operand.
110 void Thumb1InstrInfo::
111 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
112 unsigned SrcReg, bool isKill, int FI,
113 const TargetRegisterClass *RC) const {
114 DebugLoc DL = DebugLoc::getUnknownLoc();
115 if (I != MBB.end()) DL = I->getDebugLoc();
117 assert(RC == ARM::tGPRRegisterClass && "Unknown regclass!");
119 if (RC == ARM::tGPRRegisterClass) {
120 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tSpill))
121 .addReg(SrcReg, getKillRegState(isKill))
122 .addFrameIndex(FI).addImm(0));
126 void Thumb1InstrInfo::
127 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
128 unsigned DestReg, int FI,
129 const TargetRegisterClass *RC) const {
130 DebugLoc DL = DebugLoc::getUnknownLoc();
131 if (I != MBB.end()) DL = I->getDebugLoc();
133 assert(RC == ARM::tGPRRegisterClass && "Unknown regclass!");
135 if (RC == ARM::tGPRRegisterClass) {
136 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tRestore), DestReg)
137 .addFrameIndex(FI).addImm(0));
141 bool Thumb1InstrInfo::
142 spillCalleeSavedRegisters(MachineBasicBlock &MBB,
143 MachineBasicBlock::iterator MI,
144 const std::vector<CalleeSavedInfo> &CSI) const {
148 DebugLoc DL = DebugLoc::getUnknownLoc();
149 if (MI != MBB.end()) DL = MI->getDebugLoc();
151 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, get(ARM::tPUSH));
152 for (unsigned i = CSI.size(); i != 0; --i) {
153 unsigned Reg = CSI[i-1].getReg();
154 // Add the callee-saved register as live-in. It's killed at the spill.
156 MIB.addReg(Reg, RegState::Kill);
161 bool Thumb1InstrInfo::
162 restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
163 MachineBasicBlock::iterator MI,
164 const std::vector<CalleeSavedInfo> &CSI) const {
165 MachineFunction &MF = *MBB.getParent();
166 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
170 bool isVarArg = AFI->getVarArgsRegSaveSize() > 0;
171 MachineInstr *PopMI = MF.CreateMachineInstr(get(ARM::tPOP),MI->getDebugLoc());
172 for (unsigned i = CSI.size(); i != 0; --i) {
173 unsigned Reg = CSI[i-1].getReg();
174 if (Reg == ARM::LR) {
175 // Special epilogue for vararg functions. See emitEpilogue
179 PopMI->setDesc(get(ARM::tPOP_RET));
182 PopMI->addOperand(MachineOperand::CreateReg(Reg, true));
185 // It's illegal to emit pop instruction without operands.
186 if (PopMI->getNumOperands() > 0)
187 MBB.insert(MI, PopMI);
192 MachineInstr *Thumb1InstrInfo::
193 foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
194 const SmallVectorImpl<unsigned> &Ops, int FI) const {
195 if (Ops.size() != 1) return NULL;
197 unsigned OpNum = Ops[0];
198 unsigned Opc = MI->getOpcode();
199 MachineInstr *NewMI = NULL;
203 case ARM::tMOVtgpr2gpr:
204 case ARM::tMOVgpr2tgpr:
205 case ARM::tMOVgpr2gpr: {
206 if (OpNum == 0) { // move -> store
207 unsigned SrcReg = MI->getOperand(1).getReg();
208 bool isKill = MI->getOperand(1).isKill();
209 if (RI.isPhysicalRegister(SrcReg) && !isARMLowRegister(SrcReg))
210 // tSpill cannot take a high register operand.
212 NewMI = AddDefaultPred(BuildMI(MF, MI->getDebugLoc(), get(ARM::tSpill))
213 .addReg(SrcReg, getKillRegState(isKill))
214 .addFrameIndex(FI).addImm(0));
215 } else { // move -> load
216 unsigned DstReg = MI->getOperand(0).getReg();
217 if (RI.isPhysicalRegister(DstReg) && !isARMLowRegister(DstReg))
218 // tRestore cannot target a high register operand.
220 bool isDead = MI->getOperand(0).isDead();
221 NewMI = AddDefaultPred(BuildMI(MF, MI->getDebugLoc(), get(ARM::tRestore))
223 RegState::Define | getDeadRegState(isDead))
224 .addFrameIndex(FI).addImm(0));