1 //===- Thumb1InstrInfo.cpp - Thumb-1 Instruction Information --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Thumb-1 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "Thumb1InstrInfo.h"
16 #include "ARMConstantPoolValue.h"
17 #include "ARMGenInstrInfo.inc"
18 #include "ARMMachineFunctionInfo.h"
19 #include "llvm/GlobalValue.h"
20 #include "llvm/CodeGen/MachineConstantPool.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineMemOperand.h"
24 #include "llvm/CodeGen/PseudoSourceValue.h"
25 #include "llvm/ADT/SmallVector.h"
26 #include "Thumb1InstrInfo.h"
30 Thumb1InstrInfo::Thumb1InstrInfo(const ARMSubtarget &STI)
31 : ARMBaseInstrInfo(STI), RI(*this, STI) {
34 unsigned Thumb1InstrInfo::getUnindexedOpcode(unsigned Opc) const {
39 Thumb1InstrInfo::BlockHasNoFallThrough(const MachineBasicBlock &MBB) const {
40 if (MBB.empty()) return false;
42 switch (MBB.back().getOpcode()) {
44 case ARM::tBX_RET_vararg:
57 bool Thumb1InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
58 MachineBasicBlock::iterator I,
59 unsigned DestReg, unsigned SrcReg,
60 const TargetRegisterClass *DestRC,
61 const TargetRegisterClass *SrcRC) const {
62 DebugLoc DL = DebugLoc::getUnknownLoc();
63 if (I != MBB.end()) DL = I->getDebugLoc();
65 if (DestRC == ARM::GPRRegisterClass) {
66 if (SrcRC == ARM::GPRRegisterClass) {
67 BuildMI(MBB, I, DL, get(ARM::tMOVgpr2gpr), DestReg).addReg(SrcReg);
69 } else if (SrcRC == ARM::tGPRRegisterClass) {
70 BuildMI(MBB, I, DL, get(ARM::tMOVtgpr2gpr), DestReg).addReg(SrcReg);
73 } else if (DestRC == ARM::tGPRRegisterClass) {
74 if (SrcRC == ARM::GPRRegisterClass) {
75 BuildMI(MBB, I, DL, get(ARM::tMOVgpr2tgpr), DestReg).addReg(SrcReg);
77 } else if (SrcRC == ARM::tGPRRegisterClass) {
78 BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg).addReg(SrcReg);
86 bool Thumb1InstrInfo::
87 canFoldMemoryOperand(const MachineInstr *MI,
88 const SmallVectorImpl<unsigned> &Ops) const {
89 if (Ops.size() != 1) return false;
91 unsigned OpNum = Ops[0];
92 unsigned Opc = MI->getOpcode();
96 case ARM::tMOVtgpr2gpr:
97 case ARM::tMOVgpr2tgpr:
98 case ARM::tMOVgpr2gpr: {
99 if (OpNum == 0) { // move -> store
100 unsigned SrcReg = MI->getOperand(1).getReg();
101 if (TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
102 !isARMLowRegister(SrcReg))
103 // tSpill cannot take a high register operand.
105 } else { // move -> load
106 unsigned DstReg = MI->getOperand(0).getReg();
107 if (TargetRegisterInfo::isPhysicalRegister(DstReg) &&
108 !isARMLowRegister(DstReg))
109 // tRestore cannot target a high register operand.
119 void Thumb1InstrInfo::
120 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
121 unsigned SrcReg, bool isKill, int FI,
122 const TargetRegisterClass *RC) const {
123 DebugLoc DL = DebugLoc::getUnknownLoc();
124 if (I != MBB.end()) DL = I->getDebugLoc();
126 assert((RC == ARM::tGPRRegisterClass ||
127 (TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
128 isARMLowRegister(SrcReg))) && "Unknown regclass!");
130 if (RC == ARM::tGPRRegisterClass) {
131 MachineFunction &MF = *MBB.getParent();
132 MachineFrameInfo &MFI = *MF.getFrameInfo();
133 MachineMemOperand *MMO =
134 MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI),
135 MachineMemOperand::MOStore, 0,
136 MFI.getObjectSize(FI),
137 MFI.getObjectAlignment(FI));
138 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tSpill))
139 .addReg(SrcReg, getKillRegState(isKill))
140 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
144 void Thumb1InstrInfo::
145 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
146 unsigned DestReg, int FI,
147 const TargetRegisterClass *RC) const {
148 DebugLoc DL = DebugLoc::getUnknownLoc();
149 if (I != MBB.end()) DL = I->getDebugLoc();
151 assert((RC == ARM::tGPRRegisterClass ||
152 (TargetRegisterInfo::isPhysicalRegister(DestReg) &&
153 isARMLowRegister(DestReg))) && "Unknown regclass!");
155 if (RC == ARM::tGPRRegisterClass) {
156 MachineFunction &MF = *MBB.getParent();
157 MachineFrameInfo &MFI = *MF.getFrameInfo();
158 MachineMemOperand *MMO =
159 MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI),
160 MachineMemOperand::MOLoad, 0,
161 MFI.getObjectSize(FI),
162 MFI.getObjectAlignment(FI));
163 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tRestore), DestReg)
164 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
168 bool Thumb1InstrInfo::
169 spillCalleeSavedRegisters(MachineBasicBlock &MBB,
170 MachineBasicBlock::iterator MI,
171 const std::vector<CalleeSavedInfo> &CSI) const {
175 DebugLoc DL = DebugLoc::getUnknownLoc();
176 if (MI != MBB.end()) DL = MI->getDebugLoc();
178 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, get(ARM::tPUSH));
180 MIB.addReg(0); // No write back.
181 for (unsigned i = CSI.size(); i != 0; --i) {
182 unsigned Reg = CSI[i-1].getReg();
183 // Add the callee-saved register as live-in. It's killed at the spill.
185 MIB.addReg(Reg, RegState::Kill);
190 bool Thumb1InstrInfo::
191 restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
192 MachineBasicBlock::iterator MI,
193 const std::vector<CalleeSavedInfo> &CSI) const {
194 MachineFunction &MF = *MBB.getParent();
195 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
199 bool isVarArg = AFI->getVarArgsRegSaveSize() > 0;
200 DebugLoc DL = MI->getDebugLoc();
201 MachineInstrBuilder MIB = BuildMI(MF, DL, get(ARM::tPOP));
203 MIB.addReg(0); // No write back.
206 for (unsigned i = CSI.size(); i != 0; --i) {
207 unsigned Reg = CSI[i-1].getReg();
208 if (Reg == ARM::LR) {
209 // Special epilogue for vararg functions. See emitEpilogue
213 (*MIB).setDesc(get(ARM::tPOP_RET));
216 MIB.addReg(Reg, getDefRegState(true));
220 // It's illegal to emit pop instruction without operands.
222 MBB.insert(MI, &*MIB);
227 MachineInstr *Thumb1InstrInfo::
228 foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
229 const SmallVectorImpl<unsigned> &Ops, int FI) const {
230 if (Ops.size() != 1) return NULL;
232 unsigned OpNum = Ops[0];
233 unsigned Opc = MI->getOpcode();
234 MachineInstr *NewMI = NULL;
238 case ARM::tMOVtgpr2gpr:
239 case ARM::tMOVgpr2tgpr:
240 case ARM::tMOVgpr2gpr: {
241 if (OpNum == 0) { // move -> store
242 unsigned SrcReg = MI->getOperand(1).getReg();
243 bool isKill = MI->getOperand(1).isKill();
244 if (TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
245 !isARMLowRegister(SrcReg))
246 // tSpill cannot take a high register operand.
248 NewMI = AddDefaultPred(BuildMI(MF, MI->getDebugLoc(), get(ARM::tSpill))
249 .addReg(SrcReg, getKillRegState(isKill))
250 .addFrameIndex(FI).addImm(0));
251 } else { // move -> load
252 unsigned DstReg = MI->getOperand(0).getReg();
253 if (TargetRegisterInfo::isPhysicalRegister(DstReg) &&
254 !isARMLowRegister(DstReg))
255 // tRestore cannot target a high register operand.
257 bool isDead = MI->getOperand(0).isDead();
258 NewMI = AddDefaultPred(BuildMI(MF, MI->getDebugLoc(), get(ARM::tRestore))
260 RegState::Define | getDeadRegState(isDead))
261 .addFrameIndex(FI).addImm(0));
270 void Thumb1InstrInfo::reMaterialize(MachineBasicBlock &MBB,
271 MachineBasicBlock::iterator I,
272 unsigned DestReg, unsigned SubIdx,
273 const MachineInstr *Orig) const {
274 DebugLoc dl = Orig->getDebugLoc();
275 unsigned Opcode = Orig->getOpcode();
278 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
279 MI->getOperand(0).setReg(DestReg);
283 case ARM::tLDRpci_pic: {
284 MachineFunction &MF = *MBB.getParent();
285 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
286 MachineConstantPool *MCP = MF.getConstantPool();
287 unsigned CPI = Orig->getOperand(1).getIndex();
288 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI];
289 assert(MCPE.isMachineConstantPoolEntry() &&
290 "Expecting a machine constantpool entry!");
291 ARMConstantPoolValue *ACPV =
292 static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
293 assert(ACPV->isGlobalValue() && "Expecting a GV!");
294 unsigned PCLabelId = AFI->createConstPoolEntryUId();
295 ARMConstantPoolValue *NewCPV =
296 new ARMConstantPoolValue(ACPV->getGV(), PCLabelId, ARMCP::CPValue, 4);
297 CPI = MCP->getConstantPoolIndex(NewCPV, MCPE.getAlignment());
298 MachineInstrBuilder MIB = BuildMI(MBB, I, Orig->getDebugLoc(), get(Opcode),
300 .addConstantPoolIndex(CPI).addImm(PCLabelId);
301 (*MIB).setMemRefs(Orig->memoperands_begin(), Orig->memoperands_end());
306 MachineInstr *NewMI = prior(I);
307 NewMI->getOperand(0).setSubReg(SubIdx);