1 //===- Thumb1InstrInfo.cpp - Thumb-1 Instruction Information ----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Thumb-1 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "Thumb1InstrInfo.h"
16 #include "ARMGenInstrInfo.inc"
17 #include "ARMMachineFunctionInfo.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/CodeGen/MachineMemOperand.h"
21 #include "llvm/CodeGen/PseudoSourceValue.h"
22 #include "llvm/ADT/SmallVector.h"
23 #include "Thumb1InstrInfo.h"
27 Thumb1InstrInfo::Thumb1InstrInfo(const ARMSubtarget &STI)
28 : ARMBaseInstrInfo(STI), RI(*this, STI) {
31 unsigned Thumb1InstrInfo::getUnindexedOpcode(unsigned Opc) const {
35 bool Thumb1InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
36 MachineBasicBlock::iterator I,
37 unsigned DestReg, unsigned SrcReg,
38 const TargetRegisterClass *DestRC,
39 const TargetRegisterClass *SrcRC) const {
40 DebugLoc DL = DebugLoc::getUnknownLoc();
41 if (I != MBB.end()) DL = I->getDebugLoc();
43 if (DestRC == ARM::GPRRegisterClass) {
44 if (SrcRC == ARM::GPRRegisterClass) {
45 BuildMI(MBB, I, DL, get(ARM::tMOVgpr2gpr), DestReg).addReg(SrcReg);
47 } else if (SrcRC == ARM::tGPRRegisterClass) {
48 BuildMI(MBB, I, DL, get(ARM::tMOVtgpr2gpr), DestReg).addReg(SrcReg);
51 } else if (DestRC == ARM::tGPRRegisterClass) {
52 if (SrcRC == ARM::GPRRegisterClass) {
53 BuildMI(MBB, I, DL, get(ARM::tMOVgpr2tgpr), DestReg).addReg(SrcReg);
55 } else if (SrcRC == ARM::tGPRRegisterClass) {
56 BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg).addReg(SrcReg);
64 bool Thumb1InstrInfo::
65 canFoldMemoryOperand(const MachineInstr *MI,
66 const SmallVectorImpl<unsigned> &Ops) const {
67 if (Ops.size() != 1) return false;
69 unsigned OpNum = Ops[0];
70 unsigned Opc = MI->getOpcode();
74 case ARM::tMOVtgpr2gpr:
75 case ARM::tMOVgpr2tgpr:
76 case ARM::tMOVgpr2gpr: {
77 if (OpNum == 0) { // move -> store
78 unsigned SrcReg = MI->getOperand(1).getReg();
79 if (TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
80 !isARMLowRegister(SrcReg))
81 // tSpill cannot take a high register operand.
83 } else { // move -> load
84 unsigned DstReg = MI->getOperand(0).getReg();
85 if (TargetRegisterInfo::isPhysicalRegister(DstReg) &&
86 !isARMLowRegister(DstReg))
87 // tRestore cannot target a high register operand.
97 void Thumb1InstrInfo::
98 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
99 unsigned SrcReg, bool isKill, int FI,
100 const TargetRegisterClass *RC) const {
101 DebugLoc DL = DebugLoc::getUnknownLoc();
102 if (I != MBB.end()) DL = I->getDebugLoc();
104 assert((RC == ARM::tGPRRegisterClass ||
105 (TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
106 isARMLowRegister(SrcReg))) && "Unknown regclass!");
108 if (RC == ARM::tGPRRegisterClass) {
109 MachineFunction &MF = *MBB.getParent();
110 MachineFrameInfo &MFI = *MF.getFrameInfo();
111 MachineMemOperand *MMO =
112 MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI),
113 MachineMemOperand::MOStore, 0,
114 MFI.getObjectSize(FI),
115 MFI.getObjectAlignment(FI));
116 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tSpill))
117 .addReg(SrcReg, getKillRegState(isKill))
118 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
122 void Thumb1InstrInfo::
123 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
124 unsigned DestReg, int FI,
125 const TargetRegisterClass *RC) const {
126 DebugLoc DL = DebugLoc::getUnknownLoc();
127 if (I != MBB.end()) DL = I->getDebugLoc();
129 assert((RC == ARM::tGPRRegisterClass ||
130 (TargetRegisterInfo::isPhysicalRegister(DestReg) &&
131 isARMLowRegister(DestReg))) && "Unknown regclass!");
133 if (RC == ARM::tGPRRegisterClass) {
134 MachineFunction &MF = *MBB.getParent();
135 MachineFrameInfo &MFI = *MF.getFrameInfo();
136 MachineMemOperand *MMO =
137 MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI),
138 MachineMemOperand::MOLoad, 0,
139 MFI.getObjectSize(FI),
140 MFI.getObjectAlignment(FI));
141 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tRestore), DestReg)
142 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
146 bool Thumb1InstrInfo::
147 spillCalleeSavedRegisters(MachineBasicBlock &MBB,
148 MachineBasicBlock::iterator MI,
149 const std::vector<CalleeSavedInfo> &CSI) const {
153 DebugLoc DL = DebugLoc::getUnknownLoc();
154 if (MI != MBB.end()) DL = MI->getDebugLoc();
156 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, get(ARM::tPUSH));
158 MIB.addReg(0); // No write back.
159 for (unsigned i = CSI.size(); i != 0; --i) {
160 unsigned Reg = CSI[i-1].getReg();
161 // Add the callee-saved register as live-in. It's killed at the spill.
163 MIB.addReg(Reg, RegState::Kill);
168 bool Thumb1InstrInfo::
169 restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
170 MachineBasicBlock::iterator MI,
171 const std::vector<CalleeSavedInfo> &CSI) const {
172 MachineFunction &MF = *MBB.getParent();
173 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
177 bool isVarArg = AFI->getVarArgsRegSaveSize() > 0;
178 DebugLoc DL = MI->getDebugLoc();
179 MachineInstrBuilder MIB = BuildMI(MF, DL, get(ARM::tPOP));
181 MIB.addReg(0); // No write back.
184 for (unsigned i = CSI.size(); i != 0; --i) {
185 unsigned Reg = CSI[i-1].getReg();
186 if (Reg == ARM::LR) {
187 // Special epilogue for vararg functions. See emitEpilogue
191 (*MIB).setDesc(get(ARM::tPOP_RET));
194 MIB.addReg(Reg, getDefRegState(true));
198 // It's illegal to emit pop instruction without operands.
200 MBB.insert(MI, &*MIB);
205 MachineInstr *Thumb1InstrInfo::
206 foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
207 const SmallVectorImpl<unsigned> &Ops, int FI) const {
208 if (Ops.size() != 1) return NULL;
210 unsigned OpNum = Ops[0];
211 unsigned Opc = MI->getOpcode();
212 MachineInstr *NewMI = NULL;
216 case ARM::tMOVtgpr2gpr:
217 case ARM::tMOVgpr2tgpr:
218 case ARM::tMOVgpr2gpr: {
219 if (OpNum == 0) { // move -> store
220 unsigned SrcReg = MI->getOperand(1).getReg();
221 bool isKill = MI->getOperand(1).isKill();
222 if (TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
223 !isARMLowRegister(SrcReg))
224 // tSpill cannot take a high register operand.
226 NewMI = AddDefaultPred(BuildMI(MF, MI->getDebugLoc(), get(ARM::tSpill))
227 .addReg(SrcReg, getKillRegState(isKill))
228 .addFrameIndex(FI).addImm(0));
229 } else { // move -> load
230 unsigned DstReg = MI->getOperand(0).getReg();
231 if (TargetRegisterInfo::isPhysicalRegister(DstReg) &&
232 !isARMLowRegister(DstReg))
233 // tRestore cannot target a high register operand.
235 bool isDead = MI->getOperand(0).isDead();
236 NewMI = AddDefaultPred(BuildMI(MF, MI->getDebugLoc(), get(ARM::tRestore))
238 RegState::Define | getDeadRegState(isDead))
239 .addFrameIndex(FI).addImm(0));