1 //===- Thumb1InstrInfo.cpp - Thumb-1 Instruction Information --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Thumb-1 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "ARMInstrInfo.h"
16 #include "ARMGenInstrInfo.inc"
17 #include "ARMMachineFunctionInfo.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/ADT/SmallVector.h"
21 #include "Thumb1InstrInfo.h"
25 Thumb1InstrInfo::Thumb1InstrInfo(const ARMSubtarget &STI)
26 : ARMBaseInstrInfo(STI), RI(*this, STI) {
29 unsigned Thumb1InstrInfo::getUnindexedOpcode(unsigned Opc) const {
34 Thumb1InstrInfo::unsignedOffsetOpcodeToSigned(unsigned opcode,
35 unsigned *NumBits) const {
39 unsigned Thumb1InstrInfo::getOpcode(ARMII::Op Op) const {
41 case ARMII::ADDri: return ARM::tADDi8;
42 case ARMII::ADDrs: return 0;
43 case ARMII::ADDrr: return ARM::tADDrr;
44 case ARMII::B: return ARM::tB;
45 case ARMII::Bcc: return ARM::tBcc;
46 case ARMII::BR_JTr: return ARM::tBR_JTr;
47 case ARMII::BR_JTm: return 0;
48 case ARMII::BR_JTadd: return 0;
49 case ARMII::BX_RET: return ARM::tBX_RET;
50 case ARMII::FCPYS: return 0;
51 case ARMII::FCPYD: return 0;
52 case ARMII::FLDD: return 0;
53 case ARMII::FLDS: return 0;
54 case ARMII::FSTD: return 0;
55 case ARMII::FSTS: return 0;
56 case ARMII::LDR: return ARM::tLDR;
57 case ARMII::MOVr: return ARM::tMOVr;
58 case ARMII::STR: return ARM::tSTR;
59 case ARMII::SUBri: return ARM::tSUBi8;
60 case ARMII::SUBrs: return 0;
61 case ARMII::SUBrr: return ARM::tSUBrr;
62 case ARMII::VMOVD: return 0;
63 case ARMII::VMOVQ: return 0;
72 Thumb1InstrInfo::BlockHasNoFallThrough(const MachineBasicBlock &MBB) const {
73 if (MBB.empty()) return false;
75 switch (MBB.back().getOpcode()) {
77 case ARM::tBX_RET_vararg:
89 bool Thumb1InstrInfo::isMoveInstr(const MachineInstr &MI,
90 unsigned &SrcReg, unsigned &DstReg,
91 unsigned& SrcSubIdx, unsigned& DstSubIdx) const {
92 SrcSubIdx = DstSubIdx = 0; // No sub-registers.
94 unsigned oc = MI.getOpcode();
99 case ARM::tMOVhir2lor:
100 case ARM::tMOVlor2hir:
101 case ARM::tMOVhir2hir:
102 assert(MI.getDesc().getNumOperands() >= 2 &&
103 MI.getOperand(0).isReg() &&
104 MI.getOperand(1).isReg() &&
105 "Invalid Thumb MOV instruction");
106 SrcReg = MI.getOperand(1).getReg();
107 DstReg = MI.getOperand(0).getReg();
112 unsigned Thumb1InstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
113 int &FrameIndex) const {
114 switch (MI->getOpcode()) {
117 if (MI->getOperand(1).isFI() &&
118 MI->getOperand(2).isImm() &&
119 MI->getOperand(2).getImm() == 0) {
120 FrameIndex = MI->getOperand(1).getIndex();
121 return MI->getOperand(0).getReg();
128 unsigned Thumb1InstrInfo::isStoreToStackSlot(const MachineInstr *MI,
129 int &FrameIndex) const {
130 switch (MI->getOpcode()) {
133 if (MI->getOperand(1).isFI() &&
134 MI->getOperand(2).isImm() &&
135 MI->getOperand(2).getImm() == 0) {
136 FrameIndex = MI->getOperand(1).getIndex();
137 return MI->getOperand(0).getReg();
144 bool Thumb1InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
145 MachineBasicBlock::iterator I,
146 unsigned DestReg, unsigned SrcReg,
147 const TargetRegisterClass *DestRC,
148 const TargetRegisterClass *SrcRC) const {
149 DebugLoc DL = DebugLoc::getUnknownLoc();
150 if (I != MBB.end()) DL = I->getDebugLoc();
152 if (DestRC == ARM::GPRRegisterClass) {
153 if (SrcRC == ARM::GPRRegisterClass) {
154 BuildMI(MBB, I, DL, get(ARM::tMOVhir2hir), DestReg).addReg(SrcReg);
156 } else if (SrcRC == ARM::tGPRRegisterClass) {
157 BuildMI(MBB, I, DL, get(ARM::tMOVlor2hir), DestReg).addReg(SrcReg);
160 } else if (DestRC == ARM::tGPRRegisterClass) {
161 if (SrcRC == ARM::GPRRegisterClass) {
162 BuildMI(MBB, I, DL, get(ARM::tMOVhir2lor), DestReg).addReg(SrcReg);
164 } else if (SrcRC == ARM::tGPRRegisterClass) {
165 BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg).addReg(SrcReg);
173 bool Thumb1InstrInfo::
174 canFoldMemoryOperand(const MachineInstr *MI,
175 const SmallVectorImpl<unsigned> &Ops) const {
176 if (Ops.size() != 1) return false;
178 unsigned OpNum = Ops[0];
179 unsigned Opc = MI->getOpcode();
183 case ARM::tMOVlor2hir:
184 case ARM::tMOVhir2lor:
185 case ARM::tMOVhir2hir: {
186 if (OpNum == 0) { // move -> store
187 unsigned SrcReg = MI->getOperand(1).getReg();
188 if (RI.isPhysicalRegister(SrcReg) && !isARMLowRegister(SrcReg))
189 // tSpill cannot take a high register operand.
191 } else { // move -> load
192 unsigned DstReg = MI->getOperand(0).getReg();
193 if (RI.isPhysicalRegister(DstReg) && !isARMLowRegister(DstReg))
194 // tRestore cannot target a high register operand.
204 void Thumb1InstrInfo::
205 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
206 unsigned SrcReg, bool isKill, int FI,
207 const TargetRegisterClass *RC) const {
208 DebugLoc DL = DebugLoc::getUnknownLoc();
209 if (I != MBB.end()) DL = I->getDebugLoc();
211 assert(RC == ARM::tGPRRegisterClass && "Unknown regclass!");
213 if (RC == ARM::tGPRRegisterClass) {
214 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tSpill))
215 .addReg(SrcReg, getKillRegState(isKill))
216 .addFrameIndex(FI).addImm(0));
220 void Thumb1InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
222 SmallVectorImpl<MachineOperand> &Addr,
223 const TargetRegisterClass *RC,
224 SmallVectorImpl<MachineInstr*> &NewMIs) const{
225 DebugLoc DL = DebugLoc::getUnknownLoc();
228 assert(RC == ARM::GPRRegisterClass && "Unknown regclass!");
229 if (RC == ARM::GPRRegisterClass) {
230 Opc = Addr[0].isFI() ? ARM::tSpill : ARM::tSTR;
233 MachineInstrBuilder MIB =
234 BuildMI(MF, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill));
235 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
236 MIB.addOperand(Addr[i]);
238 NewMIs.push_back(MIB);
242 void Thumb1InstrInfo::
243 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
244 unsigned DestReg, int FI,
245 const TargetRegisterClass *RC) const {
246 DebugLoc DL = DebugLoc::getUnknownLoc();
247 if (I != MBB.end()) DL = I->getDebugLoc();
249 assert(RC == ARM::tGPRRegisterClass && "Unknown regclass!");
251 if (RC == ARM::tGPRRegisterClass) {
252 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tRestore), DestReg)
253 .addFrameIndex(FI).addImm(0));
257 void Thumb1InstrInfo::
258 loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
259 SmallVectorImpl<MachineOperand> &Addr,
260 const TargetRegisterClass *RC,
261 SmallVectorImpl<MachineInstr*> &NewMIs) const {
262 DebugLoc DL = DebugLoc::getUnknownLoc();
265 if (RC == ARM::GPRRegisterClass) {
266 Opc = Addr[0].isFI() ? ARM::tRestore : ARM::tLDR;
269 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
270 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
271 MIB.addOperand(Addr[i]);
273 NewMIs.push_back(MIB);
277 bool Thumb1InstrInfo::
278 spillCalleeSavedRegisters(MachineBasicBlock &MBB,
279 MachineBasicBlock::iterator MI,
280 const std::vector<CalleeSavedInfo> &CSI) const {
284 DebugLoc DL = DebugLoc::getUnknownLoc();
285 if (MI != MBB.end()) DL = MI->getDebugLoc();
287 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, get(ARM::tPUSH));
288 for (unsigned i = CSI.size(); i != 0; --i) {
289 unsigned Reg = CSI[i-1].getReg();
290 // Add the callee-saved register as live-in. It's killed at the spill.
292 MIB.addReg(Reg, RegState::Kill);
297 bool Thumb1InstrInfo::
298 restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
299 MachineBasicBlock::iterator MI,
300 const std::vector<CalleeSavedInfo> &CSI) const {
301 MachineFunction &MF = *MBB.getParent();
302 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
306 bool isVarArg = AFI->getVarArgsRegSaveSize() > 0;
307 MachineInstr *PopMI = MF.CreateMachineInstr(get(ARM::tPOP),MI->getDebugLoc());
308 for (unsigned i = CSI.size(); i != 0; --i) {
309 unsigned Reg = CSI[i-1].getReg();
310 if (Reg == ARM::LR) {
311 // Special epilogue for vararg functions. See emitEpilogue
315 PopMI->setDesc(get(ARM::tPOP_RET));
318 PopMI->addOperand(MachineOperand::CreateReg(Reg, true));
321 // It's illegal to emit pop instruction without operands.
322 if (PopMI->getNumOperands() > 0)
323 MBB.insert(MI, PopMI);
328 MachineInstr *Thumb1InstrInfo::
329 foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
330 const SmallVectorImpl<unsigned> &Ops, int FI) const {
331 if (Ops.size() != 1) return NULL;
333 unsigned OpNum = Ops[0];
334 unsigned Opc = MI->getOpcode();
335 MachineInstr *NewMI = NULL;
339 case ARM::tMOVlor2hir:
340 case ARM::tMOVhir2lor:
341 case ARM::tMOVhir2hir: {
342 if (OpNum == 0) { // move -> store
343 unsigned SrcReg = MI->getOperand(1).getReg();
344 bool isKill = MI->getOperand(1).isKill();
345 if (RI.isPhysicalRegister(SrcReg) && !isARMLowRegister(SrcReg))
346 // tSpill cannot take a high register operand.
348 NewMI = AddDefaultPred(BuildMI(MF, MI->getDebugLoc(), get(ARM::tSpill))
349 .addReg(SrcReg, getKillRegState(isKill))
350 .addFrameIndex(FI).addImm(0));
351 } else { // move -> load
352 unsigned DstReg = MI->getOperand(0).getReg();
353 if (RI.isPhysicalRegister(DstReg) && !isARMLowRegister(DstReg))
354 // tRestore cannot target a high register operand.
356 bool isDead = MI->getOperand(0).isDead();
357 NewMI = AddDefaultPred(BuildMI(MF, MI->getDebugLoc(), get(ARM::tRestore))
359 RegState::Define | getDeadRegState(isDead))
360 .addFrameIndex(FI).addImm(0));