1 //===- Thumb1InstrInfo.cpp - Thumb-1 Instruction Information ----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Thumb-1 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "Thumb1InstrInfo.h"
16 #include "ARMGenInstrInfo.inc"
17 #include "ARMMachineFunctionInfo.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/CodeGen/MachineRegisterInfo.h"
21 #include "llvm/CodeGen/MachineMemOperand.h"
22 #include "llvm/CodeGen/PseudoSourceValue.h"
23 #include "llvm/ADT/SmallVector.h"
24 #include "Thumb1InstrInfo.h"
28 Thumb1InstrInfo::Thumb1InstrInfo(const ARMSubtarget &STI)
29 : ARMBaseInstrInfo(STI), RI(*this, STI) {
32 unsigned Thumb1InstrInfo::getUnindexedOpcode(unsigned Opc) const {
36 void Thumb1InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
37 MachineBasicBlock::iterator I, DebugLoc DL,
38 unsigned DestReg, unsigned SrcReg,
40 bool tDest = ARM::tGPRRegClass.contains(DestReg);
41 bool tSrc = ARM::tGPRRegClass.contains(SrcReg);
42 unsigned Opc = ARM::tMOVgpr2gpr;
46 Opc = ARM::tMOVtgpr2gpr;
48 Opc = ARM::tMOVgpr2tgpr;
50 BuildMI(MBB, I, DL, get(Opc), DestReg)
51 .addReg(SrcReg, getKillRegState(KillSrc));
52 assert(ARM::GPRRegClass.contains(DestReg, SrcReg) &&
53 "Thumb1 can only copy GPR registers");
56 void Thumb1InstrInfo::
57 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
58 unsigned SrcReg, bool isKill, int FI,
59 const TargetRegisterClass *RC,
60 const TargetRegisterInfo *TRI) const {
61 assert((RC == ARM::tGPRRegisterClass ||
62 (TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
63 isARMLowRegister(SrcReg))) && "Unknown regclass!");
65 if (RC == ARM::tGPRRegisterClass ||
66 (TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
67 isARMLowRegister(SrcReg))) {
69 if (I != MBB.end()) DL = I->getDebugLoc();
71 MachineFunction &MF = *MBB.getParent();
72 MachineFrameInfo &MFI = *MF.getFrameInfo();
73 MachineMemOperand *MMO =
74 MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI),
75 MachineMemOperand::MOStore, 0,
76 MFI.getObjectSize(FI),
77 MFI.getObjectAlignment(FI));
78 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tSpill))
79 .addReg(SrcReg, getKillRegState(isKill))
80 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
84 void Thumb1InstrInfo::
85 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
86 unsigned DestReg, int FI,
87 const TargetRegisterClass *RC,
88 const TargetRegisterInfo *TRI) const {
89 assert((RC == ARM::tGPRRegisterClass ||
90 (TargetRegisterInfo::isPhysicalRegister(DestReg) &&
91 isARMLowRegister(DestReg))) && "Unknown regclass!");
93 if (RC == ARM::tGPRRegisterClass ||
94 (TargetRegisterInfo::isPhysicalRegister(DestReg) &&
95 isARMLowRegister(DestReg))) {
97 if (I != MBB.end()) DL = I->getDebugLoc();
99 MachineFunction &MF = *MBB.getParent();
100 MachineFrameInfo &MFI = *MF.getFrameInfo();
101 MachineMemOperand *MMO =
102 MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI),
103 MachineMemOperand::MOLoad, 0,
104 MFI.getObjectSize(FI),
105 MFI.getObjectAlignment(FI));
106 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tRestore), DestReg)
107 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
111 bool Thumb1InstrInfo::
112 spillCalleeSavedRegisters(MachineBasicBlock &MBB,
113 MachineBasicBlock::iterator MI,
114 const std::vector<CalleeSavedInfo> &CSI,
115 const TargetRegisterInfo *TRI) const {
120 if (MI != MBB.end()) DL = MI->getDebugLoc();
122 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, get(ARM::tPUSH));
124 for (unsigned i = CSI.size(); i != 0; --i) {
125 unsigned Reg = CSI[i-1].getReg();
128 // Add the callee-saved register as live-in unless it's LR and
129 // @llvm.returnaddress is called. If LR is returned for @llvm.returnaddress
130 // then it's already added to the function and entry block live-in sets.
131 if (Reg == ARM::LR) {
132 MachineFunction &MF = *MBB.getParent();
133 if (MF.getFrameInfo()->isReturnAddressTaken() &&
134 MF.getRegInfo().isLiveIn(Reg))
141 MIB.addReg(Reg, getKillRegState(isKill));
146 bool Thumb1InstrInfo::
147 restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
148 MachineBasicBlock::iterator MI,
149 const std::vector<CalleeSavedInfo> &CSI,
150 const TargetRegisterInfo *TRI) const {
151 MachineFunction &MF = *MBB.getParent();
152 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
156 bool isVarArg = AFI->getVarArgsRegSaveSize() > 0;
157 DebugLoc DL = MI->getDebugLoc();
158 MachineInstrBuilder MIB = BuildMI(MF, DL, get(ARM::tPOP));
161 bool NumRegs = false;
162 for (unsigned i = CSI.size(); i != 0; --i) {
163 unsigned Reg = CSI[i-1].getReg();
164 if (Reg == ARM::LR) {
165 // Special epilogue for vararg functions. See emitEpilogue
169 (*MIB).setDesc(get(ARM::tPOP_RET));
172 MIB.addReg(Reg, getDefRegState(true));
176 // It's illegal to emit pop instruction without operands.
178 MBB.insert(MI, &*MIB);
180 MF.DeleteMachineInstr(MIB);