1 //===- Thumb1InstrInfo.cpp - Thumb-1 Instruction Information --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Thumb-1 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "ARMInstrInfo.h"
16 #include "ARMGenInstrInfo.inc"
17 #include "ARMMachineFunctionInfo.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/ADT/SmallVector.h"
21 #include "Thumb1InstrInfo.h"
25 Thumb1InstrInfo::Thumb1InstrInfo(const ARMSubtarget &STI)
26 : ARMBaseInstrInfo(STI), RI(*this, STI) {
29 unsigned Thumb1InstrInfo::getUnindexedOpcode(unsigned Opc) const {
33 unsigned Thumb1InstrInfo::getOpcode(ARMII::Op Op) const {
35 case ARMII::ADDri: return ARM::tADDi8;
36 case ARMII::ADDrs: return 0;
37 case ARMII::ADDrr: return ARM::tADDrr;
38 case ARMII::B: return ARM::tB;
39 case ARMII::Bcc: return ARM::tBcc;
40 case ARMII::BX_RET: return ARM::tBX_RET;
41 case ARMII::LDRrr: return ARM::tLDR;
42 case ARMII::LDRri: return 0;
43 case ARMII::MOVr: return ARM::tMOVr;
44 case ARMII::STRrr: return ARM::tSTR;
45 case ARMII::STRri: return 0;
46 case ARMII::SUBri: return ARM::tSUBi8;
47 case ARMII::SUBrs: return 0;
48 case ARMII::SUBrr: return ARM::tSUBrr;
57 Thumb1InstrInfo::BlockHasNoFallThrough(const MachineBasicBlock &MBB) const {
58 if (MBB.empty()) return false;
60 switch (MBB.back().getOpcode()) {
62 case ARM::tBX_RET_vararg:
74 unsigned Thumb1InstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
75 int &FrameIndex) const {
76 switch (MI->getOpcode()) {
79 if (MI->getOperand(1).isFI() &&
80 MI->getOperand(2).isImm() &&
81 MI->getOperand(2).getImm() == 0) {
82 FrameIndex = MI->getOperand(1).getIndex();
83 return MI->getOperand(0).getReg();
90 unsigned Thumb1InstrInfo::isStoreToStackSlot(const MachineInstr *MI,
91 int &FrameIndex) const {
92 switch (MI->getOpcode()) {
95 if (MI->getOperand(1).isFI() &&
96 MI->getOperand(2).isImm() &&
97 MI->getOperand(2).getImm() == 0) {
98 FrameIndex = MI->getOperand(1).getIndex();
99 return MI->getOperand(0).getReg();
106 bool Thumb1InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
107 MachineBasicBlock::iterator I,
108 unsigned DestReg, unsigned SrcReg,
109 const TargetRegisterClass *DestRC,
110 const TargetRegisterClass *SrcRC) const {
111 DebugLoc DL = DebugLoc::getUnknownLoc();
112 if (I != MBB.end()) DL = I->getDebugLoc();
114 if (DestRC == ARM::GPRRegisterClass) {
115 if (SrcRC == ARM::GPRRegisterClass) {
116 BuildMI(MBB, I, DL, get(ARM::tMOVgpr2gpr), DestReg).addReg(SrcReg);
118 } else if (SrcRC == ARM::tGPRRegisterClass) {
119 BuildMI(MBB, I, DL, get(ARM::tMOVtgpr2gpr), DestReg).addReg(SrcReg);
122 } else if (DestRC == ARM::tGPRRegisterClass) {
123 if (SrcRC == ARM::GPRRegisterClass) {
124 BuildMI(MBB, I, DL, get(ARM::tMOVgpr2tgpr), DestReg).addReg(SrcReg);
126 } else if (SrcRC == ARM::tGPRRegisterClass) {
127 BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg).addReg(SrcReg);
135 bool Thumb1InstrInfo::
136 canFoldMemoryOperand(const MachineInstr *MI,
137 const SmallVectorImpl<unsigned> &Ops) const {
138 if (Ops.size() != 1) return false;
140 unsigned OpNum = Ops[0];
141 unsigned Opc = MI->getOpcode();
145 case ARM::tMOVtgpr2gpr:
146 case ARM::tMOVgpr2tgpr:
147 case ARM::tMOVgpr2gpr: {
148 if (OpNum == 0) { // move -> store
149 unsigned SrcReg = MI->getOperand(1).getReg();
150 if (RI.isPhysicalRegister(SrcReg) && !isARMLowRegister(SrcReg))
151 // tSpill cannot take a high register operand.
153 } else { // move -> load
154 unsigned DstReg = MI->getOperand(0).getReg();
155 if (RI.isPhysicalRegister(DstReg) && !isARMLowRegister(DstReg))
156 // tRestore cannot target a high register operand.
166 void Thumb1InstrInfo::
167 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
168 unsigned SrcReg, bool isKill, int FI,
169 const TargetRegisterClass *RC) const {
170 DebugLoc DL = DebugLoc::getUnknownLoc();
171 if (I != MBB.end()) DL = I->getDebugLoc();
173 assert(RC == ARM::tGPRRegisterClass && "Unknown regclass!");
175 if (RC == ARM::tGPRRegisterClass) {
176 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tSpill))
177 .addReg(SrcReg, getKillRegState(isKill))
178 .addFrameIndex(FI).addImm(0));
182 void Thumb1InstrInfo::
183 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
184 unsigned DestReg, int FI,
185 const TargetRegisterClass *RC) const {
186 DebugLoc DL = DebugLoc::getUnknownLoc();
187 if (I != MBB.end()) DL = I->getDebugLoc();
189 assert(RC == ARM::tGPRRegisterClass && "Unknown regclass!");
191 if (RC == ARM::tGPRRegisterClass) {
192 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tRestore), DestReg)
193 .addFrameIndex(FI).addImm(0));
197 bool Thumb1InstrInfo::
198 spillCalleeSavedRegisters(MachineBasicBlock &MBB,
199 MachineBasicBlock::iterator MI,
200 const std::vector<CalleeSavedInfo> &CSI) const {
204 DebugLoc DL = DebugLoc::getUnknownLoc();
205 if (MI != MBB.end()) DL = MI->getDebugLoc();
207 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, get(ARM::tPUSH));
208 for (unsigned i = CSI.size(); i != 0; --i) {
209 unsigned Reg = CSI[i-1].getReg();
210 // Add the callee-saved register as live-in. It's killed at the spill.
212 MIB.addReg(Reg, RegState::Kill);
217 bool Thumb1InstrInfo::
218 restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
219 MachineBasicBlock::iterator MI,
220 const std::vector<CalleeSavedInfo> &CSI) const {
221 MachineFunction &MF = *MBB.getParent();
222 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
226 bool isVarArg = AFI->getVarArgsRegSaveSize() > 0;
227 MachineInstr *PopMI = MF.CreateMachineInstr(get(ARM::tPOP),MI->getDebugLoc());
228 for (unsigned i = CSI.size(); i != 0; --i) {
229 unsigned Reg = CSI[i-1].getReg();
230 if (Reg == ARM::LR) {
231 // Special epilogue for vararg functions. See emitEpilogue
235 PopMI->setDesc(get(ARM::tPOP_RET));
238 PopMI->addOperand(MachineOperand::CreateReg(Reg, true));
241 // It's illegal to emit pop instruction without operands.
242 if (PopMI->getNumOperands() > 0)
243 MBB.insert(MI, PopMI);
248 MachineInstr *Thumb1InstrInfo::
249 foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
250 const SmallVectorImpl<unsigned> &Ops, int FI) const {
251 if (Ops.size() != 1) return NULL;
253 unsigned OpNum = Ops[0];
254 unsigned Opc = MI->getOpcode();
255 MachineInstr *NewMI = NULL;
259 case ARM::tMOVtgpr2gpr:
260 case ARM::tMOVgpr2tgpr:
261 case ARM::tMOVgpr2gpr: {
262 if (OpNum == 0) { // move -> store
263 unsigned SrcReg = MI->getOperand(1).getReg();
264 bool isKill = MI->getOperand(1).isKill();
265 if (RI.isPhysicalRegister(SrcReg) && !isARMLowRegister(SrcReg))
266 // tSpill cannot take a high register operand.
268 NewMI = AddDefaultPred(BuildMI(MF, MI->getDebugLoc(), get(ARM::tSpill))
269 .addReg(SrcReg, getKillRegState(isKill))
270 .addFrameIndex(FI).addImm(0));
271 } else { // move -> load
272 unsigned DstReg = MI->getOperand(0).getReg();
273 if (RI.isPhysicalRegister(DstReg) && !isARMLowRegister(DstReg))
274 // tRestore cannot target a high register operand.
276 bool isDead = MI->getOperand(0).isDead();
277 NewMI = AddDefaultPred(BuildMI(MF, MI->getDebugLoc(), get(ARM::tRestore))
279 RegState::Define | getDeadRegState(isDead))
280 .addFrameIndex(FI).addImm(0));