1 //===- Thumb1InstrInfo.cpp - Thumb-1 Instruction Information ----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Thumb-1 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "Thumb1InstrInfo.h"
16 #include "ARMMachineFunctionInfo.h"
17 #include "llvm/CodeGen/MachineFrameInfo.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/MachineRegisterInfo.h"
20 #include "llvm/CodeGen/MachineMemOperand.h"
21 #include "llvm/ADT/SmallVector.h"
22 #include "Thumb1InstrInfo.h"
26 Thumb1InstrInfo::Thumb1InstrInfo(const ARMSubtarget &STI)
27 : ARMBaseInstrInfo(STI), RI(*this, STI) {
30 unsigned Thumb1InstrInfo::getUnindexedOpcode(unsigned Opc) const {
34 void Thumb1InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
35 MachineBasicBlock::iterator I, DebugLoc DL,
36 unsigned DestReg, unsigned SrcReg,
38 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg)
39 .addReg(SrcReg, getKillRegState(KillSrc)));
40 assert(ARM::GPRRegClass.contains(DestReg, SrcReg) &&
41 "Thumb1 can only copy GPR registers");
44 void Thumb1InstrInfo::
45 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
46 unsigned SrcReg, bool isKill, int FI,
47 const TargetRegisterClass *RC,
48 const TargetRegisterInfo *TRI) const {
49 assert((RC == ARM::tGPRRegisterClass ||
50 (TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
51 isARMLowRegister(SrcReg))) && "Unknown regclass!");
53 if (RC == ARM::tGPRRegisterClass ||
54 (TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
55 isARMLowRegister(SrcReg))) {
57 if (I != MBB.end()) DL = I->getDebugLoc();
59 MachineFunction &MF = *MBB.getParent();
60 MachineFrameInfo &MFI = *MF.getFrameInfo();
61 MachineMemOperand *MMO =
62 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
63 MachineMemOperand::MOStore,
64 MFI.getObjectSize(FI),
65 MFI.getObjectAlignment(FI));
66 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tSTRspi))
67 .addReg(SrcReg, getKillRegState(isKill))
68 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
72 void Thumb1InstrInfo::
73 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
74 unsigned DestReg, int FI,
75 const TargetRegisterClass *RC,
76 const TargetRegisterInfo *TRI) const {
77 assert((RC == ARM::tGPRRegisterClass ||
78 (TargetRegisterInfo::isPhysicalRegister(DestReg) &&
79 isARMLowRegister(DestReg))) && "Unknown regclass!");
81 if (RC == ARM::tGPRRegisterClass ||
82 (TargetRegisterInfo::isPhysicalRegister(DestReg) &&
83 isARMLowRegister(DestReg))) {
85 if (I != MBB.end()) DL = I->getDebugLoc();
87 MachineFunction &MF = *MBB.getParent();
88 MachineFrameInfo &MFI = *MF.getFrameInfo();
89 MachineMemOperand *MMO =
90 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
91 MachineMemOperand::MOLoad,
92 MFI.getObjectSize(FI),
93 MFI.getObjectAlignment(FI));
94 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tLDRspi), DestReg)
95 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));