1 //===- Thumb1InstrInfo.cpp - Thumb-1 Instruction Information --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Thumb-1 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "ARMInstrInfo.h"
16 #include "ARMGenInstrInfo.inc"
17 #include "ARMMachineFunctionInfo.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/ADT/SmallVector.h"
21 #include "Thumb1InstrInfo.h"
25 Thumb1InstrInfo::Thumb1InstrInfo(const ARMSubtarget &STI)
26 : ARMBaseInstrInfo(STI), RI(*this, STI) {
29 unsigned Thumb1InstrInfo::
30 getUnindexedOpcode(unsigned Opc) const {
34 unsigned Thumb1InstrInfo::
35 getOpcode(ARMII::Op Op) const {
37 case ARMII::ADDri: return ARM::tADDi8;
38 case ARMII::ADDrs: return 0;
39 case ARMII::ADDrr: return ARM::tADDrr;
40 case ARMII::B: return ARM::tB;
41 case ARMII::Bcc: return ARM::tBcc;
42 case ARMII::BR_JTr: return ARM::tBR_JTr;
43 case ARMII::BR_JTm: return 0;
44 case ARMII::BR_JTadd: return 0;
45 case ARMII::BX_RET: return ARM::tBX_RET;
46 case ARMII::FCPYS: return 0;
47 case ARMII::FCPYD: return 0;
48 case ARMII::FLDD: return 0;
49 case ARMII::FLDS: return 0;
50 case ARMII::FSTD: return 0;
51 case ARMII::FSTS: return 0;
52 case ARMII::LDR: return ARM::tLDR;
53 case ARMII::MOVr: return ARM::tMOVr;
54 case ARMII::STR: return ARM::tSTR;
55 case ARMII::SUBri: return ARM::tSUBi8;
56 case ARMII::SUBrs: return 0;
57 case ARMII::SUBrr: return ARM::tSUBrr;
58 case ARMII::VMOVD: return 0;
59 case ARMII::VMOVQ: return 0;
68 Thumb1InstrInfo::BlockHasNoFallThrough(const MachineBasicBlock &MBB) const {
69 if (MBB.empty()) return false;
71 switch (MBB.back().getOpcode()) {
73 case ARM::tBX_RET_vararg:
85 bool Thumb1InstrInfo::isMoveInstr(const MachineInstr &MI,
86 unsigned &SrcReg, unsigned &DstReg,
87 unsigned& SrcSubIdx, unsigned& DstSubIdx) const {
88 SrcSubIdx = DstSubIdx = 0; // No sub-registers.
90 unsigned oc = MI.getOpcode();
95 case ARM::tMOVhir2lor:
96 case ARM::tMOVlor2hir:
97 case ARM::tMOVhir2hir:
98 assert(MI.getDesc().getNumOperands() >= 2 &&
99 MI.getOperand(0).isReg() &&
100 MI.getOperand(1).isReg() &&
101 "Invalid Thumb MOV instruction");
102 SrcReg = MI.getOperand(1).getReg();
103 DstReg = MI.getOperand(0).getReg();
108 unsigned Thumb1InstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
109 int &FrameIndex) const {
110 switch (MI->getOpcode()) {
113 if (MI->getOperand(1).isFI() &&
114 MI->getOperand(2).isImm() &&
115 MI->getOperand(2).getImm() == 0) {
116 FrameIndex = MI->getOperand(1).getIndex();
117 return MI->getOperand(0).getReg();
124 unsigned Thumb1InstrInfo::isStoreToStackSlot(const MachineInstr *MI,
125 int &FrameIndex) const {
126 switch (MI->getOpcode()) {
129 if (MI->getOperand(1).isFI() &&
130 MI->getOperand(2).isImm() &&
131 MI->getOperand(2).getImm() == 0) {
132 FrameIndex = MI->getOperand(1).getIndex();
133 return MI->getOperand(0).getReg();
140 bool Thumb1InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
141 MachineBasicBlock::iterator I,
142 unsigned DestReg, unsigned SrcReg,
143 const TargetRegisterClass *DestRC,
144 const TargetRegisterClass *SrcRC) const {
145 DebugLoc DL = DebugLoc::getUnknownLoc();
146 if (I != MBB.end()) DL = I->getDebugLoc();
148 if (DestRC == ARM::GPRRegisterClass) {
149 if (SrcRC == ARM::GPRRegisterClass) {
150 BuildMI(MBB, I, DL, get(ARM::tMOVhir2hir), DestReg).addReg(SrcReg);
152 } else if (SrcRC == ARM::tGPRRegisterClass) {
153 BuildMI(MBB, I, DL, get(ARM::tMOVlor2hir), DestReg).addReg(SrcReg);
156 } else if (DestRC == ARM::tGPRRegisterClass) {
157 if (SrcRC == ARM::GPRRegisterClass) {
158 BuildMI(MBB, I, DL, get(ARM::tMOVhir2lor), DestReg).addReg(SrcReg);
160 } else if (SrcRC == ARM::tGPRRegisterClass) {
161 BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg).addReg(SrcReg);
169 bool Thumb1InstrInfo::
170 canFoldMemoryOperand(const MachineInstr *MI,
171 const SmallVectorImpl<unsigned> &Ops) const {
172 if (Ops.size() != 1) return false;
174 unsigned OpNum = Ops[0];
175 unsigned Opc = MI->getOpcode();
179 case ARM::tMOVlor2hir:
180 case ARM::tMOVhir2lor:
181 case ARM::tMOVhir2hir: {
182 if (OpNum == 0) { // move -> store
183 unsigned SrcReg = MI->getOperand(1).getReg();
184 if (RI.isPhysicalRegister(SrcReg) && !isARMLowRegister(SrcReg))
185 // tSpill cannot take a high register operand.
187 } else { // move -> load
188 unsigned DstReg = MI->getOperand(0).getReg();
189 if (RI.isPhysicalRegister(DstReg) && !isARMLowRegister(DstReg))
190 // tRestore cannot target a high register operand.
200 void Thumb1InstrInfo::
201 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
202 unsigned SrcReg, bool isKill, int FI,
203 const TargetRegisterClass *RC) const {
204 DebugLoc DL = DebugLoc::getUnknownLoc();
205 if (I != MBB.end()) DL = I->getDebugLoc();
207 assert(RC == ARM::tGPRRegisterClass && "Unknown regclass!");
209 if (RC == ARM::tGPRRegisterClass) {
210 BuildMI(MBB, I, DL, get(ARM::tSpill))
211 .addReg(SrcReg, getKillRegState(isKill))
212 .addFrameIndex(FI).addImm(0);
216 void Thumb1InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
218 SmallVectorImpl<MachineOperand> &Addr,
219 const TargetRegisterClass *RC,
220 SmallVectorImpl<MachineInstr*> &NewMIs) const{
221 DebugLoc DL = DebugLoc::getUnknownLoc();
224 assert(RC == ARM::GPRRegisterClass && "Unknown regclass!");
225 if (RC == ARM::GPRRegisterClass) {
226 Opc = Addr[0].isFI() ? ARM::tSpill : ARM::tSTR;
229 MachineInstrBuilder MIB =
230 BuildMI(MF, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill));
231 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
232 MIB.addOperand(Addr[i]);
233 NewMIs.push_back(MIB);
237 void Thumb1InstrInfo::
238 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
239 unsigned DestReg, int FI,
240 const TargetRegisterClass *RC) const {
241 DebugLoc DL = DebugLoc::getUnknownLoc();
242 if (I != MBB.end()) DL = I->getDebugLoc();
244 assert(RC == ARM::tGPRRegisterClass && "Unknown regclass!");
246 if (RC == ARM::tGPRRegisterClass) {
247 BuildMI(MBB, I, DL, get(ARM::tRestore), DestReg)
248 .addFrameIndex(FI).addImm(0);
252 void Thumb1InstrInfo::
253 loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
254 SmallVectorImpl<MachineOperand> &Addr,
255 const TargetRegisterClass *RC,
256 SmallVectorImpl<MachineInstr*> &NewMIs) const {
257 DebugLoc DL = DebugLoc::getUnknownLoc();
260 if (RC == ARM::GPRRegisterClass) {
261 Opc = Addr[0].isFI() ? ARM::tRestore : ARM::tLDR;
264 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
265 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
266 MIB.addOperand(Addr[i]);
267 NewMIs.push_back(MIB);
271 bool Thumb1InstrInfo::
272 spillCalleeSavedRegisters(MachineBasicBlock &MBB,
273 MachineBasicBlock::iterator MI,
274 const std::vector<CalleeSavedInfo> &CSI) const {
278 DebugLoc DL = DebugLoc::getUnknownLoc();
279 if (MI != MBB.end()) DL = MI->getDebugLoc();
281 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, get(ARM::tPUSH));
282 for (unsigned i = CSI.size(); i != 0; --i) {
283 unsigned Reg = CSI[i-1].getReg();
284 // Add the callee-saved register as live-in. It's killed at the spill.
286 MIB.addReg(Reg, RegState::Kill);
291 bool Thumb1InstrInfo::
292 restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
293 MachineBasicBlock::iterator MI,
294 const std::vector<CalleeSavedInfo> &CSI) const {
295 MachineFunction &MF = *MBB.getParent();
296 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
300 bool isVarArg = AFI->getVarArgsRegSaveSize() > 0;
301 MachineInstr *PopMI = MF.CreateMachineInstr(get(ARM::tPOP),MI->getDebugLoc());
302 for (unsigned i = CSI.size(); i != 0; --i) {
303 unsigned Reg = CSI[i-1].getReg();
304 if (Reg == ARM::LR) {
305 // Special epilogue for vararg functions. See emitEpilogue
309 PopMI->setDesc(get(ARM::tPOP_RET));
312 PopMI->addOperand(MachineOperand::CreateReg(Reg, true));
315 // It's illegal to emit pop instruction without operands.
316 if (PopMI->getNumOperands() > 0)
317 MBB.insert(MI, PopMI);
322 MachineInstr *Thumb1InstrInfo::
323 foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
324 const SmallVectorImpl<unsigned> &Ops, int FI) const {
325 if (Ops.size() != 1) return NULL;
327 unsigned OpNum = Ops[0];
328 unsigned Opc = MI->getOpcode();
329 MachineInstr *NewMI = NULL;
333 case ARM::tMOVlor2hir:
334 case ARM::tMOVhir2lor:
335 case ARM::tMOVhir2hir: {
336 if (OpNum == 0) { // move -> store
337 unsigned SrcReg = MI->getOperand(1).getReg();
338 bool isKill = MI->getOperand(1).isKill();
339 if (RI.isPhysicalRegister(SrcReg) && !isARMLowRegister(SrcReg))
340 // tSpill cannot take a high register operand.
342 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::tSpill))
343 .addReg(SrcReg, getKillRegState(isKill))
344 .addFrameIndex(FI).addImm(0);
345 } else { // move -> load
346 unsigned DstReg = MI->getOperand(0).getReg();
347 if (RI.isPhysicalRegister(DstReg) && !isARMLowRegister(DstReg))
348 // tRestore cannot target a high register operand.
350 bool isDead = MI->getOperand(0).isDead();
351 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::tRestore))
352 .addReg(DstReg, RegState::Define | getDeadRegState(isDead))
353 .addFrameIndex(FI).addImm(0);