1 //===- Thumb1InstrInfo.cpp - Thumb-1 Instruction Information --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Thumb-1 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "ARMInstrInfo.h"
16 #include "ARMGenInstrInfo.inc"
17 #include "ARMMachineFunctionInfo.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/ADT/SmallVector.h"
21 #include "Thumb1InstrInfo.h"
25 Thumb1InstrInfo::Thumb1InstrInfo(const ARMSubtarget &STI)
26 : ARMBaseInstrInfo(STI), RI(*this, STI) {
29 unsigned Thumb1InstrInfo::getUnindexedOpcode(unsigned Opc) const {
33 unsigned Thumb1InstrInfo::getOpcode(ARMII::Op Op) const {
35 case ARMII::ADDri: return ARM::tADDi8;
36 case ARMII::MOVr: return ARM::tMOVr;
37 case ARMII::SUBri: return ARM::tSUBi8;
46 Thumb1InstrInfo::BlockHasNoFallThrough(const MachineBasicBlock &MBB) const {
47 if (MBB.empty()) return false;
49 switch (MBB.back().getOpcode()) {
51 case ARM::tBX_RET_vararg:
63 bool Thumb1InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
64 MachineBasicBlock::iterator I,
65 unsigned DestReg, unsigned SrcReg,
66 const TargetRegisterClass *DestRC,
67 const TargetRegisterClass *SrcRC) const {
68 DebugLoc DL = DebugLoc::getUnknownLoc();
69 if (I != MBB.end()) DL = I->getDebugLoc();
71 if (DestRC == ARM::GPRRegisterClass) {
72 if (SrcRC == ARM::GPRRegisterClass) {
73 BuildMI(MBB, I, DL, get(ARM::tMOVgpr2gpr), DestReg).addReg(SrcReg);
75 } else if (SrcRC == ARM::tGPRRegisterClass) {
76 BuildMI(MBB, I, DL, get(ARM::tMOVtgpr2gpr), DestReg).addReg(SrcReg);
79 } else if (DestRC == ARM::tGPRRegisterClass) {
80 if (SrcRC == ARM::GPRRegisterClass) {
81 BuildMI(MBB, I, DL, get(ARM::tMOVgpr2tgpr), DestReg).addReg(SrcReg);
83 } else if (SrcRC == ARM::tGPRRegisterClass) {
84 BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg).addReg(SrcReg);
92 bool Thumb1InstrInfo::
93 canFoldMemoryOperand(const MachineInstr *MI,
94 const SmallVectorImpl<unsigned> &Ops) const {
95 if (Ops.size() != 1) return false;
97 unsigned OpNum = Ops[0];
98 unsigned Opc = MI->getOpcode();
102 case ARM::tMOVtgpr2gpr:
103 case ARM::tMOVgpr2tgpr:
104 case ARM::tMOVgpr2gpr: {
105 if (OpNum == 0) { // move -> store
106 unsigned SrcReg = MI->getOperand(1).getReg();
107 if (RI.isPhysicalRegister(SrcReg) && !isARMLowRegister(SrcReg))
108 // tSpill cannot take a high register operand.
110 } else { // move -> load
111 unsigned DstReg = MI->getOperand(0).getReg();
112 if (RI.isPhysicalRegister(DstReg) && !isARMLowRegister(DstReg))
113 // tRestore cannot target a high register operand.
123 void Thumb1InstrInfo::
124 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
125 unsigned SrcReg, bool isKill, int FI,
126 const TargetRegisterClass *RC) const {
127 DebugLoc DL = DebugLoc::getUnknownLoc();
128 if (I != MBB.end()) DL = I->getDebugLoc();
130 assert(RC == ARM::tGPRRegisterClass && "Unknown regclass!");
132 if (RC == ARM::tGPRRegisterClass) {
133 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tSpill))
134 .addReg(SrcReg, getKillRegState(isKill))
135 .addFrameIndex(FI).addImm(0));
139 void Thumb1InstrInfo::
140 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
141 unsigned DestReg, int FI,
142 const TargetRegisterClass *RC) const {
143 DebugLoc DL = DebugLoc::getUnknownLoc();
144 if (I != MBB.end()) DL = I->getDebugLoc();
146 assert(RC == ARM::tGPRRegisterClass && "Unknown regclass!");
148 if (RC == ARM::tGPRRegisterClass) {
149 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tRestore), DestReg)
150 .addFrameIndex(FI).addImm(0));
154 bool Thumb1InstrInfo::
155 spillCalleeSavedRegisters(MachineBasicBlock &MBB,
156 MachineBasicBlock::iterator MI,
157 const std::vector<CalleeSavedInfo> &CSI) const {
161 DebugLoc DL = DebugLoc::getUnknownLoc();
162 if (MI != MBB.end()) DL = MI->getDebugLoc();
164 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, get(ARM::tPUSH));
165 for (unsigned i = CSI.size(); i != 0; --i) {
166 unsigned Reg = CSI[i-1].getReg();
167 // Add the callee-saved register as live-in. It's killed at the spill.
169 MIB.addReg(Reg, RegState::Kill);
174 bool Thumb1InstrInfo::
175 restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
176 MachineBasicBlock::iterator MI,
177 const std::vector<CalleeSavedInfo> &CSI) const {
178 MachineFunction &MF = *MBB.getParent();
179 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
183 bool isVarArg = AFI->getVarArgsRegSaveSize() > 0;
184 MachineInstr *PopMI = MF.CreateMachineInstr(get(ARM::tPOP),MI->getDebugLoc());
185 for (unsigned i = CSI.size(); i != 0; --i) {
186 unsigned Reg = CSI[i-1].getReg();
187 if (Reg == ARM::LR) {
188 // Special epilogue for vararg functions. See emitEpilogue
192 PopMI->setDesc(get(ARM::tPOP_RET));
195 PopMI->addOperand(MachineOperand::CreateReg(Reg, true));
198 // It's illegal to emit pop instruction without operands.
199 if (PopMI->getNumOperands() > 0)
200 MBB.insert(MI, PopMI);
205 MachineInstr *Thumb1InstrInfo::
206 foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
207 const SmallVectorImpl<unsigned> &Ops, int FI) const {
208 if (Ops.size() != 1) return NULL;
210 unsigned OpNum = Ops[0];
211 unsigned Opc = MI->getOpcode();
212 MachineInstr *NewMI = NULL;
216 case ARM::tMOVtgpr2gpr:
217 case ARM::tMOVgpr2tgpr:
218 case ARM::tMOVgpr2gpr: {
219 if (OpNum == 0) { // move -> store
220 unsigned SrcReg = MI->getOperand(1).getReg();
221 bool isKill = MI->getOperand(1).isKill();
222 if (RI.isPhysicalRegister(SrcReg) && !isARMLowRegister(SrcReg))
223 // tSpill cannot take a high register operand.
225 NewMI = AddDefaultPred(BuildMI(MF, MI->getDebugLoc(), get(ARM::tSpill))
226 .addReg(SrcReg, getKillRegState(isKill))
227 .addFrameIndex(FI).addImm(0));
228 } else { // move -> load
229 unsigned DstReg = MI->getOperand(0).getReg();
230 if (RI.isPhysicalRegister(DstReg) && !isARMLowRegister(DstReg))
231 // tRestore cannot target a high register operand.
233 bool isDead = MI->getOperand(0).isDead();
234 NewMI = AddDefaultPred(BuildMI(MF, MI->getDebugLoc(), get(ARM::tRestore))
236 RegState::Define | getDeadRegState(isDead))
237 .addFrameIndex(FI).addImm(0));