1 //===- Thumb1InstrInfo.cpp - Thumb-1 Instruction Information ----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Thumb-1 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "Thumb1InstrInfo.h"
16 #include "ARMGenInstrInfo.inc"
17 #include "ARMMachineFunctionInfo.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/CodeGen/MachineMemOperand.h"
21 #include "llvm/CodeGen/PseudoSourceValue.h"
22 #include "llvm/ADT/SmallVector.h"
23 #include "Thumb1InstrInfo.h"
27 Thumb1InstrInfo::Thumb1InstrInfo(const ARMSubtarget &STI)
28 : ARMBaseInstrInfo(STI), RI(*this, STI) {
31 unsigned Thumb1InstrInfo::getUnindexedOpcode(unsigned Opc) const {
35 bool Thumb1InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
36 MachineBasicBlock::iterator I,
37 unsigned DestReg, unsigned SrcReg,
38 const TargetRegisterClass *DestRC,
39 const TargetRegisterClass *SrcRC,
41 if (DestRC == ARM::GPRRegisterClass) {
42 if (SrcRC == ARM::GPRRegisterClass) {
43 BuildMI(MBB, I, DL, get(ARM::tMOVgpr2gpr), DestReg).addReg(SrcReg);
45 } else if (SrcRC == ARM::tGPRRegisterClass) {
46 BuildMI(MBB, I, DL, get(ARM::tMOVtgpr2gpr), DestReg).addReg(SrcReg);
49 } else if (DestRC == ARM::tGPRRegisterClass) {
50 if (SrcRC == ARM::GPRRegisterClass) {
51 BuildMI(MBB, I, DL, get(ARM::tMOVgpr2tgpr), DestReg).addReg(SrcReg);
53 } else if (SrcRC == ARM::tGPRRegisterClass) {
54 BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg).addReg(SrcReg);
62 bool Thumb1InstrInfo::
63 canFoldMemoryOperand(const MachineInstr *MI,
64 const SmallVectorImpl<unsigned> &Ops) const {
65 if (Ops.size() != 1) return false;
67 unsigned OpNum = Ops[0];
68 unsigned Opc = MI->getOpcode();
72 case ARM::tMOVtgpr2gpr:
73 case ARM::tMOVgpr2tgpr:
74 case ARM::tMOVgpr2gpr: {
75 if (OpNum == 0) { // move -> store
76 unsigned SrcReg = MI->getOperand(1).getReg();
77 if (TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
78 !isARMLowRegister(SrcReg))
79 // tSpill cannot take a high register operand.
81 } else { // move -> load
82 unsigned DstReg = MI->getOperand(0).getReg();
83 if (TargetRegisterInfo::isPhysicalRegister(DstReg) &&
84 !isARMLowRegister(DstReg))
85 // tRestore cannot target a high register operand.
95 void Thumb1InstrInfo::
96 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
97 unsigned SrcReg, bool isKill, int FI,
98 const TargetRegisterClass *RC,
99 const TargetRegisterInfo *TRI) const {
100 assert((RC == ARM::tGPRRegisterClass ||
101 (TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
102 isARMLowRegister(SrcReg))) && "Unknown regclass!");
104 if (RC == ARM::tGPRRegisterClass ||
105 (TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
106 isARMLowRegister(SrcReg))) {
108 if (I != MBB.end()) DL = I->getDebugLoc();
110 MachineFunction &MF = *MBB.getParent();
111 MachineFrameInfo &MFI = *MF.getFrameInfo();
112 MachineMemOperand *MMO =
113 MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI),
114 MachineMemOperand::MOStore, 0,
115 MFI.getObjectSize(FI),
116 MFI.getObjectAlignment(FI));
117 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tSpill))
118 .addReg(SrcReg, getKillRegState(isKill))
119 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
123 void Thumb1InstrInfo::
124 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
125 unsigned DestReg, int FI,
126 const TargetRegisterClass *RC,
127 const TargetRegisterInfo *TRI) const {
128 assert((RC == ARM::tGPRRegisterClass ||
129 (TargetRegisterInfo::isPhysicalRegister(DestReg) &&
130 isARMLowRegister(DestReg))) && "Unknown regclass!");
132 if (RC == ARM::tGPRRegisterClass ||
133 (TargetRegisterInfo::isPhysicalRegister(DestReg) &&
134 isARMLowRegister(DestReg))) {
136 if (I != MBB.end()) DL = I->getDebugLoc();
138 MachineFunction &MF = *MBB.getParent();
139 MachineFrameInfo &MFI = *MF.getFrameInfo();
140 MachineMemOperand *MMO =
141 MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI),
142 MachineMemOperand::MOLoad, 0,
143 MFI.getObjectSize(FI),
144 MFI.getObjectAlignment(FI));
145 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tRestore), DestReg)
146 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
150 bool Thumb1InstrInfo::
151 spillCalleeSavedRegisters(MachineBasicBlock &MBB,
152 MachineBasicBlock::iterator MI,
153 const std::vector<CalleeSavedInfo> &CSI) const {
158 if (MI != MBB.end()) DL = MI->getDebugLoc();
160 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, get(ARM::tPUSH));
162 for (unsigned i = CSI.size(); i != 0; --i) {
163 unsigned Reg = CSI[i-1].getReg();
164 // Add the callee-saved register as live-in. It's killed at the spill.
166 MIB.addReg(Reg, RegState::Kill);
171 bool Thumb1InstrInfo::
172 restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
173 MachineBasicBlock::iterator MI,
174 const std::vector<CalleeSavedInfo> &CSI) const {
175 MachineFunction &MF = *MBB.getParent();
176 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
180 bool isVarArg = AFI->getVarArgsRegSaveSize() > 0;
181 DebugLoc DL = MI->getDebugLoc();
182 MachineInstrBuilder MIB = BuildMI(MF, DL, get(ARM::tPOP));
185 bool NumRegs = false;
186 for (unsigned i = CSI.size(); i != 0; --i) {
187 unsigned Reg = CSI[i-1].getReg();
188 if (Reg == ARM::LR) {
189 // Special epilogue for vararg functions. See emitEpilogue
193 (*MIB).setDesc(get(ARM::tPOP_RET));
196 MIB.addReg(Reg, getDefRegState(true));
200 // It's illegal to emit pop instruction without operands.
202 MBB.insert(MI, &*MIB);
204 MF.DeleteMachineInstr(MIB);
209 MachineInstr *Thumb1InstrInfo::
210 foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
211 const SmallVectorImpl<unsigned> &Ops, int FI) const {
212 if (Ops.size() != 1) return NULL;
214 unsigned OpNum = Ops[0];
215 unsigned Opc = MI->getOpcode();
216 MachineInstr *NewMI = NULL;
220 case ARM::tMOVtgpr2gpr:
221 case ARM::tMOVgpr2tgpr:
222 case ARM::tMOVgpr2gpr: {
223 if (OpNum == 0) { // move -> store
224 unsigned SrcReg = MI->getOperand(1).getReg();
225 bool isKill = MI->getOperand(1).isKill();
226 if (TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
227 !isARMLowRegister(SrcReg))
228 // tSpill cannot take a high register operand.
230 NewMI = AddDefaultPred(BuildMI(MF, MI->getDebugLoc(), get(ARM::tSpill))
231 .addReg(SrcReg, getKillRegState(isKill))
232 .addFrameIndex(FI).addImm(0));
233 } else { // move -> load
234 unsigned DstReg = MI->getOperand(0).getReg();
235 if (TargetRegisterInfo::isPhysicalRegister(DstReg) &&
236 !isARMLowRegister(DstReg))
237 // tRestore cannot target a high register operand.
239 bool isDead = MI->getOperand(0).isDead();
240 NewMI = AddDefaultPred(BuildMI(MF, MI->getDebugLoc(), get(ARM::tRestore))
242 RegState::Define | getDeadRegState(isDead))
243 .addFrameIndex(FI).addImm(0));