1 //===- Thumb1InstrInfo.cpp - Thumb-1 Instruction Information ----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Thumb-1 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "Thumb1InstrInfo.h"
16 #include "ARMMachineFunctionInfo.h"
17 #include "llvm/CodeGen/MachineFrameInfo.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/MachineRegisterInfo.h"
20 #include "llvm/CodeGen/MachineMemOperand.h"
21 #include "llvm/CodeGen/PseudoSourceValue.h"
22 #include "llvm/ADT/SmallVector.h"
23 #include "Thumb1InstrInfo.h"
27 Thumb1InstrInfo::Thumb1InstrInfo(const ARMSubtarget &STI)
28 : ARMBaseInstrInfo(STI), RI(*this, STI) {
31 unsigned Thumb1InstrInfo::getUnindexedOpcode(unsigned Opc) const {
35 void Thumb1InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
36 MachineBasicBlock::iterator I, DebugLoc DL,
37 unsigned DestReg, unsigned SrcReg,
39 bool tDest = ARM::tGPRRegClass.contains(DestReg);
40 bool tSrc = ARM::tGPRRegClass.contains(SrcReg);
41 unsigned Opc = ARM::tMOVgpr2gpr;
45 Opc = ARM::tMOVtgpr2gpr;
47 Opc = ARM::tMOVgpr2tgpr;
49 AddDefaultPred(BuildMI(MBB, I, DL, get(Opc), DestReg)
50 .addReg(SrcReg, getKillRegState(KillSrc)));
51 assert(ARM::GPRRegClass.contains(DestReg, SrcReg) &&
52 "Thumb1 can only copy GPR registers");
55 void Thumb1InstrInfo::
56 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
57 unsigned SrcReg, bool isKill, int FI,
58 const TargetRegisterClass *RC,
59 const TargetRegisterInfo *TRI) const {
60 assert((RC == ARM::tGPRRegisterClass ||
61 (TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
62 isARMLowRegister(SrcReg))) && "Unknown regclass!");
64 if (RC == ARM::tGPRRegisterClass ||
65 (TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
66 isARMLowRegister(SrcReg))) {
68 if (I != MBB.end()) DL = I->getDebugLoc();
70 MachineFunction &MF = *MBB.getParent();
71 MachineFrameInfo &MFI = *MF.getFrameInfo();
72 MachineMemOperand *MMO =
73 MF.getMachineMemOperand(
74 MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)),
75 MachineMemOperand::MOStore,
76 MFI.getObjectSize(FI),
77 MFI.getObjectAlignment(FI));
78 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tSTRspi))
79 .addReg(SrcReg, getKillRegState(isKill))
80 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
84 void Thumb1InstrInfo::
85 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
86 unsigned DestReg, int FI,
87 const TargetRegisterClass *RC,
88 const TargetRegisterInfo *TRI) const {
89 assert((RC == ARM::tGPRRegisterClass ||
90 (TargetRegisterInfo::isPhysicalRegister(DestReg) &&
91 isARMLowRegister(DestReg))) && "Unknown regclass!");
93 if (RC == ARM::tGPRRegisterClass ||
94 (TargetRegisterInfo::isPhysicalRegister(DestReg) &&
95 isARMLowRegister(DestReg))) {
97 if (I != MBB.end()) DL = I->getDebugLoc();
99 MachineFunction &MF = *MBB.getParent();
100 MachineFrameInfo &MFI = *MF.getFrameInfo();
101 MachineMemOperand *MMO =
102 MF.getMachineMemOperand(
103 MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)),
104 MachineMemOperand::MOLoad,
105 MFI.getObjectSize(FI),
106 MFI.getObjectAlignment(FI));
107 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tLDRspi), DestReg)
108 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));