1 //===- Thumb1InstrInfo.cpp - Thumb-1 Instruction Information --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Thumb-1 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "ARMInstrInfo.h"
16 #include "ARMGenInstrInfo.inc"
17 #include "ARMMachineFunctionInfo.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/ADT/SmallVector.h"
21 #include "Thumb1InstrInfo.h"
25 Thumb1InstrInfo::Thumb1InstrInfo(const ARMSubtarget &STI)
26 : ARMBaseInstrInfo(STI), RI(*this, STI) {
29 unsigned Thumb1InstrInfo::getUnindexedOpcode(unsigned Opc) const {
34 Thumb1InstrInfo::BlockHasNoFallThrough(const MachineBasicBlock &MBB) const {
35 if (MBB.empty()) return false;
37 switch (MBB.back().getOpcode()) {
39 case ARM::tBX_RET_vararg:
51 bool Thumb1InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
52 MachineBasicBlock::iterator I,
53 unsigned DestReg, unsigned SrcReg,
54 const TargetRegisterClass *DestRC,
55 const TargetRegisterClass *SrcRC) const {
56 DebugLoc DL = DebugLoc::getUnknownLoc();
57 if (I != MBB.end()) DL = I->getDebugLoc();
59 if (DestRC == ARM::GPRRegisterClass) {
60 if (SrcRC == ARM::GPRRegisterClass) {
61 BuildMI(MBB, I, DL, get(ARM::tMOVgpr2gpr), DestReg).addReg(SrcReg);
63 } else if (SrcRC == ARM::tGPRRegisterClass) {
64 BuildMI(MBB, I, DL, get(ARM::tMOVtgpr2gpr), DestReg).addReg(SrcReg);
67 } else if (DestRC == ARM::tGPRRegisterClass) {
68 if (SrcRC == ARM::GPRRegisterClass) {
69 BuildMI(MBB, I, DL, get(ARM::tMOVgpr2tgpr), DestReg).addReg(SrcReg);
71 } else if (SrcRC == ARM::tGPRRegisterClass) {
72 BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg).addReg(SrcReg);
80 bool Thumb1InstrInfo::
81 canFoldMemoryOperand(const MachineInstr *MI,
82 const SmallVectorImpl<unsigned> &Ops) const {
83 if (Ops.size() != 1) return false;
85 unsigned OpNum = Ops[0];
86 unsigned Opc = MI->getOpcode();
90 case ARM::tMOVtgpr2gpr:
91 case ARM::tMOVgpr2tgpr:
92 case ARM::tMOVgpr2gpr: {
93 if (OpNum == 0) { // move -> store
94 unsigned SrcReg = MI->getOperand(1).getReg();
95 if (RI.isPhysicalRegister(SrcReg) && !isARMLowRegister(SrcReg))
96 // tSpill cannot take a high register operand.
98 } else { // move -> load
99 unsigned DstReg = MI->getOperand(0).getReg();
100 if (RI.isPhysicalRegister(DstReg) && !isARMLowRegister(DstReg))
101 // tRestore cannot target a high register operand.
111 void Thumb1InstrInfo::
112 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
113 unsigned SrcReg, bool isKill, int FI,
114 const TargetRegisterClass *RC) const {
115 DebugLoc DL = DebugLoc::getUnknownLoc();
116 if (I != MBB.end()) DL = I->getDebugLoc();
118 assert(RC == ARM::tGPRRegisterClass && "Unknown regclass!");
120 if (RC == ARM::tGPRRegisterClass) {
121 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tSpill))
122 .addReg(SrcReg, getKillRegState(isKill))
123 .addFrameIndex(FI).addImm(0));
127 void Thumb1InstrInfo::
128 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
129 unsigned DestReg, int FI,
130 const TargetRegisterClass *RC) const {
131 DebugLoc DL = DebugLoc::getUnknownLoc();
132 if (I != MBB.end()) DL = I->getDebugLoc();
134 assert(RC == ARM::tGPRRegisterClass && "Unknown regclass!");
136 if (RC == ARM::tGPRRegisterClass) {
137 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tRestore), DestReg)
138 .addFrameIndex(FI).addImm(0));
142 bool Thumb1InstrInfo::
143 spillCalleeSavedRegisters(MachineBasicBlock &MBB,
144 MachineBasicBlock::iterator MI,
145 const std::vector<CalleeSavedInfo> &CSI) const {
149 DebugLoc DL = DebugLoc::getUnknownLoc();
150 if (MI != MBB.end()) DL = MI->getDebugLoc();
152 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, get(ARM::tPUSH));
153 for (unsigned i = CSI.size(); i != 0; --i) {
154 unsigned Reg = CSI[i-1].getReg();
155 // Add the callee-saved register as live-in. It's killed at the spill.
157 MIB.addReg(Reg, RegState::Kill);
162 bool Thumb1InstrInfo::
163 restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
164 MachineBasicBlock::iterator MI,
165 const std::vector<CalleeSavedInfo> &CSI) const {
166 MachineFunction &MF = *MBB.getParent();
167 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
171 bool isVarArg = AFI->getVarArgsRegSaveSize() > 0;
172 MachineInstr *PopMI = MF.CreateMachineInstr(get(ARM::tPOP),MI->getDebugLoc());
173 for (unsigned i = CSI.size(); i != 0; --i) {
174 unsigned Reg = CSI[i-1].getReg();
175 if (Reg == ARM::LR) {
176 // Special epilogue for vararg functions. See emitEpilogue
180 PopMI->setDesc(get(ARM::tPOP_RET));
183 PopMI->addOperand(MachineOperand::CreateReg(Reg, true));
186 // It's illegal to emit pop instruction without operands.
187 if (PopMI->getNumOperands() > 0)
188 MBB.insert(MI, PopMI);
193 MachineInstr *Thumb1InstrInfo::
194 foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
195 const SmallVectorImpl<unsigned> &Ops, int FI) const {
196 if (Ops.size() != 1) return NULL;
198 unsigned OpNum = Ops[0];
199 unsigned Opc = MI->getOpcode();
200 MachineInstr *NewMI = NULL;
204 case ARM::tMOVtgpr2gpr:
205 case ARM::tMOVgpr2tgpr:
206 case ARM::tMOVgpr2gpr: {
207 if (OpNum == 0) { // move -> store
208 unsigned SrcReg = MI->getOperand(1).getReg();
209 bool isKill = MI->getOperand(1).isKill();
210 if (RI.isPhysicalRegister(SrcReg) && !isARMLowRegister(SrcReg))
211 // tSpill cannot take a high register operand.
213 NewMI = AddDefaultPred(BuildMI(MF, MI->getDebugLoc(), get(ARM::tSpill))
214 .addReg(SrcReg, getKillRegState(isKill))
215 .addFrameIndex(FI).addImm(0));
216 } else { // move -> load
217 unsigned DstReg = MI->getOperand(0).getReg();
218 if (RI.isPhysicalRegister(DstReg) && !isARMLowRegister(DstReg))
219 // tRestore cannot target a high register operand.
221 bool isDead = MI->getOperand(0).isDead();
222 NewMI = AddDefaultPred(BuildMI(MF, MI->getDebugLoc(), get(ARM::tRestore))
224 RegState::Define | getDeadRegState(isDead))
225 .addFrameIndex(FI).addImm(0));