1 //===- Thumb1InstrInfo.cpp - Thumb-1 Instruction Information --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Thumb-1 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "ARMInstrInfo.h"
16 #include "ARMGenInstrInfo.inc"
17 #include "ARMMachineFunctionInfo.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/ADT/SmallVector.h"
21 #include "Thumb1InstrInfo.h"
25 Thumb1InstrInfo::Thumb1InstrInfo(const ARMSubtarget &STI) : RI(*this, STI) {
28 unsigned Thumb1InstrInfo::getUnindexedOpcode(unsigned Opc) const {
33 Thumb1InstrInfo::BlockHasNoFallThrough(const MachineBasicBlock &MBB) const {
34 if (MBB.empty()) return false;
36 switch (MBB.back().getOpcode()) {
38 case ARM::tBX_RET_vararg:
51 bool Thumb1InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
52 MachineBasicBlock::iterator I,
53 unsigned DestReg, unsigned SrcReg,
54 const TargetRegisterClass *DestRC,
55 const TargetRegisterClass *SrcRC) const {
56 DebugLoc DL = DebugLoc::getUnknownLoc();
57 if (I != MBB.end()) DL = I->getDebugLoc();
59 if (DestRC == ARM::GPRRegisterClass) {
60 if (SrcRC == ARM::GPRRegisterClass) {
61 BuildMI(MBB, I, DL, get(ARM::tMOVgpr2gpr), DestReg).addReg(SrcReg);
63 } else if (SrcRC == ARM::tGPRRegisterClass) {
64 BuildMI(MBB, I, DL, get(ARM::tMOVtgpr2gpr), DestReg).addReg(SrcReg);
67 } else if (DestRC == ARM::tGPRRegisterClass) {
68 if (SrcRC == ARM::GPRRegisterClass) {
69 BuildMI(MBB, I, DL, get(ARM::tMOVgpr2tgpr), DestReg).addReg(SrcReg);
71 } else if (SrcRC == ARM::tGPRRegisterClass) {
72 BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg).addReg(SrcReg);
80 bool Thumb1InstrInfo::
81 canFoldMemoryOperand(const MachineInstr *MI,
82 const SmallVectorImpl<unsigned> &Ops) const {
83 if (Ops.size() != 1) return false;
85 unsigned OpNum = Ops[0];
86 unsigned Opc = MI->getOpcode();
90 case ARM::tMOVtgpr2gpr:
91 case ARM::tMOVgpr2tgpr:
92 case ARM::tMOVgpr2gpr: {
93 if (OpNum == 0) { // move -> store
94 unsigned SrcReg = MI->getOperand(1).getReg();
95 if (TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
96 !isARMLowRegister(SrcReg))
97 // tSpill cannot take a high register operand.
99 } else { // move -> load
100 unsigned DstReg = MI->getOperand(0).getReg();
101 if (TargetRegisterInfo::isPhysicalRegister(DstReg) &&
102 !isARMLowRegister(DstReg))
103 // tRestore cannot target a high register operand.
113 void Thumb1InstrInfo::
114 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
115 unsigned SrcReg, bool isKill, int FI,
116 const TargetRegisterClass *RC) const {
117 DebugLoc DL = DebugLoc::getUnknownLoc();
118 if (I != MBB.end()) DL = I->getDebugLoc();
120 assert((RC == ARM::tGPRRegisterClass ||
121 (TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
122 isARMLowRegister(SrcReg))) && "Unknown regclass!");
124 if (RC == ARM::tGPRRegisterClass) {
125 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tSpill))
126 .addReg(SrcReg, getKillRegState(isKill))
127 .addFrameIndex(FI).addImm(0));
131 void Thumb1InstrInfo::
132 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
133 unsigned DestReg, int FI,
134 const TargetRegisterClass *RC) const {
135 DebugLoc DL = DebugLoc::getUnknownLoc();
136 if (I != MBB.end()) DL = I->getDebugLoc();
138 assert((RC == ARM::tGPRRegisterClass ||
139 (TargetRegisterInfo::isPhysicalRegister(DestReg) &&
140 isARMLowRegister(DestReg))) && "Unknown regclass!");
142 if (RC == ARM::tGPRRegisterClass) {
143 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tRestore), DestReg)
144 .addFrameIndex(FI).addImm(0));
148 bool Thumb1InstrInfo::
149 spillCalleeSavedRegisters(MachineBasicBlock &MBB,
150 MachineBasicBlock::iterator MI,
151 const std::vector<CalleeSavedInfo> &CSI) const {
155 DebugLoc DL = DebugLoc::getUnknownLoc();
156 if (MI != MBB.end()) DL = MI->getDebugLoc();
158 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, get(ARM::tPUSH));
160 MIB.addReg(0); // No write back.
161 for (unsigned i = CSI.size(); i != 0; --i) {
162 unsigned Reg = CSI[i-1].getReg();
163 // Add the callee-saved register as live-in. It's killed at the spill.
165 MIB.addReg(Reg, RegState::Kill);
170 bool Thumb1InstrInfo::
171 restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
172 MachineBasicBlock::iterator MI,
173 const std::vector<CalleeSavedInfo> &CSI) const {
174 MachineFunction &MF = *MBB.getParent();
175 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
179 bool isVarArg = AFI->getVarArgsRegSaveSize() > 0;
180 DebugLoc DL = MI->getDebugLoc();
181 MachineInstrBuilder MIB = BuildMI(MF, DL, get(ARM::tPOP));
183 MIB.addReg(0); // No write back.
186 for (unsigned i = CSI.size(); i != 0; --i) {
187 unsigned Reg = CSI[i-1].getReg();
188 if (Reg == ARM::LR) {
189 // Special epilogue for vararg functions. See emitEpilogue
193 (*MIB).setDesc(get(ARM::tPOP_RET));
196 MIB.addReg(Reg, getDefRegState(true));
200 // It's illegal to emit pop instruction without operands.
202 MBB.insert(MI, &*MIB);
207 MachineInstr *Thumb1InstrInfo::
208 foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
209 const SmallVectorImpl<unsigned> &Ops, int FI) const {
210 if (Ops.size() != 1) return NULL;
212 unsigned OpNum = Ops[0];
213 unsigned Opc = MI->getOpcode();
214 MachineInstr *NewMI = NULL;
218 case ARM::tMOVtgpr2gpr:
219 case ARM::tMOVgpr2tgpr:
220 case ARM::tMOVgpr2gpr: {
221 if (OpNum == 0) { // move -> store
222 unsigned SrcReg = MI->getOperand(1).getReg();
223 bool isKill = MI->getOperand(1).isKill();
224 if (TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
225 !isARMLowRegister(SrcReg))
226 // tSpill cannot take a high register operand.
228 NewMI = AddDefaultPred(BuildMI(MF, MI->getDebugLoc(), get(ARM::tSpill))
229 .addReg(SrcReg, getKillRegState(isKill))
230 .addFrameIndex(FI).addImm(0));
231 } else { // move -> load
232 unsigned DstReg = MI->getOperand(0).getReg();
233 if (TargetRegisterInfo::isPhysicalRegister(DstReg) &&
234 !isARMLowRegister(DstReg))
235 // tRestore cannot target a high register operand.
237 bool isDead = MI->getOperand(0).isDead();
238 NewMI = AddDefaultPred(BuildMI(MF, MI->getDebugLoc(), get(ARM::tRestore))
240 RegState::Define | getDeadRegState(isDead))
241 .addFrameIndex(FI).addImm(0));