1 //===- Thumb1InstrInfo.cpp - Thumb-1 Instruction Information --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Thumb-1 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "ARMInstrInfo.h"
16 #include "ARMGenInstrInfo.inc"
17 #include "ARMMachineFunctionInfo.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/ADT/SmallVector.h"
21 #include "Thumb1InstrInfo.h"
25 Thumb1InstrInfo::Thumb1InstrInfo(const ARMSubtarget &STI)
26 : ARMBaseInstrInfo(STI), RI(*this, STI) {
29 unsigned Thumb1InstrInfo::getUnindexedOpcode(unsigned Opc) const {
33 unsigned Thumb1InstrInfo::getOpcode(ARMII::Op Op) const {
35 case ARMII::ADDri: return ARM::tADDi8;
36 case ARMII::ADDrs: return 0;
37 case ARMII::ADDrr: return ARM::tADDrr;
38 case ARMII::B: return ARM::tB;
39 case ARMII::Bcc: return ARM::tBcc;
40 case ARMII::BX_RET: return ARM::tBX_RET;
41 case ARMII::LDRrr: return ARM::tLDR;
42 case ARMII::LDRri: return 0;
43 case ARMII::MOVr: return ARM::tMOVr;
44 case ARMII::STRrr: return ARM::tSTR;
45 case ARMII::STRri: return 0;
46 case ARMII::SUBri: return ARM::tSUBi8;
47 case ARMII::SUBrs: return 0;
48 case ARMII::SUBrr: return ARM::tSUBrr;
57 Thumb1InstrInfo::BlockHasNoFallThrough(const MachineBasicBlock &MBB) const {
58 if (MBB.empty()) return false;
60 switch (MBB.back().getOpcode()) {
62 case ARM::tBX_RET_vararg:
74 bool Thumb1InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
75 MachineBasicBlock::iterator I,
76 unsigned DestReg, unsigned SrcReg,
77 const TargetRegisterClass *DestRC,
78 const TargetRegisterClass *SrcRC) const {
79 DebugLoc DL = DebugLoc::getUnknownLoc();
80 if (I != MBB.end()) DL = I->getDebugLoc();
82 if (DestRC == ARM::GPRRegisterClass) {
83 if (SrcRC == ARM::GPRRegisterClass) {
84 BuildMI(MBB, I, DL, get(ARM::tMOVgpr2gpr), DestReg).addReg(SrcReg);
86 } else if (SrcRC == ARM::tGPRRegisterClass) {
87 BuildMI(MBB, I, DL, get(ARM::tMOVtgpr2gpr), DestReg).addReg(SrcReg);
90 } else if (DestRC == ARM::tGPRRegisterClass) {
91 if (SrcRC == ARM::GPRRegisterClass) {
92 BuildMI(MBB, I, DL, get(ARM::tMOVgpr2tgpr), DestReg).addReg(SrcReg);
94 } else if (SrcRC == ARM::tGPRRegisterClass) {
95 BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg).addReg(SrcReg);
103 bool Thumb1InstrInfo::
104 canFoldMemoryOperand(const MachineInstr *MI,
105 const SmallVectorImpl<unsigned> &Ops) const {
106 if (Ops.size() != 1) return false;
108 unsigned OpNum = Ops[0];
109 unsigned Opc = MI->getOpcode();
113 case ARM::tMOVtgpr2gpr:
114 case ARM::tMOVgpr2tgpr:
115 case ARM::tMOVgpr2gpr: {
116 if (OpNum == 0) { // move -> store
117 unsigned SrcReg = MI->getOperand(1).getReg();
118 if (RI.isPhysicalRegister(SrcReg) && !isARMLowRegister(SrcReg))
119 // tSpill cannot take a high register operand.
121 } else { // move -> load
122 unsigned DstReg = MI->getOperand(0).getReg();
123 if (RI.isPhysicalRegister(DstReg) && !isARMLowRegister(DstReg))
124 // tRestore cannot target a high register operand.
134 void Thumb1InstrInfo::
135 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
136 unsigned SrcReg, bool isKill, int FI,
137 const TargetRegisterClass *RC) const {
138 DebugLoc DL = DebugLoc::getUnknownLoc();
139 if (I != MBB.end()) DL = I->getDebugLoc();
141 assert(RC == ARM::tGPRRegisterClass && "Unknown regclass!");
143 if (RC == ARM::tGPRRegisterClass) {
144 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tSpill))
145 .addReg(SrcReg, getKillRegState(isKill))
146 .addFrameIndex(FI).addImm(0));
150 void Thumb1InstrInfo::
151 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
152 unsigned DestReg, int FI,
153 const TargetRegisterClass *RC) const {
154 DebugLoc DL = DebugLoc::getUnknownLoc();
155 if (I != MBB.end()) DL = I->getDebugLoc();
157 assert(RC == ARM::tGPRRegisterClass && "Unknown regclass!");
159 if (RC == ARM::tGPRRegisterClass) {
160 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tRestore), DestReg)
161 .addFrameIndex(FI).addImm(0));
165 bool Thumb1InstrInfo::
166 spillCalleeSavedRegisters(MachineBasicBlock &MBB,
167 MachineBasicBlock::iterator MI,
168 const std::vector<CalleeSavedInfo> &CSI) const {
172 DebugLoc DL = DebugLoc::getUnknownLoc();
173 if (MI != MBB.end()) DL = MI->getDebugLoc();
175 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, get(ARM::tPUSH));
176 for (unsigned i = CSI.size(); i != 0; --i) {
177 unsigned Reg = CSI[i-1].getReg();
178 // Add the callee-saved register as live-in. It's killed at the spill.
180 MIB.addReg(Reg, RegState::Kill);
185 bool Thumb1InstrInfo::
186 restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
187 MachineBasicBlock::iterator MI,
188 const std::vector<CalleeSavedInfo> &CSI) const {
189 MachineFunction &MF = *MBB.getParent();
190 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
194 bool isVarArg = AFI->getVarArgsRegSaveSize() > 0;
195 MachineInstr *PopMI = MF.CreateMachineInstr(get(ARM::tPOP),MI->getDebugLoc());
196 for (unsigned i = CSI.size(); i != 0; --i) {
197 unsigned Reg = CSI[i-1].getReg();
198 if (Reg == ARM::LR) {
199 // Special epilogue for vararg functions. See emitEpilogue
203 PopMI->setDesc(get(ARM::tPOP_RET));
206 PopMI->addOperand(MachineOperand::CreateReg(Reg, true));
209 // It's illegal to emit pop instruction without operands.
210 if (PopMI->getNumOperands() > 0)
211 MBB.insert(MI, PopMI);
216 MachineInstr *Thumb1InstrInfo::
217 foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
218 const SmallVectorImpl<unsigned> &Ops, int FI) const {
219 if (Ops.size() != 1) return NULL;
221 unsigned OpNum = Ops[0];
222 unsigned Opc = MI->getOpcode();
223 MachineInstr *NewMI = NULL;
227 case ARM::tMOVtgpr2gpr:
228 case ARM::tMOVgpr2tgpr:
229 case ARM::tMOVgpr2gpr: {
230 if (OpNum == 0) { // move -> store
231 unsigned SrcReg = MI->getOperand(1).getReg();
232 bool isKill = MI->getOperand(1).isKill();
233 if (RI.isPhysicalRegister(SrcReg) && !isARMLowRegister(SrcReg))
234 // tSpill cannot take a high register operand.
236 NewMI = AddDefaultPred(BuildMI(MF, MI->getDebugLoc(), get(ARM::tSpill))
237 .addReg(SrcReg, getKillRegState(isKill))
238 .addFrameIndex(FI).addImm(0));
239 } else { // move -> load
240 unsigned DstReg = MI->getOperand(0).getReg();
241 if (RI.isPhysicalRegister(DstReg) && !isARMLowRegister(DstReg))
242 // tRestore cannot target a high register operand.
244 bool isDead = MI->getOperand(0).isDead();
245 NewMI = AddDefaultPred(BuildMI(MF, MI->getDebugLoc(), get(ARM::tRestore))
247 RegState::Define | getDeadRegState(isDead))
248 .addFrameIndex(FI).addImm(0));