1 //===- Thumb1InstrInfo.cpp - Thumb-1 Instruction Information --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Thumb-1 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "ARMInstrInfo.h"
16 #include "ARMGenInstrInfo.inc"
17 #include "ARMMachineFunctionInfo.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/CodeGen/MachineMemOperand.h"
21 #include "llvm/CodeGen/PseudoSourceValue.h"
22 #include "llvm/ADT/SmallVector.h"
23 #include "Thumb1InstrInfo.h"
27 Thumb1InstrInfo::Thumb1InstrInfo(const ARMSubtarget &STI) : RI(*this, STI) {
30 unsigned Thumb1InstrInfo::getUnindexedOpcode(unsigned Opc) const {
35 Thumb1InstrInfo::BlockHasNoFallThrough(const MachineBasicBlock &MBB) const {
36 if (MBB.empty()) return false;
38 switch (MBB.back().getOpcode()) {
40 case ARM::tBX_RET_vararg:
53 bool Thumb1InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
54 MachineBasicBlock::iterator I,
55 unsigned DestReg, unsigned SrcReg,
56 const TargetRegisterClass *DestRC,
57 const TargetRegisterClass *SrcRC) const {
58 DebugLoc DL = DebugLoc::getUnknownLoc();
59 if (I != MBB.end()) DL = I->getDebugLoc();
61 if (DestRC == ARM::GPRRegisterClass) {
62 if (SrcRC == ARM::GPRRegisterClass) {
63 BuildMI(MBB, I, DL, get(ARM::tMOVgpr2gpr), DestReg).addReg(SrcReg);
65 } else if (SrcRC == ARM::tGPRRegisterClass) {
66 BuildMI(MBB, I, DL, get(ARM::tMOVtgpr2gpr), DestReg).addReg(SrcReg);
69 } else if (DestRC == ARM::tGPRRegisterClass) {
70 if (SrcRC == ARM::GPRRegisterClass) {
71 BuildMI(MBB, I, DL, get(ARM::tMOVgpr2tgpr), DestReg).addReg(SrcReg);
73 } else if (SrcRC == ARM::tGPRRegisterClass) {
74 BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg).addReg(SrcReg);
82 bool Thumb1InstrInfo::
83 canFoldMemoryOperand(const MachineInstr *MI,
84 const SmallVectorImpl<unsigned> &Ops) const {
85 if (Ops.size() != 1) return false;
87 unsigned OpNum = Ops[0];
88 unsigned Opc = MI->getOpcode();
92 case ARM::tMOVtgpr2gpr:
93 case ARM::tMOVgpr2tgpr:
94 case ARM::tMOVgpr2gpr: {
95 if (OpNum == 0) { // move -> store
96 unsigned SrcReg = MI->getOperand(1).getReg();
97 if (TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
98 !isARMLowRegister(SrcReg))
99 // tSpill cannot take a high register operand.
101 } else { // move -> load
102 unsigned DstReg = MI->getOperand(0).getReg();
103 if (TargetRegisterInfo::isPhysicalRegister(DstReg) &&
104 !isARMLowRegister(DstReg))
105 // tRestore cannot target a high register operand.
115 void Thumb1InstrInfo::
116 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
117 unsigned SrcReg, bool isKill, int FI,
118 const TargetRegisterClass *RC) const {
119 DebugLoc DL = DebugLoc::getUnknownLoc();
120 if (I != MBB.end()) DL = I->getDebugLoc();
122 assert((RC == ARM::tGPRRegisterClass ||
123 (TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
124 isARMLowRegister(SrcReg))) && "Unknown regclass!");
126 if (RC == ARM::tGPRRegisterClass) {
127 MachineFunction &MF = *MBB.getParent();
128 MachineFrameInfo &MFI = *MF.getFrameInfo();
129 MachineMemOperand *MMO =
130 MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI),
131 MachineMemOperand::MOStore, 0,
132 MFI.getObjectSize(FI),
133 MFI.getObjectAlignment(FI));
134 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tSpill))
135 .addReg(SrcReg, getKillRegState(isKill))
136 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
140 void Thumb1InstrInfo::
141 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
142 unsigned DestReg, int FI,
143 const TargetRegisterClass *RC) const {
144 DebugLoc DL = DebugLoc::getUnknownLoc();
145 if (I != MBB.end()) DL = I->getDebugLoc();
147 assert((RC == ARM::tGPRRegisterClass ||
148 (TargetRegisterInfo::isPhysicalRegister(DestReg) &&
149 isARMLowRegister(DestReg))) && "Unknown regclass!");
151 if (RC == ARM::tGPRRegisterClass) {
152 MachineFunction &MF = *MBB.getParent();
153 MachineFrameInfo &MFI = *MF.getFrameInfo();
154 MachineMemOperand *MMO =
155 MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI),
156 MachineMemOperand::MOLoad, 0,
157 MFI.getObjectSize(FI),
158 MFI.getObjectAlignment(FI));
159 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tRestore), DestReg)
160 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
164 bool Thumb1InstrInfo::
165 spillCalleeSavedRegisters(MachineBasicBlock &MBB,
166 MachineBasicBlock::iterator MI,
167 const std::vector<CalleeSavedInfo> &CSI) const {
171 DebugLoc DL = DebugLoc::getUnknownLoc();
172 if (MI != MBB.end()) DL = MI->getDebugLoc();
174 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, get(ARM::tPUSH));
176 MIB.addReg(0); // No write back.
177 for (unsigned i = CSI.size(); i != 0; --i) {
178 unsigned Reg = CSI[i-1].getReg();
179 // Add the callee-saved register as live-in. It's killed at the spill.
181 MIB.addReg(Reg, RegState::Kill);
186 bool Thumb1InstrInfo::
187 restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
188 MachineBasicBlock::iterator MI,
189 const std::vector<CalleeSavedInfo> &CSI) const {
190 MachineFunction &MF = *MBB.getParent();
191 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
195 bool isVarArg = AFI->getVarArgsRegSaveSize() > 0;
196 DebugLoc DL = MI->getDebugLoc();
197 MachineInstrBuilder MIB = BuildMI(MF, DL, get(ARM::tPOP));
199 MIB.addReg(0); // No write back.
202 for (unsigned i = CSI.size(); i != 0; --i) {
203 unsigned Reg = CSI[i-1].getReg();
204 if (Reg == ARM::LR) {
205 // Special epilogue for vararg functions. See emitEpilogue
209 (*MIB).setDesc(get(ARM::tPOP_RET));
212 MIB.addReg(Reg, getDefRegState(true));
216 // It's illegal to emit pop instruction without operands.
218 MBB.insert(MI, &*MIB);
223 MachineInstr *Thumb1InstrInfo::
224 foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
225 const SmallVectorImpl<unsigned> &Ops, int FI) const {
226 if (Ops.size() != 1) return NULL;
228 unsigned OpNum = Ops[0];
229 unsigned Opc = MI->getOpcode();
230 MachineInstr *NewMI = NULL;
234 case ARM::tMOVtgpr2gpr:
235 case ARM::tMOVgpr2tgpr:
236 case ARM::tMOVgpr2gpr: {
237 if (OpNum == 0) { // move -> store
238 unsigned SrcReg = MI->getOperand(1).getReg();
239 bool isKill = MI->getOperand(1).isKill();
240 if (TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
241 !isARMLowRegister(SrcReg))
242 // tSpill cannot take a high register operand.
244 NewMI = AddDefaultPred(BuildMI(MF, MI->getDebugLoc(), get(ARM::tSpill))
245 .addReg(SrcReg, getKillRegState(isKill))
246 .addFrameIndex(FI).addImm(0));
247 } else { // move -> load
248 unsigned DstReg = MI->getOperand(0).getReg();
249 if (TargetRegisterInfo::isPhysicalRegister(DstReg) &&
250 !isARMLowRegister(DstReg))
251 // tRestore cannot target a high register operand.
253 bool isDead = MI->getOperand(0).isDead();
254 NewMI = AddDefaultPred(BuildMI(MF, MI->getDebugLoc(), get(ARM::tRestore))
256 RegState::Define | getDeadRegState(isDead))
257 .addFrameIndex(FI).addImm(0));