1 //===-- Thumb1InstrInfo.h - Thumb-1 Instruction Information -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Thumb-1 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef THUMB1INSTRUCTIONINFO_H
15 #define THUMB1INSTRUCTIONINFO_H
17 #include "llvm/Target/TargetInstrInfo.h"
19 #include "ARMInstrInfo.h"
20 #include "Thumb1RegisterInfo.h"
25 class Thumb1InstrInfo : public ARMBaseInstrInfo {
26 Thumb1RegisterInfo RI;
28 explicit Thumb1InstrInfo(const ARMSubtarget &STI);
30 /// getNoopForMachoTarget - Return the noop instruction to use for a noop.
31 void getNoopForMachoTarget(MCInst &NopInst) const;
33 // Return the non-pre/post incrementing version of 'Opc'. Return 0
34 // if there is not such an opcode.
35 unsigned getUnindexedOpcode(unsigned Opc) const;
37 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
38 /// such, whenever a client has an instance of instruction info, it should
39 /// always be able to get register info as well (through this method).
41 const Thumb1RegisterInfo &getRegisterInfo() const { return RI; }
43 void copyPhysReg(MachineBasicBlock &MBB,
44 MachineBasicBlock::iterator I, DebugLoc DL,
45 unsigned DestReg, unsigned SrcReg,
47 void storeRegToStackSlot(MachineBasicBlock &MBB,
48 MachineBasicBlock::iterator MBBI,
49 unsigned SrcReg, bool isKill, int FrameIndex,
50 const TargetRegisterClass *RC,
51 const TargetRegisterInfo *TRI) const;
53 void loadRegFromStackSlot(MachineBasicBlock &MBB,
54 MachineBasicBlock::iterator MBBI,
55 unsigned DestReg, int FrameIndex,
56 const TargetRegisterClass *RC,
57 const TargetRegisterInfo *TRI) const;
62 #endif // THUMB1INSTRUCTIONINFO_H