1 //===- Thumb1RegisterInfo.cpp - Thumb-1 Register Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Thumb-1 implementation of the TargetRegisterInfo class.
12 //===----------------------------------------------------------------------===//
15 #include "ARMAddressingModes.h"
16 #include "ARMBaseInstrInfo.h"
17 #include "ARMMachineFunctionInfo.h"
18 #include "ARMSubtarget.h"
19 #include "Thumb1InstrInfo.h"
20 #include "Thumb1RegisterInfo.h"
21 #include "llvm/Constants.h"
22 #include "llvm/DerivedTypes.h"
23 #include "llvm/Function.h"
24 #include "llvm/LLVMContext.h"
25 #include "llvm/CodeGen/MachineConstantPool.h"
26 #include "llvm/CodeGen/MachineFrameInfo.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineInstrBuilder.h"
29 #include "llvm/CodeGen/MachineLocation.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/Target/TargetFrameInfo.h"
32 #include "llvm/Target/TargetMachine.h"
33 #include "llvm/ADT/BitVector.h"
34 #include "llvm/ADT/SmallVector.h"
35 #include "llvm/Support/CommandLine.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Support/raw_ostream.h"
41 ThumbRegScavenging("enable-thumb-reg-scavenging",
43 cl::desc("Enable register scavenging on Thumb"));
45 Thumb1RegisterInfo::Thumb1RegisterInfo(const ARMBaseInstrInfo &tii,
46 const ARMSubtarget &sti)
47 : ARMBaseRegisterInfo(tii, sti) {
50 /// emitLoadConstPool - Emits a load from constpool to materialize the
51 /// specified immediate.
52 void Thumb1RegisterInfo::emitLoadConstPool(MachineBasicBlock &MBB,
53 MachineBasicBlock::iterator &MBBI,
55 unsigned DestReg, unsigned SubIdx,
57 ARMCC::CondCodes Pred,
58 unsigned PredReg) const {
59 MachineFunction &MF = *MBB.getParent();
60 MachineConstantPool *ConstantPool = MF.getConstantPool();
62 MF.getFunction()->getContext().getConstantInt(Type::Int32Ty, Val);
63 unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
65 BuildMI(MBB, MBBI, dl, TII.get(ARM::tLDRcp))
66 .addReg(DestReg, getDefRegState(true), SubIdx)
67 .addConstantPoolIndex(Idx).addImm(Pred).addReg(PredReg);
70 const TargetRegisterClass*
71 Thumb1RegisterInfo::getPhysicalRegisterRegClass(unsigned Reg, MVT VT) const {
72 if (isARMLowRegister(Reg))
73 return ARM::tGPRRegisterClass;
77 case ARM::R8: case ARM::R9: case ARM::R10: case ARM::R11:
78 case ARM::R12: case ARM::SP: case ARM::LR: case ARM::PC:
79 return ARM::GPRRegisterClass;
82 return TargetRegisterInfo::getPhysicalRegisterRegClass(Reg, VT);
86 Thumb1RegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const {
87 return ThumbRegScavenging;
90 bool Thumb1RegisterInfo::hasReservedCallFrame(MachineFunction &MF) const {
91 const MachineFrameInfo *FFI = MF.getFrameInfo();
92 unsigned CFSize = FFI->getMaxCallFrameSize();
93 // It's not always a good idea to include the call frame as part of the
94 // stack frame. ARM (especially Thumb) has small immediate offset to
95 // address the stack frame. So a large call frame can cause poor codegen
96 // and may even makes it impossible to scavenge a register.
97 if (CFSize >= ((1 << 8) - 1) * 4 / 2) // Half of imm8 * 4
100 return !MF.getFrameInfo()->hasVarSizedObjects();
104 /// emitThumbRegPlusImmInReg - Emits a series of instructions to materialize
105 /// a destreg = basereg + immediate in Thumb code. Materialize the immediate
106 /// in a register using mov / mvn sequences or load the immediate from a
109 void emitThumbRegPlusImmInReg(MachineBasicBlock &MBB,
110 MachineBasicBlock::iterator &MBBI,
111 unsigned DestReg, unsigned BaseReg,
112 int NumBytes, bool CanChangeCC,
113 const TargetInstrInfo &TII,
114 const Thumb1RegisterInfo& MRI,
116 bool isHigh = !isARMLowRegister(DestReg) ||
117 (BaseReg != 0 && !isARMLowRegister(BaseReg));
119 // Subtract doesn't have high register version. Load the negative value
120 // if either base or dest register is a high register. Also, if do not
121 // issue sub as part of the sequence if condition register is to be
123 if (NumBytes < 0 && !isHigh && CanChangeCC) {
125 NumBytes = -NumBytes;
127 unsigned LdReg = DestReg;
128 if (DestReg == ARM::SP) {
129 assert(BaseReg == ARM::SP && "Unexpected!");
131 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVlor2hir), ARM::R12)
132 .addReg(ARM::R3, RegState::Kill);
135 if (NumBytes <= 255 && NumBytes >= 0)
136 AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), LdReg))
138 else if (NumBytes < 0 && NumBytes >= -255) {
139 AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), LdReg))
141 AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tRSB), LdReg))
142 .addReg(LdReg, RegState::Kill);
144 MRI.emitLoadConstPool(MBB, MBBI, dl, LdReg, 0, NumBytes);
147 int Opc = (isSub) ? ARM::tSUBrr : (isHigh ? ARM::tADDhirr : ARM::tADDrr);
148 MachineInstrBuilder MIB =
149 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg);
150 if (Opc != ARM::tADDhirr)
151 MIB = AddDefaultT1CC(MIB);
152 if (DestReg == ARM::SP || isSub)
153 MIB.addReg(BaseReg).addReg(LdReg, RegState::Kill);
155 MIB.addReg(LdReg).addReg(BaseReg, RegState::Kill);
158 if (DestReg == ARM::SP)
159 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVhir2lor), ARM::R3)
160 .addReg(ARM::R12, RegState::Kill);
163 /// calcNumMI - Returns the number of instructions required to materialize
164 /// the specific add / sub r, c instruction.
165 static unsigned calcNumMI(int Opc, int ExtraOpc, unsigned Bytes,
166 unsigned NumBits, unsigned Scale) {
168 unsigned Chunk = ((1 << NumBits) - 1) * Scale;
170 if (Opc == ARM::tADDrSPi) {
171 unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes;
175 Scale = 1; // Followed by a number of tADDi8.
176 Chunk = ((1 << NumBits) - 1) * Scale;
179 NumMIs += Bytes / Chunk;
180 if ((Bytes % Chunk) != 0)
187 /// emitThumbRegPlusImmediate - Emits a series of instructions to materialize
188 /// a destreg = basereg + immediate in Thumb code.
190 void emitThumbRegPlusImmediate(MachineBasicBlock &MBB,
191 MachineBasicBlock::iterator &MBBI,
192 unsigned DestReg, unsigned BaseReg,
193 int NumBytes, const TargetInstrInfo &TII,
194 const Thumb1RegisterInfo& MRI,
196 bool isSub = NumBytes < 0;
197 unsigned Bytes = (unsigned)NumBytes;
198 if (isSub) Bytes = -NumBytes;
199 bool isMul4 = (Bytes & 3) == 0;
200 bool isTwoAddr = false;
201 bool DstNotEqBase = false;
202 unsigned NumBits = 1;
207 bool NeedPred = false;
209 if (DestReg == BaseReg && BaseReg == ARM::SP) {
210 assert(isMul4 && "Thumb sp inc / dec size must be multiple of 4!");
213 Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
215 } else if (!isSub && BaseReg == ARM::SP) {
218 // r1 = add sp, 100 * 4
222 ExtraOpc = ARM::tADDi3;
231 if (DestReg != BaseReg)
234 if (DestReg == ARM::SP) {
235 Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
236 assert(isMul4 && "Thumb sp inc / dec size must be multiple of 4!");
240 Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8;
242 NeedPred = NeedCC = true;
247 unsigned NumMIs = calcNumMI(Opc, ExtraOpc, Bytes, NumBits, Scale);
248 unsigned Threshold = (DestReg == ARM::SP) ? 3 : 2;
249 if (NumMIs > Threshold) {
250 // This will expand into too many instructions. Load the immediate from a
252 emitThumbRegPlusImmInReg(MBB, MBBI, DestReg, BaseReg, NumBytes, true, TII,
258 if (isARMLowRegister(DestReg) && isARMLowRegister(BaseReg)) {
259 // If both are low registers, emit DestReg = add BaseReg, max(Imm, 7)
260 unsigned Chunk = (1 << 3) - 1;
261 unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes;
263 const TargetInstrDesc &TID = TII.get(isSub ? ARM::tSUBi3 : ARM::tADDi3);
264 const MachineInstrBuilder MIB =
265 AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TID, DestReg));
266 AddDefaultPred(MIB.addReg(BaseReg, RegState::Kill).addImm(ThisVal));
268 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), DestReg)
269 .addReg(BaseReg, RegState::Kill);
274 unsigned Chunk = ((1 << NumBits) - 1) * Scale;
276 unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes;
279 // Build the new tADD / tSUB.
281 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg);
283 MIB = AddDefaultT1CC(MIB);
284 MIB .addReg(DestReg).addImm(ThisVal);
286 MIB = AddDefaultPred(MIB);
289 bool isKill = BaseReg != ARM::SP;
290 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg);
292 MIB = AddDefaultT1CC(MIB);
293 MIB.addReg(BaseReg, getKillRegState(isKill)).addImm(ThisVal);
295 MIB = AddDefaultPred(MIB);
298 if (Opc == ARM::tADDrSPi) {
304 Chunk = ((1 << NumBits) - 1) * Scale;
305 Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8;
306 NeedPred = NeedCC = isTwoAddr = true;
312 const TargetInstrDesc &TID = TII.get(ExtraOpc);
313 AddDefaultPred(AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TID, DestReg))
314 .addReg(DestReg, RegState::Kill)
315 .addImm(((unsigned)NumBytes) & 3));
319 static void emitSPUpdate(MachineBasicBlock &MBB,
320 MachineBasicBlock::iterator &MBBI,
321 const TargetInstrInfo &TII, DebugLoc dl,
322 const Thumb1RegisterInfo &MRI,
324 emitThumbRegPlusImmediate(MBB, MBBI, ARM::SP, ARM::SP, NumBytes, TII,
328 void Thumb1RegisterInfo::
329 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
330 MachineBasicBlock::iterator I) const {
331 if (!hasReservedCallFrame(MF)) {
332 // If we have alloca, convert as follows:
333 // ADJCALLSTACKDOWN -> sub, sp, sp, amount
334 // ADJCALLSTACKUP -> add, sp, sp, amount
335 MachineInstr *Old = I;
336 DebugLoc dl = Old->getDebugLoc();
337 unsigned Amount = Old->getOperand(0).getImm();
339 // We need to keep the stack aligned properly. To do this, we round the
340 // amount of space needed for the outgoing arguments up to the next
341 // alignment boundary.
342 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
343 Amount = (Amount+Align-1)/Align*Align;
345 // Replace the pseudo instruction with a new instruction...
346 unsigned Opc = Old->getOpcode();
347 if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
348 emitSPUpdate(MBB, I, TII, dl, *this, -Amount);
350 assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
351 emitSPUpdate(MBB, I, TII, dl, *this, Amount);
358 /// emitThumbConstant - Emit a series of instructions to materialize a
360 static void emitThumbConstant(MachineBasicBlock &MBB,
361 MachineBasicBlock::iterator &MBBI,
362 unsigned DestReg, int Imm,
363 const TargetInstrInfo &TII,
364 const Thumb1RegisterInfo& MRI,
366 bool isSub = Imm < 0;
367 if (isSub) Imm = -Imm;
369 int Chunk = (1 << 8) - 1;
370 int ThisVal = (Imm > Chunk) ? Chunk : Imm;
372 AddDefaultPred(AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8),
376 emitThumbRegPlusImmediate(MBB, MBBI, DestReg, DestReg, Imm, TII, MRI, dl);
378 const TargetInstrDesc &TID = TII.get(ARM::tRSB);
379 AddDefaultPred(AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TID, DestReg))
380 .addReg(DestReg, RegState::Kill));
384 static void removeOperands(MachineInstr &MI, unsigned i) {
386 for (unsigned e = MI.getNumOperands(); i != e; ++i)
387 MI.RemoveOperand(Op);
390 int Thumb1RegisterInfo::
391 rewriteFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
392 unsigned FrameReg, int Offset) const
394 // if/when eliminateFrameIndex() conforms with ARMBaseRegisterInfo
395 // version then can pull out Thumb1 specific parts here
399 void Thumb1RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
400 int SPAdj, RegScavenger *RS) const{
402 MachineInstr &MI = *II;
403 MachineBasicBlock &MBB = *MI.getParent();
404 MachineFunction &MF = *MBB.getParent();
405 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
406 DebugLoc dl = MI.getDebugLoc();
408 while (!MI.getOperand(i).isFI()) {
410 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
413 unsigned FrameReg = ARM::SP;
414 int FrameIndex = MI.getOperand(i).getIndex();
415 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
416 MF.getFrameInfo()->getStackSize() + SPAdj;
418 if (AFI->isGPRCalleeSavedArea1Frame(FrameIndex))
419 Offset -= AFI->getGPRCalleeSavedArea1Offset();
420 else if (AFI->isGPRCalleeSavedArea2Frame(FrameIndex))
421 Offset -= AFI->getGPRCalleeSavedArea2Offset();
422 else if (hasFP(MF)) {
423 assert(SPAdj == 0 && "Unexpected");
424 // There is alloca()'s in this function, must reference off the frame
426 FrameReg = getFrameRegister(MF);
427 Offset -= AFI->getFramePtrSpillOffset();
430 unsigned Opcode = MI.getOpcode();
431 const TargetInstrDesc &Desc = MI.getDesc();
432 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
434 if (Opcode == ARM::tADDrSPi) {
435 Offset += MI.getOperand(i+1).getImm();
437 // Can't use tADDrSPi if it's based off the frame pointer.
438 unsigned NumBits = 0;
440 if (FrameReg != ARM::SP) {
441 Opcode = ARM::tADDi3;
442 MI.setDesc(TII.get(Opcode));
447 assert((Offset & 3) == 0 &&
448 "Thumb add/sub sp, #imm immediate must be multiple of 4!");
452 // Turn it into a move.
453 MI.setDesc(TII.get(ARM::tMOVhir2lor));
454 MI.getOperand(i).ChangeToRegister(FrameReg, false);
455 MI.RemoveOperand(i+1);
459 // Common case: small offset, fits into instruction.
460 unsigned Mask = (1 << NumBits) - 1;
461 if (((Offset / Scale) & ~Mask) == 0) {
462 // Replace the FrameIndex with sp / fp
463 if (Opcode == ARM::tADDi3) {
464 removeOperands(MI, i);
465 MachineInstrBuilder MIB(&MI);
466 AddDefaultPred(AddDefaultT1CC(MIB).addReg(FrameReg)
467 .addImm(Offset / Scale));
469 MI.getOperand(i).ChangeToRegister(FrameReg, false);
470 MI.getOperand(i+1).ChangeToImmediate(Offset / Scale);
475 unsigned DestReg = MI.getOperand(0).getReg();
476 unsigned Bytes = (Offset > 0) ? Offset : -Offset;
477 unsigned NumMIs = calcNumMI(Opcode, 0, Bytes, NumBits, Scale);
478 // MI would expand into a large number of instructions. Don't try to
479 // simplify the immediate.
481 emitThumbRegPlusImmediate(MBB, II, DestReg, FrameReg, Offset, TII,
488 // Translate r0 = add sp, imm to
489 // r0 = add sp, 255*4
490 // r0 = add r0, (imm - 255*4)
491 if (Opcode == ARM::tADDi3) {
492 removeOperands(MI, i);
493 MachineInstrBuilder MIB(&MI);
494 AddDefaultPred(AddDefaultT1CC(MIB).addReg(FrameReg).addImm(Mask));
496 MI.getOperand(i).ChangeToRegister(FrameReg, false);
497 MI.getOperand(i+1).ChangeToImmediate(Mask);
499 Offset = (Offset - Mask * Scale);
500 MachineBasicBlock::iterator NII = next(II);
501 emitThumbRegPlusImmediate(MBB, NII, DestReg, DestReg, Offset, TII,
504 // Translate r0 = add sp, -imm to
505 // r0 = -imm (this is then translated into a series of instructons)
507 emitThumbConstant(MBB, II, DestReg, Offset, TII, *this, dl);
508 MI.setDesc(TII.get(ARM::tADDhirr));
509 MI.getOperand(i).ChangeToRegister(DestReg, false, false, true);
510 MI.getOperand(i+1).ChangeToRegister(FrameReg, false);
516 unsigned NumBits = 0;
519 case ARMII::AddrModeT1_s: {
521 InstrOffs = MI.getOperand(ImmIdx).getImm();
522 NumBits = (FrameReg == ARM::SP) ? 8 : 5;
527 llvm_unreachable("Unsupported addressing mode!");
531 Offset += InstrOffs * Scale;
532 assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
534 // Common case: small offset, fits into instruction.
535 MachineOperand &ImmOp = MI.getOperand(ImmIdx);
536 int ImmedOffset = Offset / Scale;
537 unsigned Mask = (1 << NumBits) - 1;
538 if ((unsigned)Offset <= Mask * Scale) {
539 // Replace the FrameIndex with sp
540 MI.getOperand(i).ChangeToRegister(FrameReg, false);
541 ImmOp.ChangeToImmediate(ImmedOffset);
545 bool isThumSpillRestore = Opcode == ARM::tRestore || Opcode == ARM::tSpill;
546 if (AddrMode == ARMII::AddrModeT1_s) {
547 // Thumb tLDRspi, tSTRspi. These will change to instructions that use
548 // a different base register.
550 Mask = (1 << NumBits) - 1;
552 // If this is a thumb spill / restore, we will be using a constpool load to
553 // materialize the offset.
554 if (AddrMode == ARMII::AddrModeT1_s && isThumSpillRestore)
555 ImmOp.ChangeToImmediate(0);
557 // Otherwise, it didn't fit. Pull in what we can to simplify the immed.
558 ImmedOffset = ImmedOffset & Mask;
559 ImmOp.ChangeToImmediate(ImmedOffset);
560 Offset &= ~(Mask*Scale);
564 // If we get here, the immediate doesn't fit into the instruction. We folded
565 // as much as possible above, handle the rest, providing a register that is
567 assert(Offset && "This code isn't needed if offset already handled!");
569 // Remove predicate first.
570 int PIdx = MI.findFirstPredOperandIdx();
572 removeOperands(MI, PIdx);
574 if (Desc.mayLoad()) {
575 // Use the destination register to materialize sp + offset.
576 unsigned TmpReg = MI.getOperand(0).getReg();
578 if (Opcode == ARM::tRestore) {
579 if (FrameReg == ARM::SP)
580 emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,
581 Offset, false, TII, *this, dl);
583 emitLoadConstPool(MBB, II, dl, TmpReg, 0, Offset);
587 emitThumbRegPlusImmediate(MBB, II, TmpReg, FrameReg, Offset, TII,
591 MI.setDesc(TII.get(ARM::tLDR));
592 MI.getOperand(i).ChangeToRegister(TmpReg, false, false, true);
594 // Use [reg, reg] addrmode.
595 MI.addOperand(MachineOperand::CreateReg(FrameReg, false));
596 else // tLDR has an extra register operand.
597 MI.addOperand(MachineOperand::CreateReg(0, false));
598 } else if (Desc.mayStore()) {
599 // FIXME! This is horrific!!! We need register scavenging.
600 // Our temporary workaround has marked r3 unavailable. Of course, r3 is
601 // also a ABI register so it's possible that is is the register that is
602 // being storing here. If that's the case, we do the following:
604 // Use r2 to materialize sp + offset
607 unsigned ValReg = MI.getOperand(0).getReg();
608 unsigned TmpReg = ARM::R3;
610 if (ValReg == ARM::R3) {
611 BuildMI(MBB, II, dl, TII.get(ARM::tMOVlor2hir), ARM::R12)
612 .addReg(ARM::R2, RegState::Kill);
615 if (TmpReg == ARM::R3 && AFI->isR3LiveIn())
616 BuildMI(MBB, II, dl, TII.get(ARM::tMOVlor2hir), ARM::R12)
617 .addReg(ARM::R3, RegState::Kill);
618 if (Opcode == ARM::tSpill) {
619 if (FrameReg == ARM::SP)
620 emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,
621 Offset, false, TII, *this, dl);
623 emitLoadConstPool(MBB, II, dl, TmpReg, 0, Offset);
627 emitThumbRegPlusImmediate(MBB, II, TmpReg, FrameReg, Offset, TII,
629 MI.setDesc(TII.get(ARM::tSTR));
630 MI.getOperand(i).ChangeToRegister(TmpReg, false, false, true);
631 if (UseRR) // Use [reg, reg] addrmode.
632 MI.addOperand(MachineOperand::CreateReg(FrameReg, false));
633 else // tSTR has an extra register operand.
634 MI.addOperand(MachineOperand::CreateReg(0, false));
636 MachineBasicBlock::iterator NII = next(II);
637 if (ValReg == ARM::R3)
638 BuildMI(MBB, NII, dl, TII.get(ARM::tMOVhir2lor), ARM::R2)
639 .addReg(ARM::R12, RegState::Kill);
640 if (TmpReg == ARM::R3 && AFI->isR3LiveIn())
641 BuildMI(MBB, NII, dl, TII.get(ARM::tMOVhir2lor), ARM::R3)
642 .addReg(ARM::R12, RegState::Kill);
644 assert(false && "Unexpected opcode!");
646 // Add predicate back if it's needed.
647 if (MI.getDesc().isPredicable()) {
648 MachineInstrBuilder MIB(&MI);
653 void Thumb1RegisterInfo::emitPrologue(MachineFunction &MF) const {
654 MachineBasicBlock &MBB = MF.front();
655 MachineBasicBlock::iterator MBBI = MBB.begin();
656 MachineFrameInfo *MFI = MF.getFrameInfo();
657 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
658 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
659 unsigned NumBytes = MFI->getStackSize();
660 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
661 DebugLoc dl = (MBBI != MBB.end() ?
662 MBBI->getDebugLoc() : DebugLoc::getUnknownLoc());
664 // Check if R3 is live in. It might have to be used as a scratch register.
665 for (MachineRegisterInfo::livein_iterator I =MF.getRegInfo().livein_begin(),
666 E = MF.getRegInfo().livein_end(); I != E; ++I) {
667 if (I->first == ARM::R3) {
668 AFI->setR3IsLiveIn(true);
673 // Thumb add/sub sp, imm8 instructions implicitly multiply the offset by 4.
674 NumBytes = (NumBytes + 3) & ~3;
675 MFI->setStackSize(NumBytes);
677 // Determine the sizes of each callee-save spill areas and record which frame
678 // belongs to which callee-save spill areas.
679 unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
680 int FramePtrSpillFI = 0;
683 emitSPUpdate(MBB, MBBI, TII, dl, *this, -VARegSaveSize);
685 if (!AFI->hasStackFrame()) {
687 emitSPUpdate(MBB, MBBI, TII, dl, *this, -NumBytes);
691 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
692 unsigned Reg = CSI[i].getReg();
693 int FI = CSI[i].getFrameIdx();
701 FramePtrSpillFI = FI;
702 AFI->addGPRCalleeSavedArea1Frame(FI);
710 FramePtrSpillFI = FI;
711 if (STI.isTargetDarwin()) {
712 AFI->addGPRCalleeSavedArea2Frame(FI);
715 AFI->addGPRCalleeSavedArea1Frame(FI);
720 AFI->addDPRCalleeSavedAreaFrame(FI);
725 if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPUSH) {
727 if (MBBI != MBB.end())
728 dl = MBBI->getDebugLoc();
731 // Darwin ABI requires FP to point to the stack slot that contains the
733 if (STI.isTargetDarwin() || hasFP(MF)) {
734 MachineInstrBuilder MIB =
735 BuildMI(MBB, MBBI, dl, TII.get(ARM::tADDrSPi), FramePtr)
736 .addFrameIndex(FramePtrSpillFI).addImm(0);
739 // Determine starting offsets of spill areas.
740 unsigned DPRCSOffset = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize);
741 unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize;
742 unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size;
743 AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) + NumBytes);
744 AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
745 AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
746 AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
748 NumBytes = DPRCSOffset;
750 // Insert it after all the callee-save spills.
751 emitSPUpdate(MBB, MBBI, TII, dl, *this, -NumBytes);
754 if (STI.isTargetELF() && hasFP(MF)) {
755 MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() -
756 AFI->getFramePtrSpillOffset());
759 AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
760 AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
761 AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
764 static bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) {
765 for (unsigned i = 0; CSRegs[i]; ++i)
766 if (Reg == CSRegs[i])
771 static bool isCSRestore(MachineInstr *MI, const unsigned *CSRegs) {
772 return (MI->getOpcode() == ARM::tRestore &&
773 MI->getOperand(1).isFI() &&
774 isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs));
777 void Thumb1RegisterInfo::emitEpilogue(MachineFunction &MF,
778 MachineBasicBlock &MBB) const {
779 MachineBasicBlock::iterator MBBI = prior(MBB.end());
780 assert((MBBI->getOpcode() == ARM::tBX_RET ||
781 MBBI->getOpcode() == ARM::tPOP_RET) &&
782 "Can only insert epilog into returning blocks");
783 DebugLoc dl = MBBI->getDebugLoc();
784 MachineFrameInfo *MFI = MF.getFrameInfo();
785 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
786 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
787 int NumBytes = (int)MFI->getStackSize();
789 if (!AFI->hasStackFrame()) {
791 emitSPUpdate(MBB, MBBI, TII, dl, *this, NumBytes);
793 // Unwind MBBI to point to first LDR / FLDD.
794 const unsigned *CSRegs = getCalleeSavedRegs();
795 if (MBBI != MBB.begin()) {
798 while (MBBI != MBB.begin() && isCSRestore(MBBI, CSRegs));
799 if (!isCSRestore(MBBI, CSRegs))
803 // Move SP to start of FP callee save spill area.
804 NumBytes -= (AFI->getGPRCalleeSavedArea1Size() +
805 AFI->getGPRCalleeSavedArea2Size() +
806 AFI->getDPRCalleeSavedAreaSize());
809 NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
810 // Reset SP based on frame pointer only if the stack frame extends beyond
811 // frame pointer stack slot or target is ELF and the function has FP.
813 emitThumbRegPlusImmediate(MBB, MBBI, ARM::SP, FramePtr, -NumBytes,
816 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVlor2hir), ARM::SP)
819 if (MBBI->getOpcode() == ARM::tBX_RET &&
820 &MBB.front() != MBBI &&
821 prior(MBBI)->getOpcode() == ARM::tPOP) {
822 MachineBasicBlock::iterator PMBBI = prior(MBBI);
823 emitSPUpdate(MBB, PMBBI, TII, dl, *this, NumBytes);
825 emitSPUpdate(MBB, MBBI, TII, dl, *this, NumBytes);
830 // Epilogue for vararg functions: pop LR to R3 and branch off it.
831 // FIXME: Verify this is still ok when R3 is no longer being reserved.
832 BuildMI(MBB, MBBI, dl, TII.get(ARM::tPOP)).addReg(ARM::R3);
834 emitSPUpdate(MBB, MBBI, TII, dl, *this, VARegSaveSize);
836 BuildMI(MBB, MBBI, dl, TII.get(ARM::tBX_RET_vararg)).addReg(ARM::R3);