1 //===- Thumb1RegisterInfo.cpp - Thumb-1 Register Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Thumb-1 implementation of the TargetRegisterInfo class.
12 //===----------------------------------------------------------------------===//
15 #include "ARMAddressingModes.h"
16 #include "ARMBaseInstrInfo.h"
17 #include "ARMMachineFunctionInfo.h"
18 #include "ARMSubtarget.h"
19 #include "Thumb1InstrInfo.h"
20 #include "Thumb1RegisterInfo.h"
21 #include "llvm/Constants.h"
22 #include "llvm/DerivedTypes.h"
23 #include "llvm/Function.h"
24 #include "llvm/LLVMContext.h"
25 #include "llvm/CodeGen/MachineConstantPool.h"
26 #include "llvm/CodeGen/MachineFrameInfo.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineInstrBuilder.h"
29 #include "llvm/CodeGen/MachineLocation.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/Target/TargetFrameInfo.h"
32 #include "llvm/Target/TargetMachine.h"
33 #include "llvm/ADT/BitVector.h"
34 #include "llvm/ADT/SmallVector.h"
35 #include "llvm/Support/ErrorHandling.h"
36 #include "llvm/Support/raw_ostream.h"
39 Thumb1RegisterInfo::Thumb1RegisterInfo(const ARMBaseInstrInfo &tii,
40 const ARMSubtarget &sti)
41 : ARMBaseRegisterInfo(tii, sti) {
44 /// emitLoadConstPool - Emits a load from constpool to materialize the
45 /// specified immediate.
46 void Thumb1RegisterInfo::emitLoadConstPool(MachineBasicBlock &MBB,
47 MachineBasicBlock::iterator &MBBI,
49 unsigned DestReg, unsigned SubIdx,
51 ARMCC::CondCodes Pred,
52 unsigned PredReg) const {
53 MachineFunction &MF = *MBB.getParent();
54 MachineConstantPool *ConstantPool = MF.getConstantPool();
55 Constant *C = ConstantInt::get(
56 Type::getInt32Ty(MBB.getParent()->getFunction()->getContext()), Val);
57 unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
59 BuildMI(MBB, MBBI, dl, TII.get(ARM::tLDRcp))
60 .addReg(DestReg, getDefRegState(true), SubIdx)
61 .addConstantPoolIndex(Idx).addImm(Pred).addReg(PredReg);
64 const TargetRegisterClass*
65 Thumb1RegisterInfo::getPhysicalRegisterRegClass(unsigned Reg, EVT VT) const {
66 if (isARMLowRegister(Reg))
67 return ARM::tGPRRegisterClass;
71 case ARM::R8: case ARM::R9: case ARM::R10: case ARM::R11:
72 case ARM::R12: case ARM::SP: case ARM::LR: case ARM::PC:
73 return ARM::GPRRegisterClass;
76 return TargetRegisterInfo::getPhysicalRegisterRegClass(Reg, VT);
80 Thumb1RegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const {
85 Thumb1RegisterInfo::requiresFrameIndexScavenging(const MachineFunction &MF)
91 bool Thumb1RegisterInfo::hasReservedCallFrame(MachineFunction &MF) const {
92 const MachineFrameInfo *FFI = MF.getFrameInfo();
93 unsigned CFSize = FFI->getMaxCallFrameSize();
94 // It's not always a good idea to include the call frame as part of the
95 // stack frame. ARM (especially Thumb) has small immediate offset to
96 // address the stack frame. So a large call frame can cause poor codegen
97 // and may even makes it impossible to scavenge a register.
98 if (CFSize >= ((1 << 8) - 1) * 4 / 2) // Half of imm8 * 4
101 return !MF.getFrameInfo()->hasVarSizedObjects();
105 /// emitThumbRegPlusImmInReg - Emits a series of instructions to materialize
106 /// a destreg = basereg + immediate in Thumb code. Materialize the immediate
107 /// in a register using mov / mvn sequences or load the immediate from a
110 void emitThumbRegPlusImmInReg(MachineBasicBlock &MBB,
111 MachineBasicBlock::iterator &MBBI,
112 unsigned DestReg, unsigned BaseReg,
113 int NumBytes, bool CanChangeCC,
114 const TargetInstrInfo &TII,
115 const Thumb1RegisterInfo& MRI,
117 MachineFunction &MF = *MBB.getParent();
118 bool isHigh = !isARMLowRegister(DestReg) ||
119 (BaseReg != 0 && !isARMLowRegister(BaseReg));
121 // Subtract doesn't have high register version. Load the negative value
122 // if either base or dest register is a high register. Also, if do not
123 // issue sub as part of the sequence if condition register is to be
125 if (NumBytes < 0 && !isHigh && CanChangeCC) {
127 NumBytes = -NumBytes;
129 unsigned LdReg = DestReg;
130 if (DestReg == ARM::SP) {
131 assert(BaseReg == ARM::SP && "Unexpected!");
132 LdReg = MF.getRegInfo().createVirtualRegister(ARM::tGPRRegisterClass);
135 if (NumBytes <= 255 && NumBytes >= 0)
136 AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), LdReg))
138 else if (NumBytes < 0 && NumBytes >= -255) {
139 AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), LdReg))
141 AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tRSB), LdReg))
142 .addReg(LdReg, RegState::Kill);
144 MRI.emitLoadConstPool(MBB, MBBI, dl, LdReg, 0, NumBytes);
147 int Opc = (isSub) ? ARM::tSUBrr : (isHigh ? ARM::tADDhirr : ARM::tADDrr);
148 MachineInstrBuilder MIB =
149 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg);
150 if (Opc != ARM::tADDhirr)
151 MIB = AddDefaultT1CC(MIB);
152 if (DestReg == ARM::SP || isSub)
153 MIB.addReg(BaseReg).addReg(LdReg, RegState::Kill);
155 MIB.addReg(LdReg).addReg(BaseReg, RegState::Kill);
159 /// calcNumMI - Returns the number of instructions required to materialize
160 /// the specific add / sub r, c instruction.
161 static unsigned calcNumMI(int Opc, int ExtraOpc, unsigned Bytes,
162 unsigned NumBits, unsigned Scale) {
164 unsigned Chunk = ((1 << NumBits) - 1) * Scale;
166 if (Opc == ARM::tADDrSPi) {
167 unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes;
171 Scale = 1; // Followed by a number of tADDi8.
172 Chunk = ((1 << NumBits) - 1) * Scale;
175 NumMIs += Bytes / Chunk;
176 if ((Bytes % Chunk) != 0)
183 /// emitThumbRegPlusImmediate - Emits a series of instructions to materialize
184 /// a destreg = basereg + immediate in Thumb code.
186 void emitThumbRegPlusImmediate(MachineBasicBlock &MBB,
187 MachineBasicBlock::iterator &MBBI,
188 unsigned DestReg, unsigned BaseReg,
189 int NumBytes, const TargetInstrInfo &TII,
190 const Thumb1RegisterInfo& MRI,
192 bool isSub = NumBytes < 0;
193 unsigned Bytes = (unsigned)NumBytes;
194 if (isSub) Bytes = -NumBytes;
195 bool isMul4 = (Bytes & 3) == 0;
196 bool isTwoAddr = false;
197 bool DstNotEqBase = false;
198 unsigned NumBits = 1;
203 bool NeedPred = false;
205 if (DestReg == BaseReg && BaseReg == ARM::SP) {
206 assert(isMul4 && "Thumb sp inc / dec size must be multiple of 4!");
209 Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
211 } else if (!isSub && BaseReg == ARM::SP) {
214 // r1 = add sp, 100 * 4
218 ExtraOpc = ARM::tADDi3;
227 if (DestReg != BaseReg)
230 if (DestReg == ARM::SP) {
231 Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
232 assert(isMul4 && "Thumb sp inc / dec size must be multiple of 4!");
236 Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8;
238 NeedPred = NeedCC = true;
243 unsigned NumMIs = calcNumMI(Opc, ExtraOpc, Bytes, NumBits, Scale);
244 unsigned Threshold = (DestReg == ARM::SP) ? 3 : 2;
245 if (NumMIs > Threshold) {
246 // This will expand into too many instructions. Load the immediate from a
248 emitThumbRegPlusImmInReg(MBB, MBBI, DestReg, BaseReg, NumBytes, true, TII,
254 if (isARMLowRegister(DestReg) && isARMLowRegister(BaseReg)) {
255 // If both are low registers, emit DestReg = add BaseReg, max(Imm, 7)
256 unsigned Chunk = (1 << 3) - 1;
257 unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes;
259 const TargetInstrDesc &TID = TII.get(isSub ? ARM::tSUBi3 : ARM::tADDi3);
260 const MachineInstrBuilder MIB =
261 AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TID, DestReg));
262 AddDefaultPred(MIB.addReg(BaseReg, RegState::Kill).addImm(ThisVal));
264 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), DestReg)
265 .addReg(BaseReg, RegState::Kill);
270 unsigned Chunk = ((1 << NumBits) - 1) * Scale;
272 unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes;
275 // Build the new tADD / tSUB.
277 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg);
279 MIB = AddDefaultT1CC(MIB);
280 MIB .addReg(DestReg).addImm(ThisVal);
282 MIB = AddDefaultPred(MIB);
285 bool isKill = BaseReg != ARM::SP;
286 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg);
288 MIB = AddDefaultT1CC(MIB);
289 MIB.addReg(BaseReg, getKillRegState(isKill)).addImm(ThisVal);
291 MIB = AddDefaultPred(MIB);
294 if (Opc == ARM::tADDrSPi) {
300 Chunk = ((1 << NumBits) - 1) * Scale;
301 Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8;
302 NeedPred = NeedCC = isTwoAddr = true;
308 const TargetInstrDesc &TID = TII.get(ExtraOpc);
309 AddDefaultPred(AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TID, DestReg))
310 .addReg(DestReg, RegState::Kill)
311 .addImm(((unsigned)NumBytes) & 3));
315 static void emitSPUpdate(MachineBasicBlock &MBB,
316 MachineBasicBlock::iterator &MBBI,
317 const TargetInstrInfo &TII, DebugLoc dl,
318 const Thumb1RegisterInfo &MRI,
320 emitThumbRegPlusImmediate(MBB, MBBI, ARM::SP, ARM::SP, NumBytes, TII,
324 void Thumb1RegisterInfo::
325 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
326 MachineBasicBlock::iterator I) const {
327 if (!hasReservedCallFrame(MF)) {
328 // If we have alloca, convert as follows:
329 // ADJCALLSTACKDOWN -> sub, sp, sp, amount
330 // ADJCALLSTACKUP -> add, sp, sp, amount
331 MachineInstr *Old = I;
332 DebugLoc dl = Old->getDebugLoc();
333 unsigned Amount = Old->getOperand(0).getImm();
335 // We need to keep the stack aligned properly. To do this, we round the
336 // amount of space needed for the outgoing arguments up to the next
337 // alignment boundary.
338 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
339 Amount = (Amount+Align-1)/Align*Align;
341 // Replace the pseudo instruction with a new instruction...
342 unsigned Opc = Old->getOpcode();
343 if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
344 emitSPUpdate(MBB, I, TII, dl, *this, -Amount);
346 assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
347 emitSPUpdate(MBB, I, TII, dl, *this, Amount);
354 /// emitThumbConstant - Emit a series of instructions to materialize a
356 static void emitThumbConstant(MachineBasicBlock &MBB,
357 MachineBasicBlock::iterator &MBBI,
358 unsigned DestReg, int Imm,
359 const TargetInstrInfo &TII,
360 const Thumb1RegisterInfo& MRI,
362 bool isSub = Imm < 0;
363 if (isSub) Imm = -Imm;
365 int Chunk = (1 << 8) - 1;
366 int ThisVal = (Imm > Chunk) ? Chunk : Imm;
368 AddDefaultPred(AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8),
372 emitThumbRegPlusImmediate(MBB, MBBI, DestReg, DestReg, Imm, TII, MRI, dl);
374 const TargetInstrDesc &TID = TII.get(ARM::tRSB);
375 AddDefaultPred(AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TID, DestReg))
376 .addReg(DestReg, RegState::Kill));
380 static void removeOperands(MachineInstr &MI, unsigned i) {
382 for (unsigned e = MI.getNumOperands(); i != e; ++i)
383 MI.RemoveOperand(Op);
386 int Thumb1RegisterInfo::
387 rewriteFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
388 unsigned FrameReg, int Offset,
389 unsigned MOVOpc, unsigned ADDriOpc, unsigned SUBriOpc) const
391 // if/when eliminateFrameIndex() conforms with ARMBaseRegisterInfo
392 // version then can pull out Thumb1 specific parts here
396 /// saveScavengerRegister - Spill the register so it can be used by the
397 /// register scavenger. Return true.
399 Thumb1RegisterInfo::saveScavengerRegister(MachineBasicBlock &MBB,
400 MachineBasicBlock::iterator I,
401 MachineBasicBlock::iterator &UseMI,
402 const TargetRegisterClass *RC,
403 unsigned Reg) const {
404 // Thumb1 can't use the emergency spill slot on the stack because
405 // ldr/str immediate offsets must be positive, and if we're referencing
406 // off the frame pointer (if, for example, there are alloca() calls in
407 // the function, the offset will be negative. Use R12 instead since that's
408 // a call clobbered register that we know won't be used in Thumb1 mode.
409 DebugLoc DL = DebugLoc::getUnknownLoc();
410 BuildMI(MBB, I, DL, TII.get(ARM::tMOVtgpr2gpr)).
411 addReg(ARM::R12, RegState::Define).addReg(Reg, RegState::Kill);
413 // The UseMI is where we would like to restore the register. If there's
414 // interference with R12 before then, however, we'll need to restore it
415 // before that instead and adjust the UseMI.
417 for (MachineBasicBlock::iterator II = I; !done && II != UseMI ; ++II) {
418 // If this instruction affects R12, adjust our restore point.
419 for (unsigned i = 0, e = II->getNumOperands(); i != e; ++i) {
420 const MachineOperand &MO = II->getOperand(i);
421 if (!MO.isReg() || MO.isUndef() || !MO.getReg() ||
422 TargetRegisterInfo::isVirtualRegister(MO.getReg()))
424 if (MO.getReg() == ARM::R12) {
431 // Restore the register from R12
432 BuildMI(MBB, UseMI, DL, TII.get(ARM::tMOVgpr2tgpr)).
433 addReg(Reg, RegState::Define).addReg(ARM::R12, RegState::Kill);
439 Thumb1RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
440 int SPAdj, int *Value,
441 RegScavenger *RS) const{
444 MachineInstr &MI = *II;
445 MachineBasicBlock &MBB = *MI.getParent();
446 MachineFunction &MF = *MBB.getParent();
447 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
448 DebugLoc dl = MI.getDebugLoc();
450 while (!MI.getOperand(i).isFI()) {
452 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
455 unsigned FrameReg = ARM::SP;
456 int FrameIndex = MI.getOperand(i).getIndex();
457 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
458 MF.getFrameInfo()->getStackSize() + SPAdj;
460 if (AFI->isGPRCalleeSavedArea1Frame(FrameIndex))
461 Offset -= AFI->getGPRCalleeSavedArea1Offset();
462 else if (AFI->isGPRCalleeSavedArea2Frame(FrameIndex))
463 Offset -= AFI->getGPRCalleeSavedArea2Offset();
464 else if (hasFP(MF)) {
465 assert(SPAdj == 0 && "Unexpected");
466 // There is alloca()'s in this function, must reference off the frame
468 FrameReg = getFrameRegister(MF);
469 Offset -= AFI->getFramePtrSpillOffset();
472 unsigned Opcode = MI.getOpcode();
473 const TargetInstrDesc &Desc = MI.getDesc();
474 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
476 if (Opcode == ARM::tADDrSPi) {
477 Offset += MI.getOperand(i+1).getImm();
479 // Can't use tADDrSPi if it's based off the frame pointer.
480 unsigned NumBits = 0;
482 if (FrameReg != ARM::SP) {
483 Opcode = ARM::tADDi3;
484 MI.setDesc(TII.get(Opcode));
489 assert((Offset & 3) == 0 &&
490 "Thumb add/sub sp, #imm immediate must be multiple of 4!");
494 // Turn it into a move.
495 MI.setDesc(TII.get(ARM::tMOVgpr2tgpr));
496 MI.getOperand(i).ChangeToRegister(FrameReg, false);
497 MI.RemoveOperand(i+1);
501 // Common case: small offset, fits into instruction.
502 unsigned Mask = (1 << NumBits) - 1;
503 if (((Offset / Scale) & ~Mask) == 0) {
504 // Replace the FrameIndex with sp / fp
505 if (Opcode == ARM::tADDi3) {
506 removeOperands(MI, i);
507 MachineInstrBuilder MIB(&MI);
508 AddDefaultPred(AddDefaultT1CC(MIB).addReg(FrameReg)
509 .addImm(Offset / Scale));
511 MI.getOperand(i).ChangeToRegister(FrameReg, false);
512 MI.getOperand(i+1).ChangeToImmediate(Offset / Scale);
517 unsigned DestReg = MI.getOperand(0).getReg();
518 unsigned Bytes = (Offset > 0) ? Offset : -Offset;
519 unsigned NumMIs = calcNumMI(Opcode, 0, Bytes, NumBits, Scale);
520 // MI would expand into a large number of instructions. Don't try to
521 // simplify the immediate.
523 emitThumbRegPlusImmediate(MBB, II, DestReg, FrameReg, Offset, TII,
530 // Translate r0 = add sp, imm to
531 // r0 = add sp, 255*4
532 // r0 = add r0, (imm - 255*4)
533 if (Opcode == ARM::tADDi3) {
534 removeOperands(MI, i);
535 MachineInstrBuilder MIB(&MI);
536 AddDefaultPred(AddDefaultT1CC(MIB).addReg(FrameReg).addImm(Mask));
538 MI.getOperand(i).ChangeToRegister(FrameReg, false);
539 MI.getOperand(i+1).ChangeToImmediate(Mask);
541 Offset = (Offset - Mask * Scale);
542 MachineBasicBlock::iterator NII = next(II);
543 emitThumbRegPlusImmediate(MBB, NII, DestReg, DestReg, Offset, TII,
546 // Translate r0 = add sp, -imm to
547 // r0 = -imm (this is then translated into a series of instructons)
549 emitThumbConstant(MBB, II, DestReg, Offset, TII, *this, dl);
551 MI.setDesc(TII.get(ARM::tADDhirr));
552 MI.getOperand(i).ChangeToRegister(DestReg, false, false, true);
553 MI.getOperand(i+1).ChangeToRegister(FrameReg, false);
554 if (Opcode == ARM::tADDi3) {
555 MachineInstrBuilder MIB(&MI);
563 unsigned NumBits = 0;
566 case ARMII::AddrModeT1_s: {
568 InstrOffs = MI.getOperand(ImmIdx).getImm();
569 NumBits = (FrameReg == ARM::SP) ? 8 : 5;
574 llvm_unreachable("Unsupported addressing mode!");
578 Offset += InstrOffs * Scale;
579 assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
581 // Common case: small offset, fits into instruction.
582 MachineOperand &ImmOp = MI.getOperand(ImmIdx);
583 int ImmedOffset = Offset / Scale;
584 unsigned Mask = (1 << NumBits) - 1;
585 if ((unsigned)Offset <= Mask * Scale) {
586 // Replace the FrameIndex with sp
587 MI.getOperand(i).ChangeToRegister(FrameReg, false);
588 ImmOp.ChangeToImmediate(ImmedOffset);
592 bool isThumSpillRestore = Opcode == ARM::tRestore || Opcode == ARM::tSpill;
593 if (AddrMode == ARMII::AddrModeT1_s) {
594 // Thumb tLDRspi, tSTRspi. These will change to instructions that use
595 // a different base register.
597 Mask = (1 << NumBits) - 1;
599 // If this is a thumb spill / restore, we will be using a constpool load to
600 // materialize the offset.
601 if (AddrMode == ARMII::AddrModeT1_s && isThumSpillRestore)
602 ImmOp.ChangeToImmediate(0);
604 // Otherwise, it didn't fit. Pull in what we can to simplify the immed.
605 ImmedOffset = ImmedOffset & Mask;
606 ImmOp.ChangeToImmediate(ImmedOffset);
607 Offset &= ~(Mask*Scale);
611 // If we get here, the immediate doesn't fit into the instruction. We folded
612 // as much as possible above, handle the rest, providing a register that is
614 assert(Offset && "This code isn't needed if offset already handled!");
616 // Remove predicate first.
617 int PIdx = MI.findFirstPredOperandIdx();
619 removeOperands(MI, PIdx);
621 if (Desc.mayLoad()) {
622 // Use the destination register to materialize sp + offset.
623 unsigned TmpReg = MI.getOperand(0).getReg();
625 if (Opcode == ARM::tRestore) {
626 if (FrameReg == ARM::SP)
627 emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,
628 Offset, false, TII, *this, dl);
630 emitLoadConstPool(MBB, II, dl, TmpReg, 0, Offset);
634 emitThumbRegPlusImmediate(MBB, II, TmpReg, FrameReg, Offset, TII,
638 MI.setDesc(TII.get(ARM::tLDR));
639 MI.getOperand(i).ChangeToRegister(TmpReg, false, false, true);
641 // Use [reg, reg] addrmode.
642 MI.addOperand(MachineOperand::CreateReg(FrameReg, false));
643 else // tLDR has an extra register operand.
644 MI.addOperand(MachineOperand::CreateReg(0, false));
645 } else if (Desc.mayStore()) {
646 VReg = MF.getRegInfo().createVirtualRegister(ARM::tGPRRegisterClass);
647 assert (Value && "Frame index virtual allocated, but Value arg is NULL!");
651 if (Opcode == ARM::tSpill) {
652 if (FrameReg == ARM::SP)
653 emitThumbRegPlusImmInReg(MBB, II, VReg, FrameReg,
654 Offset, false, TII, *this, dl);
656 emitLoadConstPool(MBB, II, dl, VReg, 0, Offset);
660 emitThumbRegPlusImmediate(MBB, II, VReg, FrameReg, Offset, TII,
662 MI.setDesc(TII.get(ARM::tSTR));
663 MI.getOperand(i).ChangeToRegister(VReg, false, false, true);
664 if (UseRR) // Use [reg, reg] addrmode.
665 MI.addOperand(MachineOperand::CreateReg(FrameReg, false));
666 else // tSTR has an extra register operand.
667 MI.addOperand(MachineOperand::CreateReg(0, false));
669 assert(false && "Unexpected opcode!");
671 // Add predicate back if it's needed.
672 if (MI.getDesc().isPredicable()) {
673 MachineInstrBuilder MIB(&MI);
679 void Thumb1RegisterInfo::emitPrologue(MachineFunction &MF) const {
680 MachineBasicBlock &MBB = MF.front();
681 MachineBasicBlock::iterator MBBI = MBB.begin();
682 MachineFrameInfo *MFI = MF.getFrameInfo();
683 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
684 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
685 unsigned NumBytes = MFI->getStackSize();
686 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
687 DebugLoc dl = (MBBI != MBB.end() ?
688 MBBI->getDebugLoc() : DebugLoc::getUnknownLoc());
690 // Thumb add/sub sp, imm8 instructions implicitly multiply the offset by 4.
691 NumBytes = (NumBytes + 3) & ~3;
692 MFI->setStackSize(NumBytes);
694 // Determine the sizes of each callee-save spill areas and record which frame
695 // belongs to which callee-save spill areas.
696 unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
697 int FramePtrSpillFI = 0;
700 emitSPUpdate(MBB, MBBI, TII, dl, *this, -VARegSaveSize);
702 if (!AFI->hasStackFrame()) {
704 emitSPUpdate(MBB, MBBI, TII, dl, *this, -NumBytes);
708 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
709 unsigned Reg = CSI[i].getReg();
710 int FI = CSI[i].getFrameIdx();
718 FramePtrSpillFI = FI;
719 AFI->addGPRCalleeSavedArea1Frame(FI);
727 FramePtrSpillFI = FI;
728 if (STI.isTargetDarwin()) {
729 AFI->addGPRCalleeSavedArea2Frame(FI);
732 AFI->addGPRCalleeSavedArea1Frame(FI);
737 AFI->addDPRCalleeSavedAreaFrame(FI);
742 if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPUSH) {
744 if (MBBI != MBB.end())
745 dl = MBBI->getDebugLoc();
748 // Darwin ABI requires FP to point to the stack slot that contains the
750 if (STI.isTargetDarwin() || hasFP(MF)) {
751 BuildMI(MBB, MBBI, dl, TII.get(ARM::tADDrSPi), FramePtr)
752 .addFrameIndex(FramePtrSpillFI).addImm(0);
755 // Determine starting offsets of spill areas.
756 unsigned DPRCSOffset = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize);
757 unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize;
758 unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size;
759 AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) + NumBytes);
760 AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
761 AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
762 AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
764 NumBytes = DPRCSOffset;
766 // Insert it after all the callee-save spills.
767 emitSPUpdate(MBB, MBBI, TII, dl, *this, -NumBytes);
770 if (STI.isTargetELF() && hasFP(MF)) {
771 MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() -
772 AFI->getFramePtrSpillOffset());
775 AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
776 AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
777 AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
780 static bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) {
781 for (unsigned i = 0; CSRegs[i]; ++i)
782 if (Reg == CSRegs[i])
787 static bool isCSRestore(MachineInstr *MI, const unsigned *CSRegs) {
788 return (MI->getOpcode() == ARM::tRestore &&
789 MI->getOperand(1).isFI() &&
790 isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs));
793 void Thumb1RegisterInfo::emitEpilogue(MachineFunction &MF,
794 MachineBasicBlock &MBB) const {
795 MachineBasicBlock::iterator MBBI = prior(MBB.end());
796 assert((MBBI->getOpcode() == ARM::tBX_RET ||
797 MBBI->getOpcode() == ARM::tPOP_RET) &&
798 "Can only insert epilog into returning blocks");
799 DebugLoc dl = MBBI->getDebugLoc();
800 MachineFrameInfo *MFI = MF.getFrameInfo();
801 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
802 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
803 int NumBytes = (int)MFI->getStackSize();
805 if (!AFI->hasStackFrame()) {
807 emitSPUpdate(MBB, MBBI, TII, dl, *this, NumBytes);
809 // Unwind MBBI to point to first LDR / FLDD.
810 const unsigned *CSRegs = getCalleeSavedRegs();
811 if (MBBI != MBB.begin()) {
814 while (MBBI != MBB.begin() && isCSRestore(MBBI, CSRegs));
815 if (!isCSRestore(MBBI, CSRegs))
819 // Move SP to start of FP callee save spill area.
820 NumBytes -= (AFI->getGPRCalleeSavedArea1Size() +
821 AFI->getGPRCalleeSavedArea2Size() +
822 AFI->getDPRCalleeSavedAreaSize());
825 NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
826 // Reset SP based on frame pointer only if the stack frame extends beyond
827 // frame pointer stack slot or target is ELF and the function has FP.
829 emitThumbRegPlusImmediate(MBB, MBBI, ARM::SP, FramePtr, -NumBytes,
832 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVtgpr2gpr), ARM::SP)
835 if (MBBI->getOpcode() == ARM::tBX_RET &&
836 &MBB.front() != MBBI &&
837 prior(MBBI)->getOpcode() == ARM::tPOP) {
838 MachineBasicBlock::iterator PMBBI = prior(MBBI);
839 emitSPUpdate(MBB, PMBBI, TII, dl, *this, NumBytes);
841 emitSPUpdate(MBB, MBBI, TII, dl, *this, NumBytes);
846 // Epilogue for vararg functions: pop LR to R3 and branch off it.
847 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tPOP)))
848 .addReg(0) // No write back.
849 .addReg(ARM::R3, RegState::Define);
851 emitSPUpdate(MBB, MBBI, TII, dl, *this, VARegSaveSize);
853 BuildMI(MBB, MBBI, dl, TII.get(ARM::tBX_RET_vararg))
854 .addReg(ARM::R3, RegState::Kill);