1 //===- Thumb1RegisterInfo.cpp - Thumb-1 Register Information ----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Thumb-1 implementation of the TargetRegisterInfo
13 //===----------------------------------------------------------------------===//
16 #include "ARMAddressingModes.h"
17 #include "ARMBaseInstrInfo.h"
18 #include "ARMMachineFunctionInfo.h"
19 #include "ARMSubtarget.h"
20 #include "Thumb1InstrInfo.h"
21 #include "Thumb1RegisterInfo.h"
22 #include "llvm/Constants.h"
23 #include "llvm/DerivedTypes.h"
24 #include "llvm/Function.h"
25 #include "llvm/LLVMContext.h"
26 #include "llvm/CodeGen/MachineConstantPool.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineLocation.h"
31 #include "llvm/CodeGen/MachineRegisterInfo.h"
32 #include "llvm/Target/TargetFrameInfo.h"
33 #include "llvm/Target/TargetMachine.h"
34 #include "llvm/ADT/BitVector.h"
35 #include "llvm/ADT/SmallVector.h"
36 #include "llvm/Support/CommandLine.h"
37 #include "llvm/Support/ErrorHandling.h"
38 #include "llvm/Support/raw_ostream.h"
41 extern cl::opt<bool> ReuseFrameIndexVals;
46 Thumb1RegisterInfo::Thumb1RegisterInfo(const ARMBaseInstrInfo &tii,
47 const ARMSubtarget &sti)
48 : ARMBaseRegisterInfo(tii, sti) {
51 /// emitLoadConstPool - Emits a load from constpool to materialize the
52 /// specified immediate.
53 void Thumb1RegisterInfo::emitLoadConstPool(MachineBasicBlock &MBB,
54 MachineBasicBlock::iterator &MBBI,
56 unsigned DestReg, unsigned SubIdx,
58 ARMCC::CondCodes Pred,
59 unsigned PredReg) const {
60 MachineFunction &MF = *MBB.getParent();
61 MachineConstantPool *ConstantPool = MF.getConstantPool();
62 const Constant *C = ConstantInt::get(
63 Type::getInt32Ty(MBB.getParent()->getFunction()->getContext()), Val);
64 unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
66 BuildMI(MBB, MBBI, dl, TII.get(ARM::tLDRcp))
67 .addReg(DestReg, getDefRegState(true), SubIdx)
68 .addConstantPoolIndex(Idx).addImm(Pred).addReg(PredReg);
71 const TargetRegisterClass*
72 Thumb1RegisterInfo::getPhysicalRegisterRegClass(unsigned Reg, EVT VT) const {
73 if (isARMLowRegister(Reg))
74 return ARM::tGPRRegisterClass;
78 case ARM::R8: case ARM::R9: case ARM::R10: case ARM::R11:
79 case ARM::R12: case ARM::SP: case ARM::LR: case ARM::PC:
80 return ARM::GPRRegisterClass;
83 return TargetRegisterInfo::getPhysicalRegisterRegClass(Reg, VT);
86 bool Thumb1RegisterInfo::hasReservedCallFrame(MachineFunction &MF) const {
87 const MachineFrameInfo *FFI = MF.getFrameInfo();
88 unsigned CFSize = FFI->getMaxCallFrameSize();
89 // It's not always a good idea to include the call frame as part of the
90 // stack frame. ARM (especially Thumb) has small immediate offset to
91 // address the stack frame. So a large call frame can cause poor codegen
92 // and may even makes it impossible to scavenge a register.
93 if (CFSize >= ((1 << 8) - 1) * 4 / 2) // Half of imm8 * 4
96 return !MF.getFrameInfo()->hasVarSizedObjects();
100 /// emitThumbRegPlusImmInReg - Emits a series of instructions to materialize
101 /// a destreg = basereg + immediate in Thumb code. Materialize the immediate
102 /// in a register using mov / mvn sequences or load the immediate from a
105 void emitThumbRegPlusImmInReg(MachineBasicBlock &MBB,
106 MachineBasicBlock::iterator &MBBI,
107 unsigned DestReg, unsigned BaseReg,
108 int NumBytes, bool CanChangeCC,
109 const TargetInstrInfo &TII,
110 const Thumb1RegisterInfo& MRI,
112 MachineFunction &MF = *MBB.getParent();
113 bool isHigh = !isARMLowRegister(DestReg) ||
114 (BaseReg != 0 && !isARMLowRegister(BaseReg));
116 // Subtract doesn't have high register version. Load the negative value
117 // if either base or dest register is a high register. Also, if do not
118 // issue sub as part of the sequence if condition register is to be
120 if (NumBytes < 0 && !isHigh && CanChangeCC) {
122 NumBytes = -NumBytes;
124 unsigned LdReg = DestReg;
125 if (DestReg == ARM::SP) {
126 assert(BaseReg == ARM::SP && "Unexpected!");
127 LdReg = MF.getRegInfo().createVirtualRegister(ARM::tGPRRegisterClass);
130 if (NumBytes <= 255 && NumBytes >= 0)
131 AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), LdReg))
133 else if (NumBytes < 0 && NumBytes >= -255) {
134 AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), LdReg))
136 AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tRSB), LdReg))
137 .addReg(LdReg, RegState::Kill);
139 MRI.emitLoadConstPool(MBB, MBBI, dl, LdReg, 0, NumBytes);
142 int Opc = (isSub) ? ARM::tSUBrr : (isHigh ? ARM::tADDhirr : ARM::tADDrr);
143 MachineInstrBuilder MIB =
144 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg);
145 if (Opc != ARM::tADDhirr)
146 MIB = AddDefaultT1CC(MIB);
147 if (DestReg == ARM::SP || isSub)
148 MIB.addReg(BaseReg).addReg(LdReg, RegState::Kill);
150 MIB.addReg(LdReg).addReg(BaseReg, RegState::Kill);
154 /// calcNumMI - Returns the number of instructions required to materialize
155 /// the specific add / sub r, c instruction.
156 static unsigned calcNumMI(int Opc, int ExtraOpc, unsigned Bytes,
157 unsigned NumBits, unsigned Scale) {
159 unsigned Chunk = ((1 << NumBits) - 1) * Scale;
161 if (Opc == ARM::tADDrSPi) {
162 unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes;
166 Scale = 1; // Followed by a number of tADDi8.
167 Chunk = ((1 << NumBits) - 1) * Scale;
170 NumMIs += Bytes / Chunk;
171 if ((Bytes % Chunk) != 0)
178 /// emitThumbRegPlusImmediate - Emits a series of instructions to materialize
179 /// a destreg = basereg + immediate in Thumb code.
181 void emitThumbRegPlusImmediate(MachineBasicBlock &MBB,
182 MachineBasicBlock::iterator &MBBI,
183 unsigned DestReg, unsigned BaseReg,
184 int NumBytes, const TargetInstrInfo &TII,
185 const Thumb1RegisterInfo& MRI,
187 bool isSub = NumBytes < 0;
188 unsigned Bytes = (unsigned)NumBytes;
189 if (isSub) Bytes = -NumBytes;
190 bool isMul4 = (Bytes & 3) == 0;
191 bool isTwoAddr = false;
192 bool DstNotEqBase = false;
193 unsigned NumBits = 1;
198 bool NeedPred = false;
200 if (DestReg == BaseReg && BaseReg == ARM::SP) {
201 assert(isMul4 && "Thumb sp inc / dec size must be multiple of 4!");
204 Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
206 } else if (!isSub && BaseReg == ARM::SP) {
209 // r1 = add sp, 100 * 4
213 ExtraOpc = ARM::tADDi3;
222 if (DestReg != BaseReg)
225 if (DestReg == ARM::SP) {
226 Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
227 assert(isMul4 && "Thumb sp inc / dec size must be multiple of 4!");
231 Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8;
233 NeedPred = NeedCC = true;
238 unsigned NumMIs = calcNumMI(Opc, ExtraOpc, Bytes, NumBits, Scale);
239 unsigned Threshold = (DestReg == ARM::SP) ? 3 : 2;
240 if (NumMIs > Threshold) {
241 // This will expand into too many instructions. Load the immediate from a
243 emitThumbRegPlusImmInReg(MBB, MBBI, DestReg, BaseReg, NumBytes, true, TII,
249 if (isARMLowRegister(DestReg) && isARMLowRegister(BaseReg)) {
250 // If both are low registers, emit DestReg = add BaseReg, max(Imm, 7)
251 unsigned Chunk = (1 << 3) - 1;
252 unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes;
254 const TargetInstrDesc &TID = TII.get(isSub ? ARM::tSUBi3 : ARM::tADDi3);
255 const MachineInstrBuilder MIB =
256 AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TID, DestReg));
257 AddDefaultPred(MIB.addReg(BaseReg, RegState::Kill).addImm(ThisVal));
259 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), DestReg)
260 .addReg(BaseReg, RegState::Kill);
265 unsigned Chunk = ((1 << NumBits) - 1) * Scale;
267 unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes;
270 // Build the new tADD / tSUB.
272 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg);
274 MIB = AddDefaultT1CC(MIB);
275 MIB .addReg(DestReg).addImm(ThisVal);
277 MIB = AddDefaultPred(MIB);
280 bool isKill = BaseReg != ARM::SP;
281 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg);
283 MIB = AddDefaultT1CC(MIB);
284 MIB.addReg(BaseReg, getKillRegState(isKill)).addImm(ThisVal);
286 MIB = AddDefaultPred(MIB);
289 if (Opc == ARM::tADDrSPi) {
295 Chunk = ((1 << NumBits) - 1) * Scale;
296 Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8;
297 NeedPred = NeedCC = isTwoAddr = true;
303 const TargetInstrDesc &TID = TII.get(ExtraOpc);
304 AddDefaultPred(AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TID, DestReg))
305 .addReg(DestReg, RegState::Kill)
306 .addImm(((unsigned)NumBytes) & 3));
310 static void emitSPUpdate(MachineBasicBlock &MBB,
311 MachineBasicBlock::iterator &MBBI,
312 const TargetInstrInfo &TII, DebugLoc dl,
313 const Thumb1RegisterInfo &MRI,
315 emitThumbRegPlusImmediate(MBB, MBBI, ARM::SP, ARM::SP, NumBytes, TII,
319 void Thumb1RegisterInfo::
320 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
321 MachineBasicBlock::iterator I) const {
322 if (!hasReservedCallFrame(MF)) {
323 // If we have alloca, convert as follows:
324 // ADJCALLSTACKDOWN -> sub, sp, sp, amount
325 // ADJCALLSTACKUP -> add, sp, sp, amount
326 MachineInstr *Old = I;
327 DebugLoc dl = Old->getDebugLoc();
328 unsigned Amount = Old->getOperand(0).getImm();
330 // We need to keep the stack aligned properly. To do this, we round the
331 // amount of space needed for the outgoing arguments up to the next
332 // alignment boundary.
333 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
334 Amount = (Amount+Align-1)/Align*Align;
336 // Replace the pseudo instruction with a new instruction...
337 unsigned Opc = Old->getOpcode();
338 if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
339 emitSPUpdate(MBB, I, TII, dl, *this, -Amount);
341 assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
342 emitSPUpdate(MBB, I, TII, dl, *this, Amount);
349 /// emitThumbConstant - Emit a series of instructions to materialize a
351 static void emitThumbConstant(MachineBasicBlock &MBB,
352 MachineBasicBlock::iterator &MBBI,
353 unsigned DestReg, int Imm,
354 const TargetInstrInfo &TII,
355 const Thumb1RegisterInfo& MRI,
357 bool isSub = Imm < 0;
358 if (isSub) Imm = -Imm;
360 int Chunk = (1 << 8) - 1;
361 int ThisVal = (Imm > Chunk) ? Chunk : Imm;
363 AddDefaultPred(AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8),
367 emitThumbRegPlusImmediate(MBB, MBBI, DestReg, DestReg, Imm, TII, MRI, dl);
369 const TargetInstrDesc &TID = TII.get(ARM::tRSB);
370 AddDefaultPred(AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TID, DestReg))
371 .addReg(DestReg, RegState::Kill));
375 static void removeOperands(MachineInstr &MI, unsigned i) {
377 for (unsigned e = MI.getNumOperands(); i != e; ++i)
378 MI.RemoveOperand(Op);
381 int Thumb1RegisterInfo::
382 rewriteFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
383 unsigned FrameReg, int Offset,
384 unsigned MOVOpc, unsigned ADDriOpc, unsigned SUBriOpc) const
386 // if/when eliminateFrameIndex() conforms with ARMBaseRegisterInfo
387 // version then can pull out Thumb1 specific parts here
391 /// saveScavengerRegister - Spill the register so it can be used by the
392 /// register scavenger. Return true.
394 Thumb1RegisterInfo::saveScavengerRegister(MachineBasicBlock &MBB,
395 MachineBasicBlock::iterator I,
396 MachineBasicBlock::iterator &UseMI,
397 const TargetRegisterClass *RC,
398 unsigned Reg) const {
399 // Thumb1 can't use the emergency spill slot on the stack because
400 // ldr/str immediate offsets must be positive, and if we're referencing
401 // off the frame pointer (if, for example, there are alloca() calls in
402 // the function, the offset will be negative. Use R12 instead since that's
403 // a call clobbered register that we know won't be used in Thumb1 mode.
405 BuildMI(MBB, I, DL, TII.get(ARM::tMOVtgpr2gpr)).
406 addReg(ARM::R12, RegState::Define).addReg(Reg, RegState::Kill);
408 // The UseMI is where we would like to restore the register. If there's
409 // interference with R12 before then, however, we'll need to restore it
410 // before that instead and adjust the UseMI.
412 for (MachineBasicBlock::iterator II = I; !done && II != UseMI ; ++II) {
413 // If this instruction affects R12, adjust our restore point.
414 for (unsigned i = 0, e = II->getNumOperands(); i != e; ++i) {
415 const MachineOperand &MO = II->getOperand(i);
416 if (!MO.isReg() || MO.isUndef() || !MO.getReg() ||
417 TargetRegisterInfo::isVirtualRegister(MO.getReg()))
419 if (MO.getReg() == ARM::R12) {
426 // Restore the register from R12
427 BuildMI(MBB, UseMI, DL, TII.get(ARM::tMOVgpr2tgpr)).
428 addReg(Reg, RegState::Define).addReg(ARM::R12, RegState::Kill);
434 Thumb1RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
435 int SPAdj, FrameIndexValue *Value,
436 RegScavenger *RS) const{
439 MachineInstr &MI = *II;
440 MachineBasicBlock &MBB = *MI.getParent();
441 MachineFunction &MF = *MBB.getParent();
442 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
443 DebugLoc dl = MI.getDebugLoc();
445 while (!MI.getOperand(i).isFI()) {
447 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
450 unsigned FrameReg = ARM::SP;
451 int FrameIndex = MI.getOperand(i).getIndex();
452 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
453 MF.getFrameInfo()->getStackSize() + SPAdj;
455 if (AFI->isGPRCalleeSavedArea1Frame(FrameIndex))
456 Offset -= AFI->getGPRCalleeSavedArea1Offset();
457 else if (AFI->isGPRCalleeSavedArea2Frame(FrameIndex))
458 Offset -= AFI->getGPRCalleeSavedArea2Offset();
459 else if (MF.getFrameInfo()->hasVarSizedObjects()) {
460 assert(SPAdj == 0 && hasFP(MF) && "Unexpected");
461 // There are alloca()'s in this function, must reference off the frame
463 FrameReg = getFrameRegister(MF);
464 Offset -= AFI->getFramePtrSpillOffset();
467 unsigned Opcode = MI.getOpcode();
468 const TargetInstrDesc &Desc = MI.getDesc();
469 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
471 if (Opcode == ARM::tADDrSPi) {
472 Offset += MI.getOperand(i+1).getImm();
474 // Can't use tADDrSPi if it's based off the frame pointer.
475 unsigned NumBits = 0;
477 if (FrameReg != ARM::SP) {
478 Opcode = ARM::tADDi3;
479 MI.setDesc(TII.get(Opcode));
484 assert((Offset & 3) == 0 &&
485 "Thumb add/sub sp, #imm immediate must be multiple of 4!");
489 if (Offset == 0 && getInstrPredicate(&MI, PredReg) == ARMCC::AL) {
490 // Turn it into a move.
491 MI.setDesc(TII.get(ARM::tMOVgpr2tgpr));
492 MI.getOperand(i).ChangeToRegister(FrameReg, false);
493 // Remove offset and remaining explicit predicate operands.
494 do MI.RemoveOperand(i+1);
495 while (MI.getNumOperands() > i+1 &&
496 (!MI.getOperand(i+1).isReg() || !MI.getOperand(i+1).isImm()));
500 // Common case: small offset, fits into instruction.
501 unsigned Mask = (1 << NumBits) - 1;
502 if (((Offset / Scale) & ~Mask) == 0) {
503 // Replace the FrameIndex with sp / fp
504 if (Opcode == ARM::tADDi3) {
505 removeOperands(MI, i);
506 MachineInstrBuilder MIB(&MI);
507 AddDefaultPred(AddDefaultT1CC(MIB).addReg(FrameReg)
508 .addImm(Offset / Scale));
510 MI.getOperand(i).ChangeToRegister(FrameReg, false);
511 MI.getOperand(i+1).ChangeToImmediate(Offset / Scale);
516 unsigned DestReg = MI.getOperand(0).getReg();
517 unsigned Bytes = (Offset > 0) ? Offset : -Offset;
518 unsigned NumMIs = calcNumMI(Opcode, 0, Bytes, NumBits, Scale);
519 // MI would expand into a large number of instructions. Don't try to
520 // simplify the immediate.
522 emitThumbRegPlusImmediate(MBB, II, DestReg, FrameReg, Offset, TII,
529 // Translate r0 = add sp, imm to
530 // r0 = add sp, 255*4
531 // r0 = add r0, (imm - 255*4)
532 if (Opcode == ARM::tADDi3) {
533 removeOperands(MI, i);
534 MachineInstrBuilder MIB(&MI);
535 AddDefaultPred(AddDefaultT1CC(MIB).addReg(FrameReg).addImm(Mask));
537 MI.getOperand(i).ChangeToRegister(FrameReg, false);
538 MI.getOperand(i+1).ChangeToImmediate(Mask);
540 Offset = (Offset - Mask * Scale);
541 MachineBasicBlock::iterator NII = llvm::next(II);
542 emitThumbRegPlusImmediate(MBB, NII, DestReg, DestReg, Offset, TII,
545 // Translate r0 = add sp, -imm to
546 // r0 = -imm (this is then translated into a series of instructons)
548 emitThumbConstant(MBB, II, DestReg, Offset, TII, *this, dl);
550 MI.setDesc(TII.get(ARM::tADDhirr));
551 MI.getOperand(i).ChangeToRegister(DestReg, false, false, true);
552 MI.getOperand(i+1).ChangeToRegister(FrameReg, false);
553 if (Opcode == ARM::tADDi3) {
554 MachineInstrBuilder MIB(&MI);
562 unsigned NumBits = 0;
565 case ARMII::AddrModeT1_s: {
567 InstrOffs = MI.getOperand(ImmIdx).getImm();
568 NumBits = (FrameReg == ARM::SP) ? 8 : 5;
573 llvm_unreachable("Unsupported addressing mode!");
577 Offset += InstrOffs * Scale;
578 assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
580 // Common case: small offset, fits into instruction.
581 MachineOperand &ImmOp = MI.getOperand(ImmIdx);
582 int ImmedOffset = Offset / Scale;
583 unsigned Mask = (1 << NumBits) - 1;
584 if ((unsigned)Offset <= Mask * Scale) {
585 // Replace the FrameIndex with sp
586 MI.getOperand(i).ChangeToRegister(FrameReg, false);
587 ImmOp.ChangeToImmediate(ImmedOffset);
591 bool isThumSpillRestore = Opcode == ARM::tRestore || Opcode == ARM::tSpill;
592 if (AddrMode == ARMII::AddrModeT1_s) {
593 // Thumb tLDRspi, tSTRspi. These will change to instructions that use
594 // a different base register.
596 Mask = (1 << NumBits) - 1;
598 // If this is a thumb spill / restore, we will be using a constpool load to
599 // materialize the offset.
600 if (AddrMode == ARMII::AddrModeT1_s && isThumSpillRestore)
601 ImmOp.ChangeToImmediate(0);
603 // Otherwise, it didn't fit. Pull in what we can to simplify the immed.
604 ImmedOffset = ImmedOffset & Mask;
605 ImmOp.ChangeToImmediate(ImmedOffset);
606 Offset &= ~(Mask*Scale);
610 // If we get here, the immediate doesn't fit into the instruction. We folded
611 // as much as possible above, handle the rest, providing a register that is
613 assert(Offset && "This code isn't needed if offset already handled!");
615 // Remove predicate first.
616 int PIdx = MI.findFirstPredOperandIdx();
618 removeOperands(MI, PIdx);
620 if (Desc.mayLoad()) {
621 // Use the destination register to materialize sp + offset.
622 unsigned TmpReg = MI.getOperand(0).getReg();
624 if (Opcode == ARM::tRestore) {
625 if (FrameReg == ARM::SP)
626 emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,
627 Offset, false, TII, *this, dl);
629 emitLoadConstPool(MBB, II, dl, TmpReg, 0, Offset);
633 emitThumbRegPlusImmediate(MBB, II, TmpReg, FrameReg, Offset, TII,
637 MI.setDesc(TII.get(ARM::tLDR));
638 MI.getOperand(i).ChangeToRegister(TmpReg, false, false, true);
640 // Use [reg, reg] addrmode.
641 MI.addOperand(MachineOperand::CreateReg(FrameReg, false));
642 else // tLDR has an extra register operand.
643 MI.addOperand(MachineOperand::CreateReg(0, false));
644 } else if (Desc.mayStore()) {
645 VReg = MF.getRegInfo().createVirtualRegister(ARM::tGPRRegisterClass);
646 assert (Value && "Frame index virtual allocated, but Value arg is NULL!");
648 bool TrackVReg = true;
649 Value->first = FrameReg; // use the frame register as a kind indicator
650 Value->second = Offset;
652 if (Opcode == ARM::tSpill) {
653 if (FrameReg == ARM::SP)
654 emitThumbRegPlusImmInReg(MBB, II, VReg, FrameReg,
655 Offset, false, TII, *this, dl);
657 emitLoadConstPool(MBB, II, dl, VReg, 0, Offset);
662 emitThumbRegPlusImmediate(MBB, II, VReg, FrameReg, Offset, TII,
664 MI.setDesc(TII.get(ARM::tSTR));
665 MI.getOperand(i).ChangeToRegister(VReg, false, false, true);
666 if (UseRR) // Use [reg, reg] addrmode.
667 MI.addOperand(MachineOperand::CreateReg(FrameReg, false));
668 else // tSTR has an extra register operand.
669 MI.addOperand(MachineOperand::CreateReg(0, false));
670 if (!ReuseFrameIndexVals || !TrackVReg)
673 assert(false && "Unexpected opcode!");
675 // Add predicate back if it's needed.
676 if (MI.getDesc().isPredicable()) {
677 MachineInstrBuilder MIB(&MI);
683 void Thumb1RegisterInfo::emitPrologue(MachineFunction &MF) const {
684 MachineBasicBlock &MBB = MF.front();
685 MachineBasicBlock::iterator MBBI = MBB.begin();
686 MachineFrameInfo *MFI = MF.getFrameInfo();
687 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
688 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
689 unsigned NumBytes = MFI->getStackSize();
690 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
691 DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
693 // Thumb add/sub sp, imm8 instructions implicitly multiply the offset by 4.
694 NumBytes = (NumBytes + 3) & ~3;
695 MFI->setStackSize(NumBytes);
697 // Determine the sizes of each callee-save spill areas and record which frame
698 // belongs to which callee-save spill areas.
699 unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
700 int FramePtrSpillFI = 0;
703 emitSPUpdate(MBB, MBBI, TII, dl, *this, -VARegSaveSize);
705 if (!AFI->hasStackFrame()) {
707 emitSPUpdate(MBB, MBBI, TII, dl, *this, -NumBytes);
711 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
712 unsigned Reg = CSI[i].getReg();
713 int FI = CSI[i].getFrameIdx();
721 FramePtrSpillFI = FI;
722 AFI->addGPRCalleeSavedArea1Frame(FI);
730 FramePtrSpillFI = FI;
731 if (STI.isTargetDarwin()) {
732 AFI->addGPRCalleeSavedArea2Frame(FI);
735 AFI->addGPRCalleeSavedArea1Frame(FI);
740 AFI->addDPRCalleeSavedAreaFrame(FI);
745 if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPUSH) {
747 if (MBBI != MBB.end())
748 dl = MBBI->getDebugLoc();
751 // Darwin ABI requires FP to point to the stack slot that contains the
753 if (STI.isTargetDarwin() || hasFP(MF)) {
754 BuildMI(MBB, MBBI, dl, TII.get(ARM::tADDrSPi), FramePtr)
755 .addFrameIndex(FramePtrSpillFI).addImm(0);
758 // Determine starting offsets of spill areas.
759 unsigned DPRCSOffset = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize);
760 unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize;
761 unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size;
762 AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) + NumBytes);
763 AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
764 AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
765 AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
767 NumBytes = DPRCSOffset;
769 // Insert it after all the callee-save spills.
770 emitSPUpdate(MBB, MBBI, TII, dl, *this, -NumBytes);
773 if (STI.isTargetELF() && hasFP(MF)) {
774 MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() -
775 AFI->getFramePtrSpillOffset());
778 AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
779 AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
780 AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
783 static bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) {
784 for (unsigned i = 0; CSRegs[i]; ++i)
785 if (Reg == CSRegs[i])
790 static bool isCSRestore(MachineInstr *MI, const unsigned *CSRegs) {
791 if (MI->getOpcode() == ARM::tRestore &&
792 MI->getOperand(1).isFI() &&
793 isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs))
795 else if (MI->getOpcode() == ARM::tPOP) {
796 // The first two operands are predicates. The last two are
797 // imp-def and imp-use of SP. Check everything in between.
798 for (int i = 2, e = MI->getNumOperands() - 2; i != e; ++i)
799 if (!isCalleeSavedRegister(MI->getOperand(i).getReg(), CSRegs))
806 void Thumb1RegisterInfo::emitEpilogue(MachineFunction &MF,
807 MachineBasicBlock &MBB) const {
808 MachineBasicBlock::iterator MBBI = prior(MBB.end());
809 assert((MBBI->getOpcode() == ARM::tBX_RET ||
810 MBBI->getOpcode() == ARM::tPOP_RET) &&
811 "Can only insert epilog into returning blocks");
812 DebugLoc dl = MBBI->getDebugLoc();
813 MachineFrameInfo *MFI = MF.getFrameInfo();
814 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
815 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
816 int NumBytes = (int)MFI->getStackSize();
817 const unsigned *CSRegs = getCalleeSavedRegs();
819 if (!AFI->hasStackFrame()) {
821 emitSPUpdate(MBB, MBBI, TII, dl, *this, NumBytes);
823 // Unwind MBBI to point to first LDR / VLDRD.
824 if (MBBI != MBB.begin()) {
827 while (MBBI != MBB.begin() && isCSRestore(MBBI, CSRegs));
828 if (!isCSRestore(MBBI, CSRegs))
832 // Move SP to start of FP callee save spill area.
833 NumBytes -= (AFI->getGPRCalleeSavedArea1Size() +
834 AFI->getGPRCalleeSavedArea2Size() +
835 AFI->getDPRCalleeSavedAreaSize());
838 NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
839 // Reset SP based on frame pointer only if the stack frame extends beyond
840 // frame pointer stack slot or target is ELF and the function has FP.
842 emitThumbRegPlusImmediate(MBB, MBBI, ARM::SP, FramePtr, -NumBytes,
845 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVtgpr2gpr), ARM::SP)
848 if (MBBI->getOpcode() == ARM::tBX_RET &&
849 &MBB.front() != MBBI &&
850 prior(MBBI)->getOpcode() == ARM::tPOP) {
851 MachineBasicBlock::iterator PMBBI = prior(MBBI);
852 emitSPUpdate(MBB, PMBBI, TII, dl, *this, NumBytes);
854 emitSPUpdate(MBB, MBBI, TII, dl, *this, NumBytes);
859 // Unlike T2 and ARM mode, the T1 pop instruction cannot restore
860 // to LR, and we can't pop the value directly to the PC since
861 // we need to update the SP after popping the value. Therefore, we
862 // pop the old LR into R3 as a temporary.
864 // Move back past the callee-saved register restoration
865 while (MBBI != MBB.end() && isCSRestore(MBBI, CSRegs))
867 // Epilogue for vararg functions: pop LR to R3 and branch off it.
868 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tPOP)))
869 .addReg(ARM::R3, RegState::Define);
871 emitSPUpdate(MBB, MBBI, TII, dl, *this, VARegSaveSize);
873 BuildMI(MBB, MBBI, dl, TII.get(ARM::tBX_RET_vararg))
874 .addReg(ARM::R3, RegState::Kill);
875 // erase the old tBX_RET instruction