1 //===-- Thumb1RegisterInfo.cpp - Thumb-1 Register Information -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Thumb-1 implementation of the TargetRegisterInfo
13 //===----------------------------------------------------------------------===//
15 #include "Thumb1RegisterInfo.h"
16 #include "ARMBaseInstrInfo.h"
17 #include "ARMMachineFunctionInfo.h"
18 #include "ARMSubtarget.h"
19 #include "MCTargetDesc/ARMAddressingModes.h"
20 #include "llvm/CodeGen/MachineConstantPool.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/RegisterScavenging.h"
26 #include "llvm/IR/Constants.h"
27 #include "llvm/IR/DerivedTypes.h"
28 #include "llvm/IR/Function.h"
29 #include "llvm/IR/LLVMContext.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Support/ErrorHandling.h"
32 #include "llvm/Target/TargetFrameLowering.h"
33 #include "llvm/Target/TargetMachine.h"
36 extern cl::opt<bool> ReuseFrameIndexVals;
41 Thumb1RegisterInfo::Thumb1RegisterInfo(const ARMSubtarget &sti)
42 : ARMBaseRegisterInfo(sti) {
45 const TargetRegisterClass*
46 Thumb1RegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC)
48 if (ARM::tGPRRegClass.hasSubClassEq(RC))
49 return &ARM::tGPRRegClass;
50 return ARMBaseRegisterInfo::getLargestLegalSuperClass(RC);
53 const TargetRegisterClass *
54 Thumb1RegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind)
56 return &ARM::tGPRRegClass;
59 /// emitLoadConstPool - Emits a load from constpool to materialize the
60 /// specified immediate.
62 Thumb1RegisterInfo::emitLoadConstPool(MachineBasicBlock &MBB,
63 MachineBasicBlock::iterator &MBBI,
65 unsigned DestReg, unsigned SubIdx,
67 ARMCC::CondCodes Pred, unsigned PredReg,
68 unsigned MIFlags) const {
69 MachineFunction &MF = *MBB.getParent();
70 const TargetInstrInfo &TII =
71 *MF.getTarget().getSubtargetImpl()->getInstrInfo();
72 MachineConstantPool *ConstantPool = MF.getConstantPool();
73 const Constant *C = ConstantInt::get(
74 Type::getInt32Ty(MBB.getParent()->getFunction()->getContext()), Val);
75 unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
77 BuildMI(MBB, MBBI, dl, TII.get(ARM::tLDRpci))
78 .addReg(DestReg, getDefRegState(true), SubIdx)
79 .addConstantPoolIndex(Idx).addImm(Pred).addReg(PredReg)
84 /// emitThumbRegPlusImmInReg - Emits a series of instructions to materialize
85 /// a destreg = basereg + immediate in Thumb code. Materialize the immediate
86 /// in a register using mov / mvn sequences or load the immediate from a
89 void emitThumbRegPlusImmInReg(MachineBasicBlock &MBB,
90 MachineBasicBlock::iterator &MBBI,
92 unsigned DestReg, unsigned BaseReg,
93 int NumBytes, bool CanChangeCC,
94 const TargetInstrInfo &TII,
95 const ARMBaseRegisterInfo& MRI,
96 unsigned MIFlags = MachineInstr::NoFlags) {
97 MachineFunction &MF = *MBB.getParent();
98 bool isHigh = !isARMLowRegister(DestReg) ||
99 (BaseReg != 0 && !isARMLowRegister(BaseReg));
101 // Subtract doesn't have high register version. Load the negative value
102 // if either base or dest register is a high register. Also, if do not
103 // issue sub as part of the sequence if condition register is to be
105 if (NumBytes < 0 && !isHigh && CanChangeCC) {
107 NumBytes = -NumBytes;
109 unsigned LdReg = DestReg;
110 if (DestReg == ARM::SP) {
111 assert(BaseReg == ARM::SP && "Unexpected!");
112 LdReg = MF.getRegInfo().createVirtualRegister(&ARM::tGPRRegClass);
115 if (NumBytes <= 255 && NumBytes >= 0)
116 AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), LdReg))
117 .addImm(NumBytes).setMIFlags(MIFlags);
118 else if (NumBytes < 0 && NumBytes >= -255) {
119 AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), LdReg))
120 .addImm(NumBytes).setMIFlags(MIFlags);
121 AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tRSB), LdReg))
122 .addReg(LdReg, RegState::Kill).setMIFlags(MIFlags);
124 MRI.emitLoadConstPool(MBB, MBBI, dl, LdReg, 0, NumBytes,
125 ARMCC::AL, 0, MIFlags);
128 int Opc = (isSub) ? ARM::tSUBrr : (isHigh ? ARM::tADDhirr : ARM::tADDrr);
129 MachineInstrBuilder MIB =
130 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg);
131 if (Opc != ARM::tADDhirr)
132 MIB = AddDefaultT1CC(MIB);
133 if (DestReg == ARM::SP || isSub)
134 MIB.addReg(BaseReg).addReg(LdReg, RegState::Kill);
136 MIB.addReg(LdReg).addReg(BaseReg, RegState::Kill);
140 /// calcNumMI - Returns the number of instructions required to materialize
141 /// the specific add / sub r, c instruction.
142 static unsigned calcNumMI(int Opc, int ExtraOpc, unsigned Bytes,
143 unsigned NumBits, unsigned Scale) {
145 unsigned Chunk = ((1 << NumBits) - 1) * Scale;
147 if (Opc == ARM::tADDrSPi) {
148 unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes;
152 Scale = 1; // Followed by a number of tADDi8.
153 Chunk = ((1 << NumBits) - 1) * Scale;
156 NumMIs += Bytes / Chunk;
157 if ((Bytes % Chunk) != 0)
164 /// emitThumbRegPlusImmediate - Emits a series of instructions to materialize
165 /// a destreg = basereg + immediate in Thumb code.
166 void llvm::emitThumbRegPlusImmediate(MachineBasicBlock &MBB,
167 MachineBasicBlock::iterator &MBBI,
169 unsigned DestReg, unsigned BaseReg,
170 int NumBytes, const TargetInstrInfo &TII,
171 const ARMBaseRegisterInfo& MRI,
173 bool isSub = NumBytes < 0;
174 unsigned Bytes = (unsigned)NumBytes;
175 if (isSub) Bytes = -NumBytes;
176 bool isMul4 = (Bytes & 3) == 0;
177 bool isTwoAddr = false;
178 bool DstNotEqBase = false;
179 unsigned NumBits = 1;
185 if (DestReg == BaseReg && BaseReg == ARM::SP) {
186 assert(isMul4 && "Thumb sp inc / dec size must be multiple of 4!");
189 Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
191 } else if (!isSub && BaseReg == ARM::SP) {
194 // r1 = add sp, 100 * 4
198 ExtraOpc = ARM::tADDi3;
207 if (DestReg != BaseReg)
210 if (DestReg == ARM::SP) {
211 Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
212 assert(isMul4 && "Thumb sp inc / dec size must be multiple of 4!");
216 Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8;
223 unsigned NumMIs = calcNumMI(Opc, ExtraOpc, Bytes, NumBits, Scale);
224 unsigned Threshold = (DestReg == ARM::SP) ? 3 : 2;
225 if (NumMIs > Threshold) {
226 // This will expand into too many instructions. Load the immediate from a
228 emitThumbRegPlusImmInReg(MBB, MBBI, dl,
229 DestReg, BaseReg, NumBytes, true,
235 if (isARMLowRegister(DestReg) && isARMLowRegister(BaseReg)) {
236 // If both are low registers, emit DestReg = add BaseReg, max(Imm, 7)
237 unsigned Chunk = (1 << 3) - 1;
238 unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes;
240 const MCInstrDesc &MCID = TII.get(isSub ? ARM::tSUBi3 : ARM::tADDi3);
241 const MachineInstrBuilder MIB =
242 AddDefaultT1CC(BuildMI(MBB, MBBI, dl, MCID, DestReg)
243 .setMIFlags(MIFlags));
244 AddDefaultPred(MIB.addReg(BaseReg, RegState::Kill).addImm(ThisVal));
246 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), DestReg)
247 .addReg(BaseReg, RegState::Kill))
248 .setMIFlags(MIFlags);
253 unsigned Chunk = ((1 << NumBits) - 1) * Scale;
255 unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes;
258 // Build the new tADD / tSUB.
260 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg);
262 MIB = AddDefaultT1CC(MIB);
263 MIB.addReg(DestReg).addImm(ThisVal);
264 MIB = AddDefaultPred(MIB);
265 MIB.setMIFlags(MIFlags);
267 bool isKill = BaseReg != ARM::SP;
268 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg);
270 MIB = AddDefaultT1CC(MIB);
271 MIB.addReg(BaseReg, getKillRegState(isKill)).addImm(ThisVal);
272 MIB = AddDefaultPred(MIB);
273 MIB.setMIFlags(MIFlags);
276 if (Opc == ARM::tADDrSPi) {
282 Chunk = ((1 << NumBits) - 1) * Scale;
283 Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8;
284 NeedCC = isTwoAddr = true;
290 const MCInstrDesc &MCID = TII.get(ExtraOpc);
291 AddDefaultPred(AddDefaultT1CC(BuildMI(MBB, MBBI, dl, MCID, DestReg))
292 .addReg(DestReg, RegState::Kill)
293 .addImm(((unsigned)NumBytes) & 3)
294 .setMIFlags(MIFlags));
298 /// emitThumbConstant - Emit a series of instructions to materialize a
300 static void emitThumbConstant(MachineBasicBlock &MBB,
301 MachineBasicBlock::iterator &MBBI,
302 unsigned DestReg, int Imm,
303 const TargetInstrInfo &TII,
304 const Thumb1RegisterInfo& MRI,
306 bool isSub = Imm < 0;
307 if (isSub) Imm = -Imm;
309 int Chunk = (1 << 8) - 1;
310 int ThisVal = (Imm > Chunk) ? Chunk : Imm;
312 AddDefaultPred(AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8),
316 emitThumbRegPlusImmediate(MBB, MBBI, dl, DestReg, DestReg, Imm, TII, MRI);
318 const MCInstrDesc &MCID = TII.get(ARM::tRSB);
319 AddDefaultPred(AddDefaultT1CC(BuildMI(MBB, MBBI, dl, MCID, DestReg))
320 .addReg(DestReg, RegState::Kill));
324 static void removeOperands(MachineInstr &MI, unsigned i) {
326 for (unsigned e = MI.getNumOperands(); i != e; ++i)
327 MI.RemoveOperand(Op);
330 /// convertToNonSPOpcode - Change the opcode to the non-SP version, because
331 /// we're replacing the frame index with a non-SP register.
332 static unsigned convertToNonSPOpcode(unsigned Opcode) {
344 bool Thumb1RegisterInfo::
345 rewriteFrameIndex(MachineBasicBlock::iterator II, unsigned FrameRegIdx,
346 unsigned FrameReg, int &Offset,
347 const ARMBaseInstrInfo &TII) const {
348 MachineInstr &MI = *II;
349 MachineBasicBlock &MBB = *MI.getParent();
350 DebugLoc dl = MI.getDebugLoc();
351 MachineInstrBuilder MIB(*MBB.getParent(), &MI);
352 unsigned Opcode = MI.getOpcode();
353 const MCInstrDesc &Desc = MI.getDesc();
354 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
356 if (Opcode == ARM::tADDrSPi) {
357 Offset += MI.getOperand(FrameRegIdx+1).getImm();
359 // Can't use tADDrSPi if it's based off the frame pointer.
360 unsigned NumBits = 0;
362 if (FrameReg != ARM::SP) {
363 Opcode = ARM::tADDi3;
368 assert((Offset & 3) == 0 &&
369 "Thumb add/sub sp, #imm immediate must be multiple of 4!");
373 if (Offset == 0 && getInstrPredicate(&MI, PredReg) == ARMCC::AL) {
374 // Turn it into a move.
375 MI.setDesc(TII.get(ARM::tMOVr));
376 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
378 MI.RemoveOperand(FrameRegIdx+1);
382 // Common case: small offset, fits into instruction.
383 unsigned Mask = (1 << NumBits) - 1;
384 if (((Offset / Scale) & ~Mask) == 0) {
385 // Replace the FrameIndex with sp / fp
386 if (Opcode == ARM::tADDi3) {
387 MI.setDesc(TII.get(Opcode));
388 removeOperands(MI, FrameRegIdx);
389 AddDefaultPred(AddDefaultT1CC(MIB).addReg(FrameReg)
390 .addImm(Offset / Scale));
392 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
393 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset / Scale);
398 unsigned DestReg = MI.getOperand(0).getReg();
399 unsigned Bytes = (Offset > 0) ? Offset : -Offset;
400 unsigned NumMIs = calcNumMI(Opcode, 0, Bytes, NumBits, Scale);
401 // MI would expand into a large number of instructions. Don't try to
402 // simplify the immediate.
404 emitThumbRegPlusImmediate(MBB, II, dl, DestReg, FrameReg, Offset, TII,
411 // Translate r0 = add sp, imm to
412 // r0 = add sp, 255*4
413 // r0 = add r0, (imm - 255*4)
414 if (Opcode == ARM::tADDi3) {
415 MI.setDesc(TII.get(Opcode));
416 removeOperands(MI, FrameRegIdx);
417 AddDefaultPred(AddDefaultT1CC(MIB).addReg(FrameReg).addImm(Mask));
419 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
420 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Mask);
422 Offset = (Offset - Mask * Scale);
423 MachineBasicBlock::iterator NII = std::next(II);
424 emitThumbRegPlusImmediate(MBB, NII, dl, DestReg, DestReg, Offset, TII,
427 // Translate r0 = add sp, -imm to
428 // r0 = -imm (this is then translated into a series of instructions)
430 emitThumbConstant(MBB, II, DestReg, Offset, TII, *this, dl);
432 MI.setDesc(TII.get(ARM::tADDhirr));
433 MI.getOperand(FrameRegIdx).ChangeToRegister(DestReg, false, false, true);
434 MI.getOperand(FrameRegIdx+1).ChangeToRegister(FrameReg, false);
438 if (AddrMode != ARMII::AddrModeT1_s)
439 llvm_unreachable("Unsupported addressing mode!");
441 unsigned ImmIdx = FrameRegIdx + 1;
442 int InstrOffs = MI.getOperand(ImmIdx).getImm();
443 unsigned NumBits = (FrameReg == ARM::SP) ? 8 : 5;
446 Offset += InstrOffs * Scale;
447 assert((Offset & (Scale - 1)) == 0 && "Can't encode this offset!");
449 // Common case: small offset, fits into instruction.
450 MachineOperand &ImmOp = MI.getOperand(ImmIdx);
451 int ImmedOffset = Offset / Scale;
452 unsigned Mask = (1 << NumBits) - 1;
454 if ((unsigned)Offset <= Mask * Scale) {
455 // Replace the FrameIndex with the frame register (e.g., sp).
456 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
457 ImmOp.ChangeToImmediate(ImmedOffset);
459 // If we're using a register where sp was stored, convert the instruction
460 // to the non-SP version.
461 unsigned NewOpc = convertToNonSPOpcode(Opcode);
462 if (NewOpc != Opcode && FrameReg != ARM::SP)
463 MI.setDesc(TII.get(NewOpc));
469 Mask = (1 << NumBits) - 1;
471 // If this is a thumb spill / restore, we will be using a constpool load to
472 // materialize the offset.
473 if (Opcode == ARM::tLDRspi || Opcode == ARM::tSTRspi) {
474 ImmOp.ChangeToImmediate(0);
476 // Otherwise, it didn't fit. Pull in what we can to simplify the immed.
477 ImmedOffset = ImmedOffset & Mask;
478 ImmOp.ChangeToImmediate(ImmedOffset);
479 Offset &= ~(Mask * Scale);
486 void Thumb1RegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
487 int64_t Offset) const {
488 const ARMBaseInstrInfo &TII =
489 *static_cast<const ARMBaseInstrInfo *>(MI.getParent()
494 int Off = Offset; // ARM doesn't need the general 64-bit offsets
497 while (!MI.getOperand(i).isFI()) {
499 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
501 bool Done = rewriteFrameIndex(MI, i, BaseReg, Off, TII);
502 assert (Done && "Unable to resolve frame index!");
506 /// saveScavengerRegister - Spill the register so it can be used by the
507 /// register scavenger. Return true.
509 Thumb1RegisterInfo::saveScavengerRegister(MachineBasicBlock &MBB,
510 MachineBasicBlock::iterator I,
511 MachineBasicBlock::iterator &UseMI,
512 const TargetRegisterClass *RC,
513 unsigned Reg) const {
514 // Thumb1 can't use the emergency spill slot on the stack because
515 // ldr/str immediate offsets must be positive, and if we're referencing
516 // off the frame pointer (if, for example, there are alloca() calls in
517 // the function, the offset will be negative. Use R12 instead since that's
518 // a call clobbered register that we know won't be used in Thumb1 mode.
519 const TargetInstrInfo &TII =
520 *MBB.getParent()->getTarget().getSubtargetImpl()->getInstrInfo();
522 AddDefaultPred(BuildMI(MBB, I, DL, TII.get(ARM::tMOVr))
523 .addReg(ARM::R12, RegState::Define)
524 .addReg(Reg, RegState::Kill));
526 // The UseMI is where we would like to restore the register. If there's
527 // interference with R12 before then, however, we'll need to restore it
528 // before that instead and adjust the UseMI.
530 for (MachineBasicBlock::iterator II = I; !done && II != UseMI ; ++II) {
531 if (II->isDebugValue())
533 // If this instruction affects R12, adjust our restore point.
534 for (unsigned i = 0, e = II->getNumOperands(); i != e; ++i) {
535 const MachineOperand &MO = II->getOperand(i);
536 if (MO.isRegMask() && MO.clobbersPhysReg(ARM::R12)) {
541 if (!MO.isReg() || MO.isUndef() || !MO.getReg() ||
542 TargetRegisterInfo::isVirtualRegister(MO.getReg()))
544 if (MO.getReg() == ARM::R12) {
551 // Restore the register from R12
552 AddDefaultPred(BuildMI(MBB, UseMI, DL, TII.get(ARM::tMOVr)).
553 addReg(Reg, RegState::Define).addReg(ARM::R12, RegState::Kill));
559 Thumb1RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
560 int SPAdj, unsigned FIOperandNum,
561 RegScavenger *RS) const {
563 MachineInstr &MI = *II;
564 MachineBasicBlock &MBB = *MI.getParent();
565 MachineFunction &MF = *MBB.getParent();
566 const ARMBaseInstrInfo &TII =
567 *static_cast<const ARMBaseInstrInfo *>(
568 MF.getTarget().getSubtargetImpl()->getInstrInfo());
569 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
570 DebugLoc dl = MI.getDebugLoc();
571 MachineInstrBuilder MIB(*MBB.getParent(), &MI);
573 unsigned FrameReg = ARM::SP;
574 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
575 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
576 MF.getFrameInfo()->getStackSize() + SPAdj;
578 if (MF.getFrameInfo()->hasVarSizedObjects()) {
580 MF.getTarget().getSubtargetImpl()->getFrameLowering()->hasFP(MF) &&
582 // There are alloca()'s in this function, must reference off the frame
583 // pointer or base pointer instead.
584 if (!hasBasePointer(MF)) {
585 FrameReg = getFrameRegister(MF);
586 Offset -= AFI->getFramePtrSpillOffset();
591 // PEI::scavengeFrameVirtualRegs() cannot accurately track SPAdj because the
592 // call frame setup/destroy instructions have already been eliminated. That
593 // means the stack pointer cannot be used to access the emergency spill slot
594 // when !hasReservedCallFrame().
596 if (RS && FrameReg == ARM::SP && RS->isScavengingFrameIndex(FrameIndex)){
597 assert(MF.getTarget()
600 ->hasReservedCallFrame(MF) &&
601 "Cannot use SP to access the emergency spill slot in "
602 "functions without a reserved call frame");
603 assert(!MF.getFrameInfo()->hasVarSizedObjects() &&
604 "Cannot use SP to access the emergency spill slot in "
605 "functions with variable sized frame objects");
609 // Special handling of dbg_value instructions.
610 if (MI.isDebugValue()) {
611 MI.getOperand(FIOperandNum). ChangeToRegister(FrameReg, false /*isDef*/);
612 MI.getOperand(FIOperandNum+1).ChangeToImmediate(Offset);
616 // Modify MI as necessary to handle as much of 'Offset' as possible
617 assert(AFI->isThumbFunction() &&
618 "This eliminateFrameIndex only supports Thumb1!");
619 if (rewriteFrameIndex(MI, FIOperandNum, FrameReg, Offset, TII))
622 // If we get here, the immediate doesn't fit into the instruction. We folded
623 // as much as possible above, handle the rest, providing a register that is
625 assert(Offset && "This code isn't needed if offset already handled!");
627 unsigned Opcode = MI.getOpcode();
629 // Remove predicate first.
630 int PIdx = MI.findFirstPredOperandIdx();
632 removeOperands(MI, PIdx);
635 // Use the destination register to materialize sp + offset.
636 unsigned TmpReg = MI.getOperand(0).getReg();
638 if (Opcode == ARM::tLDRspi) {
639 if (FrameReg == ARM::SP)
640 emitThumbRegPlusImmInReg(MBB, II, dl, TmpReg, FrameReg,
641 Offset, false, TII, *this);
643 emitLoadConstPool(MBB, II, dl, TmpReg, 0, Offset);
647 emitThumbRegPlusImmediate(MBB, II, dl, TmpReg, FrameReg, Offset, TII,
651 MI.setDesc(TII.get(UseRR ? ARM::tLDRr : ARM::tLDRi));
652 MI.getOperand(FIOperandNum).ChangeToRegister(TmpReg, false, false, true);
654 // Use [reg, reg] addrmode. Replace the immediate operand w/ the frame
655 // register. The offset is already handled in the vreg value.
656 MI.getOperand(FIOperandNum+1).ChangeToRegister(FrameReg, false, false,
658 } else if (MI.mayStore()) {
659 VReg = MF.getRegInfo().createVirtualRegister(&ARM::tGPRRegClass);
662 if (Opcode == ARM::tSTRspi) {
663 if (FrameReg == ARM::SP)
664 emitThumbRegPlusImmInReg(MBB, II, dl, VReg, FrameReg,
665 Offset, false, TII, *this);
667 emitLoadConstPool(MBB, II, dl, VReg, 0, Offset);
671 emitThumbRegPlusImmediate(MBB, II, dl, VReg, FrameReg, Offset, TII,
673 MI.setDesc(TII.get(UseRR ? ARM::tSTRr : ARM::tSTRi));
674 MI.getOperand(FIOperandNum).ChangeToRegister(VReg, false, false, true);
676 // Use [reg, reg] addrmode. Replace the immediate operand w/ the frame
677 // register. The offset is already handled in the vreg value.
678 MI.getOperand(FIOperandNum+1).ChangeToRegister(FrameReg, false, false,
681 llvm_unreachable("Unexpected opcode!");
684 // Add predicate back if it's needed.
685 if (MI.isPredicable())