1 //===- Thumb1RegisterInfo.cpp - Thumb-1 Register Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Thumb-1 implementation of the TargetRegisterInfo class.
12 //===----------------------------------------------------------------------===//
15 #include "ARMAddressingModes.h"
16 #include "ARMBaseInstrInfo.h"
17 #include "ARMMachineFunctionInfo.h"
18 #include "ARMSubtarget.h"
19 #include "Thumb1InstrInfo.h"
20 #include "Thumb1RegisterInfo.h"
21 #include "llvm/Constants.h"
22 #include "llvm/DerivedTypes.h"
23 #include "llvm/Function.h"
24 #include "llvm/LLVMContext.h"
25 #include "llvm/CodeGen/MachineConstantPool.h"
26 #include "llvm/CodeGen/MachineFrameInfo.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineInstrBuilder.h"
29 #include "llvm/CodeGen/MachineLocation.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/Target/TargetFrameInfo.h"
32 #include "llvm/Target/TargetMachine.h"
33 #include "llvm/ADT/BitVector.h"
34 #include "llvm/ADT/SmallVector.h"
35 #include "llvm/Support/CommandLine.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Support/raw_ostream.h"
41 ThumbRegScavenging("enable-thumb-reg-scavenging",
43 cl::desc("Enable register scavenging on Thumb"));
45 Thumb1RegisterInfo::Thumb1RegisterInfo(const ARMBaseInstrInfo &tii,
46 const ARMSubtarget &sti)
47 : ARMBaseRegisterInfo(tii, sti) {
51 const MachineInstrBuilder &AddDefaultPred(const MachineInstrBuilder &MIB) {
52 return MIB.addImm((int64_t)ARMCC::AL).addReg(0);
56 const MachineInstrBuilder &AddDefaultCC(const MachineInstrBuilder &MIB) {
57 return MIB.addReg(ARM::CPSR);
60 /// emitLoadConstPool - Emits a load from constpool to materialize the
61 /// specified immediate.
62 void Thumb1RegisterInfo::emitLoadConstPool(MachineBasicBlock &MBB,
63 MachineBasicBlock::iterator &MBBI,
65 unsigned DestReg, int Val,
66 ARMCC::CondCodes Pred,
67 unsigned PredReg) const {
68 MachineFunction &MF = *MBB.getParent();
69 MachineConstantPool *ConstantPool = MF.getConstantPool();
71 MF.getFunction()->getContext()->getConstantInt(Type::Int32Ty, Val);
72 unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
74 BuildMI(MBB, MBBI, dl, TII.get(ARM::tLDRcp), DestReg)
75 .addConstantPoolIndex(Idx).addImm(Pred).addReg(PredReg);
78 const TargetRegisterClass*
79 Thumb1RegisterInfo::getPhysicalRegisterRegClass(unsigned Reg, MVT VT) const {
80 if (isARMLowRegister(Reg))
81 return ARM::tGPRRegisterClass;
85 case ARM::R8: case ARM::R9: case ARM::R10: case ARM::R11:
86 case ARM::R12: case ARM::SP: case ARM::LR: case ARM::PC:
87 return ARM::GPRRegisterClass;
90 return TargetRegisterInfo::getPhysicalRegisterRegClass(Reg, VT);
94 Thumb1RegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const {
95 return ThumbRegScavenging;
98 bool Thumb1RegisterInfo::hasReservedCallFrame(MachineFunction &MF) const {
99 const MachineFrameInfo *FFI = MF.getFrameInfo();
100 unsigned CFSize = FFI->getMaxCallFrameSize();
101 // It's not always a good idea to include the call frame as part of the
102 // stack frame. ARM (especially Thumb) has small immediate offset to
103 // address the stack frame. So a large call frame can cause poor codegen
104 // and may even makes it impossible to scavenge a register.
105 if (CFSize >= ((1 << 8) - 1) * 4 / 2) // Half of imm8 * 4
108 return !MF.getFrameInfo()->hasVarSizedObjects();
112 /// emitThumbRegPlusImmInReg - Emits a series of instructions to materialize
113 /// a destreg = basereg + immediate in Thumb code. Materialize the immediate
114 /// in a register using mov / mvn sequences or load the immediate from a
117 void emitThumbRegPlusImmInReg(MachineBasicBlock &MBB,
118 MachineBasicBlock::iterator &MBBI,
119 unsigned DestReg, unsigned BaseReg,
120 int NumBytes, bool CanChangeCC,
121 const TargetInstrInfo &TII,
122 const Thumb1RegisterInfo& MRI,
124 bool isHigh = !isARMLowRegister(DestReg) ||
125 (BaseReg != 0 && !isARMLowRegister(BaseReg));
127 // Subtract doesn't have high register version. Load the negative value
128 // if either base or dest register is a high register. Also, if do not
129 // issue sub as part of the sequence if condition register is to be
131 if (NumBytes < 0 && !isHigh && CanChangeCC) {
133 NumBytes = -NumBytes;
135 unsigned LdReg = DestReg;
136 if (DestReg == ARM::SP) {
137 assert(BaseReg == ARM::SP && "Unexpected!");
139 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVlor2hir), ARM::R12)
140 .addReg(ARM::R3, RegState::Kill);
143 if (NumBytes <= 255 && NumBytes >= 0)
144 AddDefaultCC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), LdReg))
146 else if (NumBytes < 0 && NumBytes >= -255) {
147 AddDefaultCC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), LdReg))
149 AddDefaultCC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tRSB), LdReg))
150 .addReg(LdReg, RegState::Kill);
152 MRI.emitLoadConstPool(MBB, MBBI, dl, LdReg, NumBytes);
155 int Opc = (isSub) ? ARM::tSUBrr : (isHigh ? ARM::tADDhirr : ARM::tADDrr);
156 MachineInstrBuilder MIB =
157 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg);
158 if (Opc != ARM::tADDhirr)
159 MIB = AddDefaultCC(MIB);
160 if (DestReg == ARM::SP || isSub)
161 MIB.addReg(BaseReg).addReg(LdReg, RegState::Kill);
163 MIB.addReg(LdReg).addReg(BaseReg, RegState::Kill);
166 if (DestReg == ARM::SP)
167 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVhir2lor), ARM::R3)
168 .addReg(ARM::R12, RegState::Kill);
171 /// calcNumMI - Returns the number of instructions required to materialize
172 /// the specific add / sub r, c instruction.
173 static unsigned calcNumMI(int Opc, int ExtraOpc, unsigned Bytes,
174 unsigned NumBits, unsigned Scale) {
176 unsigned Chunk = ((1 << NumBits) - 1) * Scale;
178 if (Opc == ARM::tADDrSPi) {
179 unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes;
183 Scale = 1; // Followed by a number of tADDi8.
184 Chunk = ((1 << NumBits) - 1) * Scale;
187 NumMIs += Bytes / Chunk;
188 if ((Bytes % Chunk) != 0)
195 /// emitThumbRegPlusImmediate - Emits a series of instructions to materialize
196 /// a destreg = basereg + immediate in Thumb code.
198 void emitThumbRegPlusImmediate(MachineBasicBlock &MBB,
199 MachineBasicBlock::iterator &MBBI,
200 unsigned DestReg, unsigned BaseReg,
201 int NumBytes, const TargetInstrInfo &TII,
202 const Thumb1RegisterInfo& MRI,
204 bool isSub = NumBytes < 0;
205 unsigned Bytes = (unsigned)NumBytes;
206 if (isSub) Bytes = -NumBytes;
207 bool isMul4 = (Bytes & 3) == 0;
208 bool isTwoAddr = false;
209 bool DstNotEqBase = false;
210 unsigned NumBits = 1;
215 bool NeedPred = false;
217 if (DestReg == BaseReg && BaseReg == ARM::SP) {
218 assert(isMul4 && "Thumb sp inc / dec size must be multiple of 4!");
221 Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
223 } else if (!isSub && BaseReg == ARM::SP) {
226 // r1 = add sp, 100 * 4
230 ExtraOpc = ARM::tADDi3;
239 if (DestReg != BaseReg)
242 Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8;
243 NeedPred = NeedCC = true;
247 unsigned NumMIs = calcNumMI(Opc, ExtraOpc, Bytes, NumBits, Scale);
248 unsigned Threshold = (DestReg == ARM::SP) ? 3 : 2;
249 if (NumMIs > Threshold) {
250 // This will expand into too many instructions. Load the immediate from a
252 emitThumbRegPlusImmInReg(MBB, MBBI, DestReg, BaseReg, NumBytes, true, TII,
258 if (isARMLowRegister(DestReg) && isARMLowRegister(BaseReg)) {
259 // If both are low registers, emit DestReg = add BaseReg, max(Imm, 7)
260 unsigned Chunk = (1 << 3) - 1;
261 unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes;
263 const TargetInstrDesc &TID = TII.get(isSub ? ARM::tSUBi3 : ARM::tADDi3);
264 const MachineInstrBuilder MIB =
265 AddDefaultCC(BuildMI(MBB, MBBI, dl, TID, DestReg));
266 AddDefaultPred(MIB.addReg(BaseReg, RegState::Kill).addImm(ThisVal));
268 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), DestReg)
269 .addReg(BaseReg, RegState::Kill);
274 unsigned Chunk = ((1 << NumBits) - 1) * Scale;
276 unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes;
279 // Build the new tADD / tSUB.
281 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg);
283 MIB = AddDefaultCC(MIB);
284 MIB .addReg(DestReg).addImm(ThisVal);
286 MIB = AddDefaultPred(MIB);
289 bool isKill = BaseReg != ARM::SP;
290 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg);
292 MIB = AddDefaultCC(MIB);
293 MIB.addReg(BaseReg, getKillRegState(isKill)).addImm(ThisVal);
295 MIB = AddDefaultPred(MIB);
298 if (Opc == ARM::tADDrSPi) {
304 Chunk = ((1 << NumBits) - 1) * Scale;
305 Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8;
306 NeedPred = NeedCC = isTwoAddr = true;
312 const TargetInstrDesc &TID = TII.get(ExtraOpc);
313 AddDefaultPred(AddDefaultCC(BuildMI(MBB, MBBI, dl, TID, DestReg))
314 .addReg(DestReg, RegState::Kill)
315 .addImm(((unsigned)NumBytes) & 3));
319 static void emitSPUpdate(MachineBasicBlock &MBB,
320 MachineBasicBlock::iterator &MBBI,
321 const TargetInstrInfo &TII, DebugLoc dl,
322 const Thumb1RegisterInfo &MRI,
324 emitThumbRegPlusImmediate(MBB, MBBI, ARM::SP, ARM::SP, NumBytes, TII,
328 void Thumb1RegisterInfo::
329 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
330 MachineBasicBlock::iterator I) const {
331 if (!hasReservedCallFrame(MF)) {
332 // If we have alloca, convert as follows:
333 // ADJCALLSTACKDOWN -> sub, sp, sp, amount
334 // ADJCALLSTACKUP -> add, sp, sp, amount
335 MachineInstr *Old = I;
336 DebugLoc dl = Old->getDebugLoc();
337 unsigned Amount = Old->getOperand(0).getImm();
339 // We need to keep the stack aligned properly. To do this, we round the
340 // amount of space needed for the outgoing arguments up to the next
341 // alignment boundary.
342 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
343 Amount = (Amount+Align-1)/Align*Align;
345 // Replace the pseudo instruction with a new instruction...
346 unsigned Opc = Old->getOpcode();
347 if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
348 emitSPUpdate(MBB, I, TII, dl, *this, -Amount);
350 assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
351 emitSPUpdate(MBB, I, TII, dl, *this, Amount);
358 /// emitThumbConstant - Emit a series of instructions to materialize a
360 static void emitThumbConstant(MachineBasicBlock &MBB,
361 MachineBasicBlock::iterator &MBBI,
362 unsigned DestReg, int Imm,
363 const TargetInstrInfo &TII,
364 const Thumb1RegisterInfo& MRI,
366 bool isSub = Imm < 0;
367 if (isSub) Imm = -Imm;
369 int Chunk = (1 << 8) - 1;
370 int ThisVal = (Imm > Chunk) ? Chunk : Imm;
372 AddDefaultPred(AddDefaultCC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8),
376 emitThumbRegPlusImmediate(MBB, MBBI, DestReg, DestReg, Imm, TII, MRI, dl);
378 const TargetInstrDesc &TID = TII.get(ARM::tRSB);
379 AddDefaultPred(AddDefaultCC(BuildMI(MBB, MBBI, dl, TID, DestReg))
380 .addReg(DestReg, RegState::Kill));
384 static void removeOperands(MachineInstr &MI, unsigned i) {
386 for (unsigned e = MI.getNumOperands(); i != e; ++i)
387 MI.RemoveOperand(Op);
390 void Thumb1RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
391 int SPAdj, RegScavenger *RS) const{
393 MachineInstr &MI = *II;
394 MachineBasicBlock &MBB = *MI.getParent();
395 MachineFunction &MF = *MBB.getParent();
396 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
397 DebugLoc dl = MI.getDebugLoc();
399 while (!MI.getOperand(i).isFI()) {
401 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
404 unsigned FrameReg = ARM::SP;
405 int FrameIndex = MI.getOperand(i).getIndex();
406 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
407 MF.getFrameInfo()->getStackSize() + SPAdj;
409 if (AFI->isGPRCalleeSavedArea1Frame(FrameIndex))
410 Offset -= AFI->getGPRCalleeSavedArea1Offset();
411 else if (AFI->isGPRCalleeSavedArea2Frame(FrameIndex))
412 Offset -= AFI->getGPRCalleeSavedArea2Offset();
413 else if (hasFP(MF)) {
414 assert(SPAdj == 0 && "Unexpected");
415 // There is alloca()'s in this function, must reference off the frame
417 FrameReg = getFrameRegister(MF);
418 Offset -= AFI->getFramePtrSpillOffset();
421 unsigned Opcode = MI.getOpcode();
422 const TargetInstrDesc &Desc = MI.getDesc();
423 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
425 if (Opcode == ARM::tADDrSPi) {
426 Offset += MI.getOperand(i+1).getImm();
428 // Can't use tADDrSPi if it's based off the frame pointer.
429 unsigned NumBits = 0;
431 if (FrameReg != ARM::SP) {
432 Opcode = ARM::tADDi3;
433 MI.setDesc(TII.get(Opcode));
438 assert((Offset & 3) == 0 &&
439 "Thumb add/sub sp, #imm immediate must be multiple of 4!");
443 // Turn it into a move.
444 MI.setDesc(TII.get(ARM::tMOVhir2lor));
445 MI.getOperand(i).ChangeToRegister(FrameReg, false);
446 MI.RemoveOperand(i+1);
450 // Common case: small offset, fits into instruction.
451 unsigned Mask = (1 << NumBits) - 1;
452 if (((Offset / Scale) & ~Mask) == 0) {
453 // Replace the FrameIndex with sp / fp
454 if (Opcode == ARM::tADDi3) {
455 removeOperands(MI, i);
456 MachineInstrBuilder MIB(&MI);
457 AddDefaultPred(AddDefaultCC(MIB).addReg(FrameReg).addImm(Offset/Scale));
459 MI.getOperand(i).ChangeToRegister(FrameReg, false);
460 MI.getOperand(i+1).ChangeToImmediate(Offset / Scale);
465 unsigned DestReg = MI.getOperand(0).getReg();
466 unsigned Bytes = (Offset > 0) ? Offset : -Offset;
467 unsigned NumMIs = calcNumMI(Opcode, 0, Bytes, NumBits, Scale);
468 // MI would expand into a large number of instructions. Don't try to
469 // simplify the immediate.
471 emitThumbRegPlusImmediate(MBB, II, DestReg, FrameReg, Offset, TII,
478 // Translate r0 = add sp, imm to
479 // r0 = add sp, 255*4
480 // r0 = add r0, (imm - 255*4)
481 if (Opcode == ARM::tADDi3) {
482 removeOperands(MI, i);
483 MachineInstrBuilder MIB(&MI);
484 AddDefaultPred(AddDefaultCC(MIB).addReg(FrameReg).addImm(Mask));
486 MI.getOperand(i).ChangeToRegister(FrameReg, false);
487 MI.getOperand(i+1).ChangeToImmediate(Mask);
489 Offset = (Offset - Mask * Scale);
490 MachineBasicBlock::iterator NII = next(II);
491 emitThumbRegPlusImmediate(MBB, NII, DestReg, DestReg, Offset, TII,
494 // Translate r0 = add sp, -imm to
495 // r0 = -imm (this is then translated into a series of instructons)
497 emitThumbConstant(MBB, II, DestReg, Offset, TII, *this, dl);
498 MI.setDesc(TII.get(ARM::tADDhirr));
499 MI.getOperand(i).ChangeToRegister(DestReg, false, false, true);
500 MI.getOperand(i+1).ChangeToRegister(FrameReg, false);
506 unsigned NumBits = 0;
509 case ARMII::AddrModeT1_s: {
511 InstrOffs = MI.getOperand(ImmIdx).getImm();
512 NumBits = (FrameReg == ARM::SP) ? 8 : 5;
517 llvm_unreachable("Unsupported addressing mode!");
521 Offset += InstrOffs * Scale;
522 assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
524 // Common case: small offset, fits into instruction.
525 MachineOperand &ImmOp = MI.getOperand(ImmIdx);
526 int ImmedOffset = Offset / Scale;
527 unsigned Mask = (1 << NumBits) - 1;
528 if ((unsigned)Offset <= Mask * Scale) {
529 // Replace the FrameIndex with sp
530 MI.getOperand(i).ChangeToRegister(FrameReg, false);
531 ImmOp.ChangeToImmediate(ImmedOffset);
535 bool isThumSpillRestore = Opcode == ARM::tRestore || Opcode == ARM::tSpill;
536 if (AddrMode == ARMII::AddrModeT1_s) {
537 // Thumb tLDRspi, tSTRspi. These will change to instructions that use
538 // a different base register.
540 Mask = (1 << NumBits) - 1;
542 // If this is a thumb spill / restore, we will be using a constpool load to
543 // materialize the offset.
544 if (AddrMode == ARMII::AddrModeT1_s && isThumSpillRestore)
545 ImmOp.ChangeToImmediate(0);
547 // Otherwise, it didn't fit. Pull in what we can to simplify the immed.
548 ImmedOffset = ImmedOffset & Mask;
549 ImmOp.ChangeToImmediate(ImmedOffset);
550 Offset &= ~(Mask*Scale);
554 // If we get here, the immediate doesn't fit into the instruction. We folded
555 // as much as possible above, handle the rest, providing a register that is
557 assert(Offset && "This code isn't needed if offset already handled!");
559 // Remove predicate first.
560 int PIdx = MI.findFirstPredOperandIdx();
562 removeOperands(MI, PIdx);
564 if (Desc.mayLoad()) {
565 // Use the destination register to materialize sp + offset.
566 unsigned TmpReg = MI.getOperand(0).getReg();
568 if (Opcode == ARM::tRestore) {
569 if (FrameReg == ARM::SP)
570 emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,
571 Offset, false, TII, *this, dl);
573 emitLoadConstPool(MBB, II, dl, TmpReg, Offset);
577 emitThumbRegPlusImmediate(MBB, II, TmpReg, FrameReg, Offset, TII,
581 MI.setDesc(TII.get(ARM::tLDR));
582 MI.getOperand(i).ChangeToRegister(TmpReg, false, false, true);
584 // Use [reg, reg] addrmode.
585 MI.addOperand(MachineOperand::CreateReg(FrameReg, false));
586 else // tLDR has an extra register operand.
587 MI.addOperand(MachineOperand::CreateReg(0, false));
588 } else if (Desc.mayStore()) {
589 // FIXME! This is horrific!!! We need register scavenging.
590 // Our temporary workaround has marked r3 unavailable. Of course, r3 is
591 // also a ABI register so it's possible that is is the register that is
592 // being storing here. If that's the case, we do the following:
594 // Use r2 to materialize sp + offset
597 unsigned ValReg = MI.getOperand(0).getReg();
598 unsigned TmpReg = ARM::R3;
600 if (ValReg == ARM::R3) {
601 BuildMI(MBB, II, dl, TII.get(ARM::tMOVlor2hir), ARM::R12)
602 .addReg(ARM::R2, RegState::Kill);
605 if (TmpReg == ARM::R3 && AFI->isR3LiveIn())
606 BuildMI(MBB, II, dl, TII.get(ARM::tMOVlor2hir), ARM::R12)
607 .addReg(ARM::R3, RegState::Kill);
608 if (Opcode == ARM::tSpill) {
609 if (FrameReg == ARM::SP)
610 emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,
611 Offset, false, TII, *this, dl);
613 emitLoadConstPool(MBB, II, dl, TmpReg, Offset);
617 emitThumbRegPlusImmediate(MBB, II, TmpReg, FrameReg, Offset, TII,
619 MI.setDesc(TII.get(ARM::tSTR));
620 MI.getOperand(i).ChangeToRegister(TmpReg, false, false, true);
621 if (UseRR) // Use [reg, reg] addrmode.
622 MI.addOperand(MachineOperand::CreateReg(FrameReg, false));
623 else // tSTR has an extra register operand.
624 MI.addOperand(MachineOperand::CreateReg(0, false));
626 MachineBasicBlock::iterator NII = next(II);
627 if (ValReg == ARM::R3)
628 BuildMI(MBB, NII, dl, TII.get(ARM::tMOVhir2lor), ARM::R2)
629 .addReg(ARM::R12, RegState::Kill);
630 if (TmpReg == ARM::R3 && AFI->isR3LiveIn())
631 BuildMI(MBB, NII, dl, TII.get(ARM::tMOVhir2lor), ARM::R3)
632 .addReg(ARM::R12, RegState::Kill);
634 assert(false && "Unexpected opcode!");
636 // Add predicate back if it's needed.
637 if (MI.getDesc().isPredicable()) {
638 MachineInstrBuilder MIB(&MI);
643 void Thumb1RegisterInfo::emitPrologue(MachineFunction &MF) const {
644 MachineBasicBlock &MBB = MF.front();
645 MachineBasicBlock::iterator MBBI = MBB.begin();
646 MachineFrameInfo *MFI = MF.getFrameInfo();
647 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
648 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
649 unsigned NumBytes = MFI->getStackSize();
650 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
651 DebugLoc dl = (MBBI != MBB.end() ?
652 MBBI->getDebugLoc() : DebugLoc::getUnknownLoc());
654 // Check if R3 is live in. It might have to be used as a scratch register.
655 for (MachineRegisterInfo::livein_iterator I =MF.getRegInfo().livein_begin(),
656 E = MF.getRegInfo().livein_end(); I != E; ++I) {
657 if (I->first == ARM::R3) {
658 AFI->setR3IsLiveIn(true);
663 // Thumb add/sub sp, imm8 instructions implicitly multiply the offset by 4.
664 NumBytes = (NumBytes + 3) & ~3;
665 MFI->setStackSize(NumBytes);
667 // Determine the sizes of each callee-save spill areas and record which frame
668 // belongs to which callee-save spill areas.
669 unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
670 int FramePtrSpillFI = 0;
673 emitSPUpdate(MBB, MBBI, TII, dl, *this, -VARegSaveSize);
675 if (!AFI->hasStackFrame()) {
677 emitSPUpdate(MBB, MBBI, TII, dl, *this, -NumBytes);
681 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
682 unsigned Reg = CSI[i].getReg();
683 int FI = CSI[i].getFrameIdx();
691 FramePtrSpillFI = FI;
692 AFI->addGPRCalleeSavedArea1Frame(FI);
700 FramePtrSpillFI = FI;
701 if (STI.isTargetDarwin()) {
702 AFI->addGPRCalleeSavedArea2Frame(FI);
705 AFI->addGPRCalleeSavedArea1Frame(FI);
710 AFI->addDPRCalleeSavedAreaFrame(FI);
715 if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPUSH) {
717 if (MBBI != MBB.end())
718 dl = MBBI->getDebugLoc();
721 // Darwin ABI requires FP to point to the stack slot that contains the
723 if (STI.isTargetDarwin() || hasFP(MF)) {
724 MachineInstrBuilder MIB =
725 BuildMI(MBB, MBBI, dl, TII.get(ARM::tADDrSPi), FramePtr)
726 .addFrameIndex(FramePtrSpillFI).addImm(0);
729 // Determine starting offsets of spill areas.
730 unsigned DPRCSOffset = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize);
731 unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize;
732 unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size;
733 AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) + NumBytes);
734 AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
735 AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
736 AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
738 NumBytes = DPRCSOffset;
740 // Insert it after all the callee-save spills.
741 emitSPUpdate(MBB, MBBI, TII, dl, *this, -NumBytes);
744 if (STI.isTargetELF() && hasFP(MF)) {
745 MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() -
746 AFI->getFramePtrSpillOffset());
749 AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
750 AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
751 AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
754 static bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) {
755 for (unsigned i = 0; CSRegs[i]; ++i)
756 if (Reg == CSRegs[i])
761 static bool isCSRestore(MachineInstr *MI, const unsigned *CSRegs) {
762 return (MI->getOpcode() == ARM::tRestore &&
763 MI->getOperand(1).isFI() &&
764 isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs));
767 void Thumb1RegisterInfo::emitEpilogue(MachineFunction &MF,
768 MachineBasicBlock &MBB) const {
769 MachineBasicBlock::iterator MBBI = prior(MBB.end());
770 assert((MBBI->getOpcode() == ARM::tBX_RET ||
771 MBBI->getOpcode() == ARM::tPOP_RET) &&
772 "Can only insert epilog into returning blocks");
773 DebugLoc dl = MBBI->getDebugLoc();
774 MachineFrameInfo *MFI = MF.getFrameInfo();
775 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
776 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
777 int NumBytes = (int)MFI->getStackSize();
779 if (!AFI->hasStackFrame()) {
781 emitSPUpdate(MBB, MBBI, TII, dl, *this, NumBytes);
783 // Unwind MBBI to point to first LDR / FLDD.
784 const unsigned *CSRegs = getCalleeSavedRegs();
785 if (MBBI != MBB.begin()) {
788 while (MBBI != MBB.begin() && isCSRestore(MBBI, CSRegs));
789 if (!isCSRestore(MBBI, CSRegs))
793 // Move SP to start of FP callee save spill area.
794 NumBytes -= (AFI->getGPRCalleeSavedArea1Size() +
795 AFI->getGPRCalleeSavedArea2Size() +
796 AFI->getDPRCalleeSavedAreaSize());
799 NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
800 // Reset SP based on frame pointer only if the stack frame extends beyond
801 // frame pointer stack slot or target is ELF and the function has FP.
803 emitThumbRegPlusImmediate(MBB, MBBI, ARM::SP, FramePtr, -NumBytes,
806 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVlor2hir), ARM::SP)
809 if (MBBI->getOpcode() == ARM::tBX_RET &&
810 &MBB.front() != MBBI &&
811 prior(MBBI)->getOpcode() == ARM::tPOP) {
812 MachineBasicBlock::iterator PMBBI = prior(MBBI);
813 emitSPUpdate(MBB, PMBBI, TII, dl, *this, NumBytes);
815 emitSPUpdate(MBB, MBBI, TII, dl, *this, NumBytes);
820 // Epilogue for vararg functions: pop LR to R3 and branch off it.
821 // FIXME: Verify this is still ok when R3 is no longer being reserved.
822 BuildMI(MBB, MBBI, dl, TII.get(ARM::tPOP)).addReg(ARM::R3);
824 emitSPUpdate(MBB, MBBI, TII, dl, *this, VARegSaveSize);
826 BuildMI(MBB, MBBI, dl, TII.get(ARM::tBX_RET_vararg)).addReg(ARM::R3);