1 //===- Thumb1RegisterInfo.cpp - Thumb-1 Register Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Thumb-1 implementation of the TargetRegisterInfo class.
12 //===----------------------------------------------------------------------===//
15 #include "ARMAddressingModes.h"
16 #include "ARMBaseInstrInfo.h"
17 #include "ARMMachineFunctionInfo.h"
18 #include "ARMSubtarget.h"
19 #include "Thumb1InstrInfo.h"
20 #include "Thumb1RegisterInfo.h"
21 #include "llvm/Constants.h"
22 #include "llvm/DerivedTypes.h"
23 #include "llvm/Function.h"
24 #include "llvm/LLVMContext.h"
25 #include "llvm/CodeGen/MachineConstantPool.h"
26 #include "llvm/CodeGen/MachineFrameInfo.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineInstrBuilder.h"
29 #include "llvm/CodeGen/MachineLocation.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/Target/TargetFrameInfo.h"
32 #include "llvm/Target/TargetMachine.h"
33 #include "llvm/ADT/BitVector.h"
34 #include "llvm/ADT/SmallVector.h"
35 #include "llvm/Support/CommandLine.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Support/raw_ostream.h"
41 ThumbRegScavenging("enable-thumb-reg-scavenging",
43 cl::desc("Enable register scavenging on Thumb"));
45 Thumb1RegisterInfo::Thumb1RegisterInfo(const ARMBaseInstrInfo &tii,
46 const ARMSubtarget &sti)
47 : ARMBaseRegisterInfo(tii, sti) {
50 /// emitLoadConstPool - Emits a load from constpool to materialize the
51 /// specified immediate.
52 void Thumb1RegisterInfo::emitLoadConstPool(MachineBasicBlock &MBB,
53 MachineBasicBlock::iterator &MBBI,
55 unsigned DestReg, unsigned SubIdx,
57 ARMCC::CondCodes Pred,
58 unsigned PredReg) const {
59 MachineFunction &MF = *MBB.getParent();
60 MachineConstantPool *ConstantPool = MF.getConstantPool();
61 Constant *C = ConstantInt::get(Type::Int32Ty, Val);
62 unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
64 BuildMI(MBB, MBBI, dl, TII.get(ARM::tLDRcp))
65 .addReg(DestReg, getDefRegState(true), SubIdx)
66 .addConstantPoolIndex(Idx).addImm(Pred).addReg(PredReg);
69 const TargetRegisterClass*
70 Thumb1RegisterInfo::getPhysicalRegisterRegClass(unsigned Reg, MVT VT) const {
71 if (isARMLowRegister(Reg))
72 return ARM::tGPRRegisterClass;
76 case ARM::R8: case ARM::R9: case ARM::R10: case ARM::R11:
77 case ARM::R12: case ARM::SP: case ARM::LR: case ARM::PC:
78 return ARM::GPRRegisterClass;
81 return TargetRegisterInfo::getPhysicalRegisterRegClass(Reg, VT);
85 Thumb1RegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const {
86 return ThumbRegScavenging;
89 bool Thumb1RegisterInfo::hasReservedCallFrame(MachineFunction &MF) const {
90 const MachineFrameInfo *FFI = MF.getFrameInfo();
91 unsigned CFSize = FFI->getMaxCallFrameSize();
92 // It's not always a good idea to include the call frame as part of the
93 // stack frame. ARM (especially Thumb) has small immediate offset to
94 // address the stack frame. So a large call frame can cause poor codegen
95 // and may even makes it impossible to scavenge a register.
96 if (CFSize >= ((1 << 8) - 1) * 4 / 2) // Half of imm8 * 4
99 return !MF.getFrameInfo()->hasVarSizedObjects();
103 /// emitThumbRegPlusImmInReg - Emits a series of instructions to materialize
104 /// a destreg = basereg + immediate in Thumb code. Materialize the immediate
105 /// in a register using mov / mvn sequences or load the immediate from a
108 void emitThumbRegPlusImmInReg(MachineBasicBlock &MBB,
109 MachineBasicBlock::iterator &MBBI,
110 unsigned DestReg, unsigned BaseReg,
111 int NumBytes, bool CanChangeCC,
112 const TargetInstrInfo &TII,
113 const Thumb1RegisterInfo& MRI,
115 bool isHigh = !isARMLowRegister(DestReg) ||
116 (BaseReg != 0 && !isARMLowRegister(BaseReg));
118 // Subtract doesn't have high register version. Load the negative value
119 // if either base or dest register is a high register. Also, if do not
120 // issue sub as part of the sequence if condition register is to be
122 if (NumBytes < 0 && !isHigh && CanChangeCC) {
124 NumBytes = -NumBytes;
126 unsigned LdReg = DestReg;
127 if (DestReg == ARM::SP) {
128 assert(BaseReg == ARM::SP && "Unexpected!");
130 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVtgpr2gpr), ARM::R12)
131 .addReg(ARM::R3, RegState::Kill);
134 if (NumBytes <= 255 && NumBytes >= 0)
135 AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), LdReg))
137 else if (NumBytes < 0 && NumBytes >= -255) {
138 AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), LdReg))
140 AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tRSB), LdReg))
141 .addReg(LdReg, RegState::Kill);
143 MRI.emitLoadConstPool(MBB, MBBI, dl, LdReg, 0, NumBytes);
146 int Opc = (isSub) ? ARM::tSUBrr : (isHigh ? ARM::tADDhirr : ARM::tADDrr);
147 MachineInstrBuilder MIB =
148 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg);
149 if (Opc != ARM::tADDhirr)
150 MIB = AddDefaultT1CC(MIB);
151 if (DestReg == ARM::SP || isSub)
152 MIB.addReg(BaseReg).addReg(LdReg, RegState::Kill);
154 MIB.addReg(LdReg).addReg(BaseReg, RegState::Kill);
157 if (DestReg == ARM::SP)
158 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2tgpr), ARM::R3)
159 .addReg(ARM::R12, RegState::Kill);
162 /// calcNumMI - Returns the number of instructions required to materialize
163 /// the specific add / sub r, c instruction.
164 static unsigned calcNumMI(int Opc, int ExtraOpc, unsigned Bytes,
165 unsigned NumBits, unsigned Scale) {
167 unsigned Chunk = ((1 << NumBits) - 1) * Scale;
169 if (Opc == ARM::tADDrSPi) {
170 unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes;
174 Scale = 1; // Followed by a number of tADDi8.
175 Chunk = ((1 << NumBits) - 1) * Scale;
178 NumMIs += Bytes / Chunk;
179 if ((Bytes % Chunk) != 0)
186 /// emitThumbRegPlusImmediate - Emits a series of instructions to materialize
187 /// a destreg = basereg + immediate in Thumb code.
189 void emitThumbRegPlusImmediate(MachineBasicBlock &MBB,
190 MachineBasicBlock::iterator &MBBI,
191 unsigned DestReg, unsigned BaseReg,
192 int NumBytes, const TargetInstrInfo &TII,
193 const Thumb1RegisterInfo& MRI,
195 bool isSub = NumBytes < 0;
196 unsigned Bytes = (unsigned)NumBytes;
197 if (isSub) Bytes = -NumBytes;
198 bool isMul4 = (Bytes & 3) == 0;
199 bool isTwoAddr = false;
200 bool DstNotEqBase = false;
201 unsigned NumBits = 1;
206 bool NeedPred = false;
208 if (DestReg == BaseReg && BaseReg == ARM::SP) {
209 assert(isMul4 && "Thumb sp inc / dec size must be multiple of 4!");
212 Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
214 } else if (!isSub && BaseReg == ARM::SP) {
217 // r1 = add sp, 100 * 4
221 ExtraOpc = ARM::tADDi3;
230 if (DestReg != BaseReg)
233 if (DestReg == ARM::SP) {
234 Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
235 assert(isMul4 && "Thumb sp inc / dec size must be multiple of 4!");
239 Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8;
241 NeedPred = NeedCC = true;
246 unsigned NumMIs = calcNumMI(Opc, ExtraOpc, Bytes, NumBits, Scale);
247 unsigned Threshold = (DestReg == ARM::SP) ? 3 : 2;
248 if (NumMIs > Threshold) {
249 // This will expand into too many instructions. Load the immediate from a
251 emitThumbRegPlusImmInReg(MBB, MBBI, DestReg, BaseReg, NumBytes, true, TII,
257 if (isARMLowRegister(DestReg) && isARMLowRegister(BaseReg)) {
258 // If both are low registers, emit DestReg = add BaseReg, max(Imm, 7)
259 unsigned Chunk = (1 << 3) - 1;
260 unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes;
262 const TargetInstrDesc &TID = TII.get(isSub ? ARM::tSUBi3 : ARM::tADDi3);
263 const MachineInstrBuilder MIB =
264 AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TID, DestReg));
265 AddDefaultPred(MIB.addReg(BaseReg, RegState::Kill).addImm(ThisVal));
267 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), DestReg)
268 .addReg(BaseReg, RegState::Kill);
273 unsigned Chunk = ((1 << NumBits) - 1) * Scale;
275 unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes;
278 // Build the new tADD / tSUB.
280 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg);
282 MIB = AddDefaultT1CC(MIB);
283 MIB .addReg(DestReg).addImm(ThisVal);
285 MIB = AddDefaultPred(MIB);
288 bool isKill = BaseReg != ARM::SP;
289 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg);
291 MIB = AddDefaultT1CC(MIB);
292 MIB.addReg(BaseReg, getKillRegState(isKill)).addImm(ThisVal);
294 MIB = AddDefaultPred(MIB);
297 if (Opc == ARM::tADDrSPi) {
303 Chunk = ((1 << NumBits) - 1) * Scale;
304 Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8;
305 NeedPred = NeedCC = isTwoAddr = true;
311 const TargetInstrDesc &TID = TII.get(ExtraOpc);
312 AddDefaultPred(AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TID, DestReg))
313 .addReg(DestReg, RegState::Kill)
314 .addImm(((unsigned)NumBytes) & 3));
318 static void emitSPUpdate(MachineBasicBlock &MBB,
319 MachineBasicBlock::iterator &MBBI,
320 const TargetInstrInfo &TII, DebugLoc dl,
321 const Thumb1RegisterInfo &MRI,
323 emitThumbRegPlusImmediate(MBB, MBBI, ARM::SP, ARM::SP, NumBytes, TII,
327 void Thumb1RegisterInfo::
328 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
329 MachineBasicBlock::iterator I) const {
330 if (!hasReservedCallFrame(MF)) {
331 // If we have alloca, convert as follows:
332 // ADJCALLSTACKDOWN -> sub, sp, sp, amount
333 // ADJCALLSTACKUP -> add, sp, sp, amount
334 MachineInstr *Old = I;
335 DebugLoc dl = Old->getDebugLoc();
336 unsigned Amount = Old->getOperand(0).getImm();
338 // We need to keep the stack aligned properly. To do this, we round the
339 // amount of space needed for the outgoing arguments up to the next
340 // alignment boundary.
341 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
342 Amount = (Amount+Align-1)/Align*Align;
344 // Replace the pseudo instruction with a new instruction...
345 unsigned Opc = Old->getOpcode();
346 if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
347 emitSPUpdate(MBB, I, TII, dl, *this, -Amount);
349 assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
350 emitSPUpdate(MBB, I, TII, dl, *this, Amount);
357 /// emitThumbConstant - Emit a series of instructions to materialize a
359 static void emitThumbConstant(MachineBasicBlock &MBB,
360 MachineBasicBlock::iterator &MBBI,
361 unsigned DestReg, int Imm,
362 const TargetInstrInfo &TII,
363 const Thumb1RegisterInfo& MRI,
365 bool isSub = Imm < 0;
366 if (isSub) Imm = -Imm;
368 int Chunk = (1 << 8) - 1;
369 int ThisVal = (Imm > Chunk) ? Chunk : Imm;
371 AddDefaultPred(AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8),
375 emitThumbRegPlusImmediate(MBB, MBBI, DestReg, DestReg, Imm, TII, MRI, dl);
377 const TargetInstrDesc &TID = TII.get(ARM::tRSB);
378 AddDefaultPred(AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TID, DestReg))
379 .addReg(DestReg, RegState::Kill));
383 static void removeOperands(MachineInstr &MI, unsigned i) {
385 for (unsigned e = MI.getNumOperands(); i != e; ++i)
386 MI.RemoveOperand(Op);
389 int Thumb1RegisterInfo::
390 rewriteFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
391 unsigned FrameReg, int Offset,
392 unsigned MOVOpc, unsigned ADDriOpc, unsigned SUBriOpc) const
394 // if/when eliminateFrameIndex() conforms with ARMBaseRegisterInfo
395 // version then can pull out Thumb1 specific parts here
399 void Thumb1RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
400 int SPAdj, RegScavenger *RS) const{
402 MachineInstr &MI = *II;
403 MachineBasicBlock &MBB = *MI.getParent();
404 MachineFunction &MF = *MBB.getParent();
405 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
406 DebugLoc dl = MI.getDebugLoc();
408 while (!MI.getOperand(i).isFI()) {
410 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
413 unsigned FrameReg = ARM::SP;
414 int FrameIndex = MI.getOperand(i).getIndex();
415 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
416 MF.getFrameInfo()->getStackSize() + SPAdj;
418 if (AFI->isGPRCalleeSavedArea1Frame(FrameIndex))
419 Offset -= AFI->getGPRCalleeSavedArea1Offset();
420 else if (AFI->isGPRCalleeSavedArea2Frame(FrameIndex))
421 Offset -= AFI->getGPRCalleeSavedArea2Offset();
422 else if (hasFP(MF)) {
423 assert(SPAdj == 0 && "Unexpected");
424 // There is alloca()'s in this function, must reference off the frame
426 FrameReg = getFrameRegister(MF);
427 Offset -= AFI->getFramePtrSpillOffset();
430 unsigned Opcode = MI.getOpcode();
431 const TargetInstrDesc &Desc = MI.getDesc();
432 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
434 if (Opcode == ARM::tADDrSPi) {
435 Offset += MI.getOperand(i+1).getImm();
437 // Can't use tADDrSPi if it's based off the frame pointer.
438 unsigned NumBits = 0;
440 if (FrameReg != ARM::SP) {
441 Opcode = ARM::tADDi3;
442 MI.setDesc(TII.get(Opcode));
447 assert((Offset & 3) == 0 &&
448 "Thumb add/sub sp, #imm immediate must be multiple of 4!");
452 // Turn it into a move.
453 MI.setDesc(TII.get(ARM::tMOVgpr2tgpr));
454 MI.getOperand(i).ChangeToRegister(FrameReg, false);
455 MI.RemoveOperand(i+1);
459 // Common case: small offset, fits into instruction.
460 unsigned Mask = (1 << NumBits) - 1;
461 if (((Offset / Scale) & ~Mask) == 0) {
462 // Replace the FrameIndex with sp / fp
463 if (Opcode == ARM::tADDi3) {
464 removeOperands(MI, i);
465 MachineInstrBuilder MIB(&MI);
466 AddDefaultPred(AddDefaultT1CC(MIB).addReg(FrameReg)
467 .addImm(Offset / Scale));
469 MI.getOperand(i).ChangeToRegister(FrameReg, false);
470 MI.getOperand(i+1).ChangeToImmediate(Offset / Scale);
475 unsigned DestReg = MI.getOperand(0).getReg();
476 unsigned Bytes = (Offset > 0) ? Offset : -Offset;
477 unsigned NumMIs = calcNumMI(Opcode, 0, Bytes, NumBits, Scale);
478 // MI would expand into a large number of instructions. Don't try to
479 // simplify the immediate.
481 emitThumbRegPlusImmediate(MBB, II, DestReg, FrameReg, Offset, TII,
488 // Translate r0 = add sp, imm to
489 // r0 = add sp, 255*4
490 // r0 = add r0, (imm - 255*4)
491 if (Opcode == ARM::tADDi3) {
492 removeOperands(MI, i);
493 MachineInstrBuilder MIB(&MI);
494 AddDefaultPred(AddDefaultT1CC(MIB).addReg(FrameReg).addImm(Mask));
496 MI.getOperand(i).ChangeToRegister(FrameReg, false);
497 MI.getOperand(i+1).ChangeToImmediate(Mask);
499 Offset = (Offset - Mask * Scale);
500 MachineBasicBlock::iterator NII = next(II);
501 emitThumbRegPlusImmediate(MBB, NII, DestReg, DestReg, Offset, TII,
504 // Translate r0 = add sp, -imm to
505 // r0 = -imm (this is then translated into a series of instructons)
507 emitThumbConstant(MBB, II, DestReg, Offset, TII, *this, dl);
509 MI.setDesc(TII.get(ARM::tADDhirr));
510 MI.getOperand(i).ChangeToRegister(DestReg, false, false, true);
511 MI.getOperand(i+1).ChangeToRegister(FrameReg, false);
512 if (Opcode == ARM::tADDi3) {
513 MachineInstrBuilder MIB(&MI);
521 unsigned NumBits = 0;
524 case ARMII::AddrModeT1_s: {
526 InstrOffs = MI.getOperand(ImmIdx).getImm();
527 NumBits = (FrameReg == ARM::SP) ? 8 : 5;
532 llvm_unreachable("Unsupported addressing mode!");
536 Offset += InstrOffs * Scale;
537 assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
539 // Common case: small offset, fits into instruction.
540 MachineOperand &ImmOp = MI.getOperand(ImmIdx);
541 int ImmedOffset = Offset / Scale;
542 unsigned Mask = (1 << NumBits) - 1;
543 if ((unsigned)Offset <= Mask * Scale) {
544 // Replace the FrameIndex with sp
545 MI.getOperand(i).ChangeToRegister(FrameReg, false);
546 ImmOp.ChangeToImmediate(ImmedOffset);
550 bool isThumSpillRestore = Opcode == ARM::tRestore || Opcode == ARM::tSpill;
551 if (AddrMode == ARMII::AddrModeT1_s) {
552 // Thumb tLDRspi, tSTRspi. These will change to instructions that use
553 // a different base register.
555 Mask = (1 << NumBits) - 1;
557 // If this is a thumb spill / restore, we will be using a constpool load to
558 // materialize the offset.
559 if (AddrMode == ARMII::AddrModeT1_s && isThumSpillRestore)
560 ImmOp.ChangeToImmediate(0);
562 // Otherwise, it didn't fit. Pull in what we can to simplify the immed.
563 ImmedOffset = ImmedOffset & Mask;
564 ImmOp.ChangeToImmediate(ImmedOffset);
565 Offset &= ~(Mask*Scale);
569 // If we get here, the immediate doesn't fit into the instruction. We folded
570 // as much as possible above, handle the rest, providing a register that is
572 assert(Offset && "This code isn't needed if offset already handled!");
574 // Remove predicate first.
575 int PIdx = MI.findFirstPredOperandIdx();
577 removeOperands(MI, PIdx);
579 if (Desc.mayLoad()) {
580 // Use the destination register to materialize sp + offset.
581 unsigned TmpReg = MI.getOperand(0).getReg();
583 if (Opcode == ARM::tRestore) {
584 if (FrameReg == ARM::SP)
585 emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,
586 Offset, false, TII, *this, dl);
588 emitLoadConstPool(MBB, II, dl, TmpReg, 0, Offset);
592 emitThumbRegPlusImmediate(MBB, II, TmpReg, FrameReg, Offset, TII,
596 MI.setDesc(TII.get(ARM::tLDR));
597 MI.getOperand(i).ChangeToRegister(TmpReg, false, false, true);
599 // Use [reg, reg] addrmode.
600 MI.addOperand(MachineOperand::CreateReg(FrameReg, false));
601 else // tLDR has an extra register operand.
602 MI.addOperand(MachineOperand::CreateReg(0, false));
603 } else if (Desc.mayStore()) {
604 // FIXME! This is horrific!!! We need register scavenging.
605 // Our temporary workaround has marked r3 unavailable. Of course, r3 is
606 // also a ABI register so it's possible that is is the register that is
607 // being storing here. If that's the case, we do the following:
609 // Use r2 to materialize sp + offset
612 unsigned ValReg = MI.getOperand(0).getReg();
613 unsigned TmpReg = ARM::R3;
615 if (ValReg == ARM::R3) {
616 BuildMI(MBB, II, dl, TII.get(ARM::tMOVtgpr2gpr), ARM::R12)
617 .addReg(ARM::R2, RegState::Kill);
620 if (TmpReg == ARM::R3 && AFI->isR3LiveIn())
621 BuildMI(MBB, II, dl, TII.get(ARM::tMOVtgpr2gpr), ARM::R12)
622 .addReg(ARM::R3, RegState::Kill);
623 if (Opcode == ARM::tSpill) {
624 if (FrameReg == ARM::SP)
625 emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,
626 Offset, false, TII, *this, dl);
628 emitLoadConstPool(MBB, II, dl, TmpReg, 0, Offset);
632 emitThumbRegPlusImmediate(MBB, II, TmpReg, FrameReg, Offset, TII,
634 MI.setDesc(TII.get(ARM::tSTR));
635 MI.getOperand(i).ChangeToRegister(TmpReg, false, false, true);
636 if (UseRR) // Use [reg, reg] addrmode.
637 MI.addOperand(MachineOperand::CreateReg(FrameReg, false));
638 else // tSTR has an extra register operand.
639 MI.addOperand(MachineOperand::CreateReg(0, false));
641 MachineBasicBlock::iterator NII = next(II);
642 if (ValReg == ARM::R3)
643 BuildMI(MBB, NII, dl, TII.get(ARM::tMOVgpr2tgpr), ARM::R2)
644 .addReg(ARM::R12, RegState::Kill);
645 if (TmpReg == ARM::R3 && AFI->isR3LiveIn())
646 BuildMI(MBB, NII, dl, TII.get(ARM::tMOVgpr2tgpr), ARM::R3)
647 .addReg(ARM::R12, RegState::Kill);
649 assert(false && "Unexpected opcode!");
651 // Add predicate back if it's needed.
652 if (MI.getDesc().isPredicable()) {
653 MachineInstrBuilder MIB(&MI);
658 void Thumb1RegisterInfo::emitPrologue(MachineFunction &MF) const {
659 MachineBasicBlock &MBB = MF.front();
660 MachineBasicBlock::iterator MBBI = MBB.begin();
661 MachineFrameInfo *MFI = MF.getFrameInfo();
662 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
663 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
664 unsigned NumBytes = MFI->getStackSize();
665 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
666 DebugLoc dl = (MBBI != MBB.end() ?
667 MBBI->getDebugLoc() : DebugLoc::getUnknownLoc());
669 // Check if R3 is live in. It might have to be used as a scratch register.
670 for (MachineRegisterInfo::livein_iterator I =MF.getRegInfo().livein_begin(),
671 E = MF.getRegInfo().livein_end(); I != E; ++I) {
672 if (I->first == ARM::R3) {
673 AFI->setR3IsLiveIn(true);
678 // Thumb add/sub sp, imm8 instructions implicitly multiply the offset by 4.
679 NumBytes = (NumBytes + 3) & ~3;
680 MFI->setStackSize(NumBytes);
682 // Determine the sizes of each callee-save spill areas and record which frame
683 // belongs to which callee-save spill areas.
684 unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
685 int FramePtrSpillFI = 0;
688 emitSPUpdate(MBB, MBBI, TII, dl, *this, -VARegSaveSize);
690 if (!AFI->hasStackFrame()) {
692 emitSPUpdate(MBB, MBBI, TII, dl, *this, -NumBytes);
696 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
697 unsigned Reg = CSI[i].getReg();
698 int FI = CSI[i].getFrameIdx();
706 FramePtrSpillFI = FI;
707 AFI->addGPRCalleeSavedArea1Frame(FI);
715 FramePtrSpillFI = FI;
716 if (STI.isTargetDarwin()) {
717 AFI->addGPRCalleeSavedArea2Frame(FI);
720 AFI->addGPRCalleeSavedArea1Frame(FI);
725 AFI->addDPRCalleeSavedAreaFrame(FI);
730 if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPUSH) {
732 if (MBBI != MBB.end())
733 dl = MBBI->getDebugLoc();
736 // Darwin ABI requires FP to point to the stack slot that contains the
738 if (STI.isTargetDarwin() || hasFP(MF)) {
739 MachineInstrBuilder MIB =
740 BuildMI(MBB, MBBI, dl, TII.get(ARM::tADDrSPi), FramePtr)
741 .addFrameIndex(FramePtrSpillFI).addImm(0);
744 // Determine starting offsets of spill areas.
745 unsigned DPRCSOffset = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize);
746 unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize;
747 unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size;
748 AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) + NumBytes);
749 AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
750 AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
751 AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
753 NumBytes = DPRCSOffset;
755 // Insert it after all the callee-save spills.
756 emitSPUpdate(MBB, MBBI, TII, dl, *this, -NumBytes);
759 if (STI.isTargetELF() && hasFP(MF)) {
760 MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() -
761 AFI->getFramePtrSpillOffset());
764 AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
765 AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
766 AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
769 static bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) {
770 for (unsigned i = 0; CSRegs[i]; ++i)
771 if (Reg == CSRegs[i])
776 static bool isCSRestore(MachineInstr *MI, const unsigned *CSRegs) {
777 return (MI->getOpcode() == ARM::tRestore &&
778 MI->getOperand(1).isFI() &&
779 isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs));
782 void Thumb1RegisterInfo::emitEpilogue(MachineFunction &MF,
783 MachineBasicBlock &MBB) const {
784 MachineBasicBlock::iterator MBBI = prior(MBB.end());
785 assert((MBBI->getOpcode() == ARM::tBX_RET ||
786 MBBI->getOpcode() == ARM::tPOP_RET) &&
787 "Can only insert epilog into returning blocks");
788 DebugLoc dl = MBBI->getDebugLoc();
789 MachineFrameInfo *MFI = MF.getFrameInfo();
790 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
791 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
792 int NumBytes = (int)MFI->getStackSize();
794 if (!AFI->hasStackFrame()) {
796 emitSPUpdate(MBB, MBBI, TII, dl, *this, NumBytes);
798 // Unwind MBBI to point to first LDR / FLDD.
799 const unsigned *CSRegs = getCalleeSavedRegs();
800 if (MBBI != MBB.begin()) {
803 while (MBBI != MBB.begin() && isCSRestore(MBBI, CSRegs));
804 if (!isCSRestore(MBBI, CSRegs))
808 // Move SP to start of FP callee save spill area.
809 NumBytes -= (AFI->getGPRCalleeSavedArea1Size() +
810 AFI->getGPRCalleeSavedArea2Size() +
811 AFI->getDPRCalleeSavedAreaSize());
814 NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
815 // Reset SP based on frame pointer only if the stack frame extends beyond
816 // frame pointer stack slot or target is ELF and the function has FP.
818 emitThumbRegPlusImmediate(MBB, MBBI, ARM::SP, FramePtr, -NumBytes,
821 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVtgpr2gpr), ARM::SP)
824 if (MBBI->getOpcode() == ARM::tBX_RET &&
825 &MBB.front() != MBBI &&
826 prior(MBBI)->getOpcode() == ARM::tPOP) {
827 MachineBasicBlock::iterator PMBBI = prior(MBBI);
828 emitSPUpdate(MBB, PMBBI, TII, dl, *this, NumBytes);
830 emitSPUpdate(MBB, MBBI, TII, dl, *this, NumBytes);
835 // Epilogue for vararg functions: pop LR to R3 and branch off it.
836 // FIXME: Verify this is still ok when R3 is no longer being reserved.
837 BuildMI(MBB, MBBI, dl, TII.get(ARM::tPOP)).addReg(ARM::R3);
839 emitSPUpdate(MBB, MBBI, TII, dl, *this, VARegSaveSize);
841 BuildMI(MBB, MBBI, dl, TII.get(ARM::tBX_RET_vararg)).addReg(ARM::R3);