1 //===- Thumb1RegisterInfo.cpp - Thumb-1 Register Information ----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Thumb-1 implementation of the TargetRegisterInfo
13 //===----------------------------------------------------------------------===//
16 #include "ARMAddressingModes.h"
17 #include "ARMBaseInstrInfo.h"
18 #include "ARMMachineFunctionInfo.h"
19 #include "ARMSubtarget.h"
20 #include "Thumb1InstrInfo.h"
21 #include "Thumb1RegisterInfo.h"
22 #include "llvm/Constants.h"
23 #include "llvm/DerivedTypes.h"
24 #include "llvm/Function.h"
25 #include "llvm/LLVMContext.h"
26 #include "llvm/CodeGen/MachineConstantPool.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineLocation.h"
31 #include "llvm/CodeGen/MachineRegisterInfo.h"
32 #include "llvm/Target/TargetFrameInfo.h"
33 #include "llvm/Target/TargetMachine.h"
34 #include "llvm/ADT/BitVector.h"
35 #include "llvm/ADT/SmallVector.h"
36 #include "llvm/Support/CommandLine.h"
37 #include "llvm/Support/ErrorHandling.h"
38 #include "llvm/Support/raw_ostream.h"
41 extern cl::opt<bool> ReuseFrameIndexVals;
46 Thumb1RegisterInfo::Thumb1RegisterInfo(const ARMBaseInstrInfo &tii,
47 const ARMSubtarget &sti)
48 : ARMBaseRegisterInfo(tii, sti) {
51 /// emitLoadConstPool - Emits a load from constpool to materialize the
52 /// specified immediate.
53 void Thumb1RegisterInfo::emitLoadConstPool(MachineBasicBlock &MBB,
54 MachineBasicBlock::iterator &MBBI,
56 unsigned DestReg, unsigned SubIdx,
58 ARMCC::CondCodes Pred,
59 unsigned PredReg) const {
60 MachineFunction &MF = *MBB.getParent();
61 MachineConstantPool *ConstantPool = MF.getConstantPool();
62 const Constant *C = ConstantInt::get(
63 Type::getInt32Ty(MBB.getParent()->getFunction()->getContext()), Val);
64 unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
66 BuildMI(MBB, MBBI, dl, TII.get(ARM::tLDRcp))
67 .addReg(DestReg, getDefRegState(true), SubIdx)
68 .addConstantPoolIndex(Idx).addImm(Pred).addReg(PredReg);
71 bool Thumb1RegisterInfo::hasReservedCallFrame(const MachineFunction &MF) const {
72 const MachineFrameInfo *FFI = MF.getFrameInfo();
73 unsigned CFSize = FFI->getMaxCallFrameSize();
74 // It's not always a good idea to include the call frame as part of the
75 // stack frame. ARM (especially Thumb) has small immediate offset to
76 // address the stack frame. So a large call frame can cause poor codegen
77 // and may even makes it impossible to scavenge a register.
78 if (CFSize >= ((1 << 8) - 1) * 4 / 2) // Half of imm8 * 4
81 return !MF.getFrameInfo()->hasVarSizedObjects();
85 /// emitThumbRegPlusImmInReg - Emits a series of instructions to materialize
86 /// a destreg = basereg + immediate in Thumb code. Materialize the immediate
87 /// in a register using mov / mvn sequences or load the immediate from a
90 void emitThumbRegPlusImmInReg(MachineBasicBlock &MBB,
91 MachineBasicBlock::iterator &MBBI,
92 unsigned DestReg, unsigned BaseReg,
93 int NumBytes, bool CanChangeCC,
94 const TargetInstrInfo &TII,
95 const Thumb1RegisterInfo& MRI,
97 MachineFunction &MF = *MBB.getParent();
98 bool isHigh = !isARMLowRegister(DestReg) ||
99 (BaseReg != 0 && !isARMLowRegister(BaseReg));
101 // Subtract doesn't have high register version. Load the negative value
102 // if either base or dest register is a high register. Also, if do not
103 // issue sub as part of the sequence if condition register is to be
105 if (NumBytes < 0 && !isHigh && CanChangeCC) {
107 NumBytes = -NumBytes;
109 unsigned LdReg = DestReg;
110 if (DestReg == ARM::SP) {
111 assert(BaseReg == ARM::SP && "Unexpected!");
112 LdReg = MF.getRegInfo().createVirtualRegister(ARM::tGPRRegisterClass);
115 if (NumBytes <= 255 && NumBytes >= 0)
116 AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), LdReg))
118 else if (NumBytes < 0 && NumBytes >= -255) {
119 AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), LdReg))
121 AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tRSB), LdReg))
122 .addReg(LdReg, RegState::Kill);
124 MRI.emitLoadConstPool(MBB, MBBI, dl, LdReg, 0, NumBytes);
127 int Opc = (isSub) ? ARM::tSUBrr : (isHigh ? ARM::tADDhirr : ARM::tADDrr);
128 MachineInstrBuilder MIB =
129 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg);
130 if (Opc != ARM::tADDhirr)
131 MIB = AddDefaultT1CC(MIB);
132 if (DestReg == ARM::SP || isSub)
133 MIB.addReg(BaseReg).addReg(LdReg, RegState::Kill);
135 MIB.addReg(LdReg).addReg(BaseReg, RegState::Kill);
139 /// calcNumMI - Returns the number of instructions required to materialize
140 /// the specific add / sub r, c instruction.
141 static unsigned calcNumMI(int Opc, int ExtraOpc, unsigned Bytes,
142 unsigned NumBits, unsigned Scale) {
144 unsigned Chunk = ((1 << NumBits) - 1) * Scale;
146 if (Opc == ARM::tADDrSPi) {
147 unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes;
151 Scale = 1; // Followed by a number of tADDi8.
152 Chunk = ((1 << NumBits) - 1) * Scale;
155 NumMIs += Bytes / Chunk;
156 if ((Bytes % Chunk) != 0)
163 /// emitThumbRegPlusImmediate - Emits a series of instructions to materialize
164 /// a destreg = basereg + immediate in Thumb code.
166 void emitThumbRegPlusImmediate(MachineBasicBlock &MBB,
167 MachineBasicBlock::iterator &MBBI,
168 unsigned DestReg, unsigned BaseReg,
169 int NumBytes, const TargetInstrInfo &TII,
170 const Thumb1RegisterInfo& MRI,
172 bool isSub = NumBytes < 0;
173 unsigned Bytes = (unsigned)NumBytes;
174 if (isSub) Bytes = -NumBytes;
175 bool isMul4 = (Bytes & 3) == 0;
176 bool isTwoAddr = false;
177 bool DstNotEqBase = false;
178 unsigned NumBits = 1;
183 bool NeedPred = false;
185 if (DestReg == BaseReg && BaseReg == ARM::SP) {
186 assert(isMul4 && "Thumb sp inc / dec size must be multiple of 4!");
189 Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
191 } else if (!isSub && BaseReg == ARM::SP) {
194 // r1 = add sp, 100 * 4
198 ExtraOpc = ARM::tADDi3;
207 if (DestReg != BaseReg)
210 if (DestReg == ARM::SP) {
211 Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
212 assert(isMul4 && "Thumb sp inc / dec size must be multiple of 4!");
216 Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8;
218 NeedPred = NeedCC = true;
223 unsigned NumMIs = calcNumMI(Opc, ExtraOpc, Bytes, NumBits, Scale);
224 unsigned Threshold = (DestReg == ARM::SP) ? 3 : 2;
225 if (NumMIs > Threshold) {
226 // This will expand into too many instructions. Load the immediate from a
228 emitThumbRegPlusImmInReg(MBB, MBBI, DestReg, BaseReg, NumBytes, true, TII,
234 if (isARMLowRegister(DestReg) && isARMLowRegister(BaseReg)) {
235 // If both are low registers, emit DestReg = add BaseReg, max(Imm, 7)
236 unsigned Chunk = (1 << 3) - 1;
237 unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes;
239 const TargetInstrDesc &TID = TII.get(isSub ? ARM::tSUBi3 : ARM::tADDi3);
240 const MachineInstrBuilder MIB =
241 AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TID, DestReg));
242 AddDefaultPred(MIB.addReg(BaseReg, RegState::Kill).addImm(ThisVal));
244 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), DestReg)
245 .addReg(BaseReg, RegState::Kill);
250 unsigned Chunk = ((1 << NumBits) - 1) * Scale;
252 unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes;
255 // Build the new tADD / tSUB.
257 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg);
259 MIB = AddDefaultT1CC(MIB);
260 MIB .addReg(DestReg).addImm(ThisVal);
262 MIB = AddDefaultPred(MIB);
265 bool isKill = BaseReg != ARM::SP;
266 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg);
268 MIB = AddDefaultT1CC(MIB);
269 MIB.addReg(BaseReg, getKillRegState(isKill)).addImm(ThisVal);
271 MIB = AddDefaultPred(MIB);
274 if (Opc == ARM::tADDrSPi) {
280 Chunk = ((1 << NumBits) - 1) * Scale;
281 Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8;
282 NeedPred = NeedCC = isTwoAddr = true;
288 const TargetInstrDesc &TID = TII.get(ExtraOpc);
289 AddDefaultPred(AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TID, DestReg))
290 .addReg(DestReg, RegState::Kill)
291 .addImm(((unsigned)NumBytes) & 3));
295 static void emitSPUpdate(MachineBasicBlock &MBB,
296 MachineBasicBlock::iterator &MBBI,
297 const TargetInstrInfo &TII, DebugLoc dl,
298 const Thumb1RegisterInfo &MRI,
300 emitThumbRegPlusImmediate(MBB, MBBI, ARM::SP, ARM::SP, NumBytes, TII,
304 void Thumb1RegisterInfo::
305 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
306 MachineBasicBlock::iterator I) const {
307 if (!hasReservedCallFrame(MF)) {
308 // If we have alloca, convert as follows:
309 // ADJCALLSTACKDOWN -> sub, sp, sp, amount
310 // ADJCALLSTACKUP -> add, sp, sp, amount
311 MachineInstr *Old = I;
312 DebugLoc dl = Old->getDebugLoc();
313 unsigned Amount = Old->getOperand(0).getImm();
315 // We need to keep the stack aligned properly. To do this, we round the
316 // amount of space needed for the outgoing arguments up to the next
317 // alignment boundary.
318 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
319 Amount = (Amount+Align-1)/Align*Align;
321 // Replace the pseudo instruction with a new instruction...
322 unsigned Opc = Old->getOpcode();
323 if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
324 emitSPUpdate(MBB, I, TII, dl, *this, -Amount);
326 assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
327 emitSPUpdate(MBB, I, TII, dl, *this, Amount);
334 /// emitThumbConstant - Emit a series of instructions to materialize a
336 static void emitThumbConstant(MachineBasicBlock &MBB,
337 MachineBasicBlock::iterator &MBBI,
338 unsigned DestReg, int Imm,
339 const TargetInstrInfo &TII,
340 const Thumb1RegisterInfo& MRI,
342 bool isSub = Imm < 0;
343 if (isSub) Imm = -Imm;
345 int Chunk = (1 << 8) - 1;
346 int ThisVal = (Imm > Chunk) ? Chunk : Imm;
348 AddDefaultPred(AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8),
352 emitThumbRegPlusImmediate(MBB, MBBI, DestReg, DestReg, Imm, TII, MRI, dl);
354 const TargetInstrDesc &TID = TII.get(ARM::tRSB);
355 AddDefaultPred(AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TID, DestReg))
356 .addReg(DestReg, RegState::Kill));
360 static void removeOperands(MachineInstr &MI, unsigned i) {
362 for (unsigned e = MI.getNumOperands(); i != e; ++i)
363 MI.RemoveOperand(Op);
366 bool Thumb1RegisterInfo::
367 rewriteFrameIndex(MachineBasicBlock::iterator II, unsigned FrameRegIdx,
368 unsigned FrameReg, int &Offset,
369 const ARMBaseInstrInfo &TII) const {
370 MachineInstr &MI = *II;
371 MachineBasicBlock &MBB = *MI.getParent();
372 DebugLoc dl = MI.getDebugLoc();
373 unsigned Opcode = MI.getOpcode();
374 const TargetInstrDesc &Desc = MI.getDesc();
375 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
377 if (Opcode == ARM::tADDrSPi) {
378 Offset += MI.getOperand(FrameRegIdx+1).getImm();
380 // Can't use tADDrSPi if it's based off the frame pointer.
381 unsigned NumBits = 0;
383 if (FrameReg != ARM::SP) {
384 Opcode = ARM::tADDi3;
385 MI.setDesc(TII.get(Opcode));
390 assert((Offset & 3) == 0 &&
391 "Thumb add/sub sp, #imm immediate must be multiple of 4!");
395 if (Offset == 0 && getInstrPredicate(&MI, PredReg) == ARMCC::AL) {
396 // Turn it into a move.
397 MI.setDesc(TII.get(ARM::tMOVgpr2tgpr));
398 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
399 // Remove offset and remaining explicit predicate operands.
400 do MI.RemoveOperand(FrameRegIdx+1);
401 while (MI.getNumOperands() > FrameRegIdx+1 &&
402 (!MI.getOperand(FrameRegIdx+1).isReg() ||
403 !MI.getOperand(FrameRegIdx+1).isImm()));
407 // Common case: small offset, fits into instruction.
408 unsigned Mask = (1 << NumBits) - 1;
409 if (((Offset / Scale) & ~Mask) == 0) {
410 // Replace the FrameIndex with sp / fp
411 if (Opcode == ARM::tADDi3) {
412 removeOperands(MI, FrameRegIdx);
413 MachineInstrBuilder MIB(&MI);
414 AddDefaultPred(AddDefaultT1CC(MIB).addReg(FrameReg)
415 .addImm(Offset / Scale));
417 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
418 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset / Scale);
423 unsigned DestReg = MI.getOperand(0).getReg();
424 unsigned Bytes = (Offset > 0) ? Offset : -Offset;
425 unsigned NumMIs = calcNumMI(Opcode, 0, Bytes, NumBits, Scale);
426 // MI would expand into a large number of instructions. Don't try to
427 // simplify the immediate.
429 emitThumbRegPlusImmediate(MBB, II, DestReg, FrameReg, Offset, TII,
436 // Translate r0 = add sp, imm to
437 // r0 = add sp, 255*4
438 // r0 = add r0, (imm - 255*4)
439 if (Opcode == ARM::tADDi3) {
440 removeOperands(MI, FrameRegIdx);
441 MachineInstrBuilder MIB(&MI);
442 AddDefaultPred(AddDefaultT1CC(MIB).addReg(FrameReg).addImm(Mask));
444 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
445 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Mask);
447 Offset = (Offset - Mask * Scale);
448 MachineBasicBlock::iterator NII = llvm::next(II);
449 emitThumbRegPlusImmediate(MBB, NII, DestReg, DestReg, Offset, TII,
452 // Translate r0 = add sp, -imm to
453 // r0 = -imm (this is then translated into a series of instructons)
455 emitThumbConstant(MBB, II, DestReg, Offset, TII, *this, dl);
457 MI.setDesc(TII.get(ARM::tADDhirr));
458 MI.getOperand(FrameRegIdx).ChangeToRegister(DestReg, false, false, true);
459 MI.getOperand(FrameRegIdx+1).ChangeToRegister(FrameReg, false);
460 if (Opcode == ARM::tADDi3) {
461 MachineInstrBuilder MIB(&MI);
469 unsigned NumBits = 0;
472 case ARMII::AddrModeT1_s: {
473 ImmIdx = FrameRegIdx+1;
474 InstrOffs = MI.getOperand(ImmIdx).getImm();
475 NumBits = (FrameReg == ARM::SP) ? 8 : 5;
480 llvm_unreachable("Unsupported addressing mode!");
484 Offset += InstrOffs * Scale;
485 assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
487 // Common case: small offset, fits into instruction.
488 MachineOperand &ImmOp = MI.getOperand(ImmIdx);
489 int ImmedOffset = Offset / Scale;
490 unsigned Mask = (1 << NumBits) - 1;
491 if ((unsigned)Offset <= Mask * Scale) {
492 // Replace the FrameIndex with sp
493 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
494 ImmOp.ChangeToImmediate(ImmedOffset);
498 bool isThumSpillRestore = Opcode == ARM::tRestore || Opcode == ARM::tSpill;
499 if (AddrMode == ARMII::AddrModeT1_s) {
500 // Thumb tLDRspi, tSTRspi. These will change to instructions that use
501 // a different base register.
503 Mask = (1 << NumBits) - 1;
505 // If this is a thumb spill / restore, we will be using a constpool load to
506 // materialize the offset.
507 if (AddrMode == ARMII::AddrModeT1_s && isThumSpillRestore)
508 ImmOp.ChangeToImmediate(0);
510 // Otherwise, it didn't fit. Pull in what we can to simplify the immed.
511 ImmedOffset = ImmedOffset & Mask;
512 ImmOp.ChangeToImmediate(ImmedOffset);
513 Offset &= ~(Mask*Scale);
520 Thumb1RegisterInfo::resolveFrameIndex(MachineBasicBlock::iterator I,
521 unsigned BaseReg, int64_t Offset) const {
522 MachineInstr &MI = *I;
523 int Off = Offset; // ARM doesn't need the general 64-bit offsets
526 while (!MI.getOperand(i).isFI()) {
528 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
531 Done = rewriteFrameIndex(MI, i, BaseReg, Off, TII);
532 assert (Done && "Unable to resolve frame index!");
535 /// saveScavengerRegister - Spill the register so it can be used by the
536 /// register scavenger. Return true.
538 Thumb1RegisterInfo::saveScavengerRegister(MachineBasicBlock &MBB,
539 MachineBasicBlock::iterator I,
540 MachineBasicBlock::iterator &UseMI,
541 const TargetRegisterClass *RC,
542 unsigned Reg) const {
543 // Thumb1 can't use the emergency spill slot on the stack because
544 // ldr/str immediate offsets must be positive, and if we're referencing
545 // off the frame pointer (if, for example, there are alloca() calls in
546 // the function, the offset will be negative. Use R12 instead since that's
547 // a call clobbered register that we know won't be used in Thumb1 mode.
549 BuildMI(MBB, I, DL, TII.get(ARM::tMOVtgpr2gpr)).
550 addReg(ARM::R12, RegState::Define).addReg(Reg, RegState::Kill);
552 // The UseMI is where we would like to restore the register. If there's
553 // interference with R12 before then, however, we'll need to restore it
554 // before that instead and adjust the UseMI.
556 for (MachineBasicBlock::iterator II = I; !done && II != UseMI ; ++II) {
557 if (II->isDebugValue())
559 // If this instruction affects R12, adjust our restore point.
560 for (unsigned i = 0, e = II->getNumOperands(); i != e; ++i) {
561 const MachineOperand &MO = II->getOperand(i);
562 if (!MO.isReg() || MO.isUndef() || !MO.getReg() ||
563 TargetRegisterInfo::isVirtualRegister(MO.getReg()))
565 if (MO.getReg() == ARM::R12) {
572 // Restore the register from R12
573 BuildMI(MBB, UseMI, DL, TII.get(ARM::tMOVgpr2tgpr)).
574 addReg(Reg, RegState::Define).addReg(ARM::R12, RegState::Kill);
580 Thumb1RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
581 int SPAdj, FrameIndexValue *Value,
582 RegScavenger *RS) const{
585 MachineInstr &MI = *II;
586 MachineBasicBlock &MBB = *MI.getParent();
587 MachineFunction &MF = *MBB.getParent();
588 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
589 DebugLoc dl = MI.getDebugLoc();
591 while (!MI.getOperand(i).isFI()) {
593 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
596 unsigned FrameReg = ARM::SP;
597 int FrameIndex = MI.getOperand(i).getIndex();
598 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
599 MF.getFrameInfo()->getStackSize() + SPAdj;
601 if (AFI->isGPRCalleeSavedArea1Frame(FrameIndex))
602 Offset -= AFI->getGPRCalleeSavedArea1Offset();
603 else if (AFI->isGPRCalleeSavedArea2Frame(FrameIndex))
604 Offset -= AFI->getGPRCalleeSavedArea2Offset();
605 else if (MF.getFrameInfo()->hasVarSizedObjects()) {
606 assert(SPAdj == 0 && hasFP(MF) && "Unexpected");
607 // There are alloca()'s in this function, must reference off the frame
609 FrameReg = getFrameRegister(MF);
610 Offset -= AFI->getFramePtrSpillOffset();
613 // Special handling of dbg_value instructions.
614 if (MI.isDebugValue()) {
615 MI.getOperand(i). ChangeToRegister(FrameReg, false /*isDef*/);
616 MI.getOperand(i+1).ChangeToImmediate(Offset);
620 // Modify MI as necessary to handle as much of 'Offset' as possible
621 assert(AFI->isThumbFunction() &&
622 "This eliminateFrameIndex only supports Thumb1!");
623 if (rewriteFrameIndex(MI, i, FrameReg, Offset, TII))
626 // If we get here, the immediate doesn't fit into the instruction. We folded
627 // as much as possible above, handle the rest, providing a register that is
629 assert(Offset && "This code isn't needed if offset already handled!");
631 unsigned Opcode = MI.getOpcode();
632 const TargetInstrDesc &Desc = MI.getDesc();
634 // Remove predicate first.
635 int PIdx = MI.findFirstPredOperandIdx();
637 removeOperands(MI, PIdx);
639 if (Desc.mayLoad()) {
640 // Use the destination register to materialize sp + offset.
641 unsigned TmpReg = MI.getOperand(0).getReg();
643 if (Opcode == ARM::tRestore) {
644 if (FrameReg == ARM::SP)
645 emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,
646 Offset, false, TII, *this, dl);
648 emitLoadConstPool(MBB, II, dl, TmpReg, 0, Offset);
652 emitThumbRegPlusImmediate(MBB, II, TmpReg, FrameReg, Offset, TII,
656 MI.setDesc(TII.get(ARM::tLDR));
657 MI.getOperand(i).ChangeToRegister(TmpReg, false, false, true);
659 // Use [reg, reg] addrmode.
660 MI.addOperand(MachineOperand::CreateReg(FrameReg, false));
661 else // tLDR has an extra register operand.
662 MI.addOperand(MachineOperand::CreateReg(0, false));
663 } else if (Desc.mayStore()) {
664 VReg = MF.getRegInfo().createVirtualRegister(ARM::tGPRRegisterClass);
665 assert (Value && "Frame index virtual allocated, but Value arg is NULL!");
667 bool TrackVReg = true;
668 Value->first = FrameReg; // use the frame register as a kind indicator
669 Value->second = Offset;
671 if (Opcode == ARM::tSpill) {
672 if (FrameReg == ARM::SP)
673 emitThumbRegPlusImmInReg(MBB, II, VReg, FrameReg,
674 Offset, false, TII, *this, dl);
676 emitLoadConstPool(MBB, II, dl, VReg, 0, Offset);
681 emitThumbRegPlusImmediate(MBB, II, VReg, FrameReg, Offset, TII,
683 MI.setDesc(TII.get(ARM::tSTR));
684 MI.getOperand(i).ChangeToRegister(VReg, false, false, true);
685 if (UseRR) // Use [reg, reg] addrmode.
686 MI.addOperand(MachineOperand::CreateReg(FrameReg, false));
687 else // tSTR has an extra register operand.
688 MI.addOperand(MachineOperand::CreateReg(0, false));
689 if (!ReuseFrameIndexVals || !TrackVReg)
692 assert(false && "Unexpected opcode!");
694 // Add predicate back if it's needed.
695 if (MI.getDesc().isPredicable()) {
696 MachineInstrBuilder MIB(&MI);
702 void Thumb1RegisterInfo::emitPrologue(MachineFunction &MF) const {
703 MachineBasicBlock &MBB = MF.front();
704 MachineBasicBlock::iterator MBBI = MBB.begin();
705 MachineFrameInfo *MFI = MF.getFrameInfo();
706 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
707 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
708 unsigned NumBytes = MFI->getStackSize();
709 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
710 DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
712 // Thumb add/sub sp, imm8 instructions implicitly multiply the offset by 4.
713 NumBytes = (NumBytes + 3) & ~3;
714 MFI->setStackSize(NumBytes);
716 // Determine the sizes of each callee-save spill areas and record which frame
717 // belongs to which callee-save spill areas.
718 unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
719 int FramePtrSpillFI = 0;
722 emitSPUpdate(MBB, MBBI, TII, dl, *this, -VARegSaveSize);
724 if (!AFI->hasStackFrame()) {
726 emitSPUpdate(MBB, MBBI, TII, dl, *this, -NumBytes);
730 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
731 unsigned Reg = CSI[i].getReg();
732 int FI = CSI[i].getFrameIdx();
740 FramePtrSpillFI = FI;
741 AFI->addGPRCalleeSavedArea1Frame(FI);
749 FramePtrSpillFI = FI;
750 if (STI.isTargetDarwin()) {
751 AFI->addGPRCalleeSavedArea2Frame(FI);
754 AFI->addGPRCalleeSavedArea1Frame(FI);
759 AFI->addDPRCalleeSavedAreaFrame(FI);
764 if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPUSH) {
766 if (MBBI != MBB.end())
767 dl = MBBI->getDebugLoc();
770 // Adjust FP so it point to the stack slot that contains the previous FP.
772 BuildMI(MBB, MBBI, dl, TII.get(ARM::tADDrSPi), FramePtr)
773 .addFrameIndex(FramePtrSpillFI).addImm(0);
774 AFI->setShouldRestoreSPFromFP(true);
777 // Determine starting offsets of spill areas.
778 unsigned DPRCSOffset = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize);
779 unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize;
780 unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size;
781 AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) + NumBytes);
782 AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
783 AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
784 AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
786 NumBytes = DPRCSOffset;
788 // Insert it after all the callee-save spills.
789 emitSPUpdate(MBB, MBBI, TII, dl, *this, -NumBytes);
792 if (STI.isTargetELF() && hasFP(MF))
793 MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() -
794 AFI->getFramePtrSpillOffset());
796 AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
797 AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
798 AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
801 static bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) {
802 for (unsigned i = 0; CSRegs[i]; ++i)
803 if (Reg == CSRegs[i])
808 static bool isCSRestore(MachineInstr *MI, const unsigned *CSRegs) {
809 if (MI->getOpcode() == ARM::tRestore &&
810 MI->getOperand(1).isFI() &&
811 isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs))
813 else if (MI->getOpcode() == ARM::tPOP) {
814 // The first two operands are predicates. The last two are
815 // imp-def and imp-use of SP. Check everything in between.
816 for (int i = 2, e = MI->getNumOperands() - 2; i != e; ++i)
817 if (!isCalleeSavedRegister(MI->getOperand(i).getReg(), CSRegs))
824 void Thumb1RegisterInfo::emitEpilogue(MachineFunction &MF,
825 MachineBasicBlock &MBB) const {
826 MachineBasicBlock::iterator MBBI = prior(MBB.end());
827 assert((MBBI->getOpcode() == ARM::tBX_RET ||
828 MBBI->getOpcode() == ARM::tPOP_RET) &&
829 "Can only insert epilog into returning blocks");
830 DebugLoc dl = MBBI->getDebugLoc();
831 MachineFrameInfo *MFI = MF.getFrameInfo();
832 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
833 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
834 int NumBytes = (int)MFI->getStackSize();
835 const unsigned *CSRegs = getCalleeSavedRegs();
837 if (!AFI->hasStackFrame()) {
839 emitSPUpdate(MBB, MBBI, TII, dl, *this, NumBytes);
841 // Unwind MBBI to point to first LDR / VLDRD.
842 if (MBBI != MBB.begin()) {
845 while (MBBI != MBB.begin() && isCSRestore(MBBI, CSRegs));
846 if (!isCSRestore(MBBI, CSRegs))
850 // Move SP to start of FP callee save spill area.
851 NumBytes -= (AFI->getGPRCalleeSavedArea1Size() +
852 AFI->getGPRCalleeSavedArea2Size() +
853 AFI->getDPRCalleeSavedAreaSize());
855 if (AFI->shouldRestoreSPFromFP()) {
856 NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
857 // Reset SP based on frame pointer only if the stack frame extends beyond
858 // frame pointer stack slot or target is ELF and the function has FP.
860 emitThumbRegPlusImmediate(MBB, MBBI, ARM::SP, FramePtr, -NumBytes,
863 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVtgpr2gpr), ARM::SP)
866 if (MBBI->getOpcode() == ARM::tBX_RET &&
867 &MBB.front() != MBBI &&
868 prior(MBBI)->getOpcode() == ARM::tPOP) {
869 MachineBasicBlock::iterator PMBBI = prior(MBBI);
870 emitSPUpdate(MBB, PMBBI, TII, dl, *this, NumBytes);
872 emitSPUpdate(MBB, MBBI, TII, dl, *this, NumBytes);
877 // Unlike T2 and ARM mode, the T1 pop instruction cannot restore
878 // to LR, and we can't pop the value directly to the PC since
879 // we need to update the SP after popping the value. Therefore, we
880 // pop the old LR into R3 as a temporary.
882 // Move back past the callee-saved register restoration
883 while (MBBI != MBB.end() && isCSRestore(MBBI, CSRegs))
885 // Epilogue for vararg functions: pop LR to R3 and branch off it.
886 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tPOP)))
887 .addReg(ARM::R3, RegState::Define);
889 emitSPUpdate(MBB, MBBI, TII, dl, *this, VARegSaveSize);
891 BuildMI(MBB, MBBI, dl, TII.get(ARM::tBX_RET_vararg))
892 .addReg(ARM::R3, RegState::Kill);
893 // erase the old tBX_RET instruction