1 //===- Thumb1RegisterInfo.cpp - Thumb-1 Register Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Thumb-1 implementation of the TargetRegisterInfo class.
12 //===----------------------------------------------------------------------===//
15 #include "ARMAddressingModes.h"
16 #include "ARMBaseInstrInfo.h"
17 #include "ARMMachineFunctionInfo.h"
18 #include "ARMSubtarget.h"
19 #include "Thumb1InstrInfo.h"
20 #include "Thumb1RegisterInfo.h"
21 #include "llvm/Constants.h"
22 #include "llvm/DerivedTypes.h"
23 #include "llvm/Function.h"
24 #include "llvm/LLVMContext.h"
25 #include "llvm/CodeGen/MachineConstantPool.h"
26 #include "llvm/CodeGen/MachineFrameInfo.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineInstrBuilder.h"
29 #include "llvm/CodeGen/MachineLocation.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/Target/TargetFrameInfo.h"
32 #include "llvm/Target/TargetMachine.h"
33 #include "llvm/ADT/BitVector.h"
34 #include "llvm/ADT/SmallVector.h"
35 #include "llvm/Support/CommandLine.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Support/raw_ostream.h"
40 // FIXME: This cmd line option conditionalizes the new register scavenging
41 // implemenation in PEI. Remove the option when scavenging works well enough
43 extern cl::opt<bool> FrameIndexVirtualScavenging;
45 Thumb1RegisterInfo::Thumb1RegisterInfo(const ARMBaseInstrInfo &tii,
46 const ARMSubtarget &sti)
47 : ARMBaseRegisterInfo(tii, sti) {
50 /// emitLoadConstPool - Emits a load from constpool to materialize the
51 /// specified immediate.
52 void Thumb1RegisterInfo::emitLoadConstPool(MachineBasicBlock &MBB,
53 MachineBasicBlock::iterator &MBBI,
55 unsigned DestReg, unsigned SubIdx,
57 ARMCC::CondCodes Pred,
58 unsigned PredReg) const {
59 MachineFunction &MF = *MBB.getParent();
60 MachineConstantPool *ConstantPool = MF.getConstantPool();
61 Constant *C = ConstantInt::get(
62 Type::getInt32Ty(MBB.getParent()->getFunction()->getContext()), Val);
63 unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
65 BuildMI(MBB, MBBI, dl, TII.get(ARM::tLDRcp))
66 .addReg(DestReg, getDefRegState(true), SubIdx)
67 .addConstantPoolIndex(Idx).addImm(Pred).addReg(PredReg);
70 const TargetRegisterClass*
71 Thumb1RegisterInfo::getPhysicalRegisterRegClass(unsigned Reg, EVT VT) const {
72 if (isARMLowRegister(Reg))
73 return ARM::tGPRRegisterClass;
77 case ARM::R8: case ARM::R9: case ARM::R10: case ARM::R11:
78 case ARM::R12: case ARM::SP: case ARM::LR: case ARM::PC:
79 return ARM::GPRRegisterClass;
82 return TargetRegisterInfo::getPhysicalRegisterRegClass(Reg, VT);
86 Thumb1RegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const {
87 return FrameIndexVirtualScavenging;
90 bool Thumb1RegisterInfo::hasReservedCallFrame(MachineFunction &MF) const {
91 const MachineFrameInfo *FFI = MF.getFrameInfo();
92 unsigned CFSize = FFI->getMaxCallFrameSize();
93 // It's not always a good idea to include the call frame as part of the
94 // stack frame. ARM (especially Thumb) has small immediate offset to
95 // address the stack frame. So a large call frame can cause poor codegen
96 // and may even makes it impossible to scavenge a register.
97 if (CFSize >= ((1 << 8) - 1) * 4 / 2) // Half of imm8 * 4
100 return !MF.getFrameInfo()->hasVarSizedObjects();
104 /// emitThumbRegPlusImmInReg - Emits a series of instructions to materialize
105 /// a destreg = basereg + immediate in Thumb code. Materialize the immediate
106 /// in a register using mov / mvn sequences or load the immediate from a
109 void emitThumbRegPlusImmInReg(MachineBasicBlock &MBB,
110 MachineBasicBlock::iterator &MBBI,
111 unsigned DestReg, unsigned BaseReg,
112 int NumBytes, bool CanChangeCC,
113 const TargetInstrInfo &TII,
114 const Thumb1RegisterInfo& MRI,
116 MachineFunction &MF = *MBB.getParent();
117 bool isHigh = !isARMLowRegister(DestReg) ||
118 (BaseReg != 0 && !isARMLowRegister(BaseReg));
120 // Subtract doesn't have high register version. Load the negative value
121 // if either base or dest register is a high register. Also, if do not
122 // issue sub as part of the sequence if condition register is to be
124 if (NumBytes < 0 && !isHigh && CanChangeCC) {
126 NumBytes = -NumBytes;
128 unsigned LdReg = DestReg;
129 if (DestReg == ARM::SP) {
130 assert(BaseReg == ARM::SP && "Unexpected!");
131 if (FrameIndexVirtualScavenging) {
132 LdReg = MF.getRegInfo().createVirtualRegister(ARM::tGPRRegisterClass);
135 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVtgpr2gpr), ARM::R12)
136 .addReg(ARM::R3, RegState::Kill);
140 if (NumBytes <= 255 && NumBytes >= 0)
141 AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), LdReg))
143 else if (NumBytes < 0 && NumBytes >= -255) {
144 AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), LdReg))
146 AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tRSB), LdReg))
147 .addReg(LdReg, RegState::Kill);
149 MRI.emitLoadConstPool(MBB, MBBI, dl, LdReg, 0, NumBytes);
152 int Opc = (isSub) ? ARM::tSUBrr : (isHigh ? ARM::tADDhirr : ARM::tADDrr);
153 MachineInstrBuilder MIB =
154 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg);
155 if (Opc != ARM::tADDhirr)
156 MIB = AddDefaultT1CC(MIB);
157 if (DestReg == ARM::SP || isSub)
158 MIB.addReg(BaseReg).addReg(LdReg, RegState::Kill);
160 MIB.addReg(LdReg).addReg(BaseReg, RegState::Kill);
163 if (!FrameIndexVirtualScavenging && DestReg == ARM::SP)
164 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2tgpr), ARM::R3)
165 .addReg(ARM::R12, RegState::Kill);
168 /// calcNumMI - Returns the number of instructions required to materialize
169 /// the specific add / sub r, c instruction.
170 static unsigned calcNumMI(int Opc, int ExtraOpc, unsigned Bytes,
171 unsigned NumBits, unsigned Scale) {
173 unsigned Chunk = ((1 << NumBits) - 1) * Scale;
175 if (Opc == ARM::tADDrSPi) {
176 unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes;
180 Scale = 1; // Followed by a number of tADDi8.
181 Chunk = ((1 << NumBits) - 1) * Scale;
184 NumMIs += Bytes / Chunk;
185 if ((Bytes % Chunk) != 0)
192 /// emitThumbRegPlusImmediate - Emits a series of instructions to materialize
193 /// a destreg = basereg + immediate in Thumb code.
195 void emitThumbRegPlusImmediate(MachineBasicBlock &MBB,
196 MachineBasicBlock::iterator &MBBI,
197 unsigned DestReg, unsigned BaseReg,
198 int NumBytes, const TargetInstrInfo &TII,
199 const Thumb1RegisterInfo& MRI,
201 bool isSub = NumBytes < 0;
202 unsigned Bytes = (unsigned)NumBytes;
203 if (isSub) Bytes = -NumBytes;
204 bool isMul4 = (Bytes & 3) == 0;
205 bool isTwoAddr = false;
206 bool DstNotEqBase = false;
207 unsigned NumBits = 1;
212 bool NeedPred = false;
214 if (DestReg == BaseReg && BaseReg == ARM::SP) {
215 assert(isMul4 && "Thumb sp inc / dec size must be multiple of 4!");
218 Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
220 } else if (!isSub && BaseReg == ARM::SP) {
223 // r1 = add sp, 100 * 4
227 ExtraOpc = ARM::tADDi3;
236 if (DestReg != BaseReg)
239 if (DestReg == ARM::SP) {
240 Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
241 assert(isMul4 && "Thumb sp inc / dec size must be multiple of 4!");
245 Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8;
247 NeedPred = NeedCC = true;
252 unsigned NumMIs = calcNumMI(Opc, ExtraOpc, Bytes, NumBits, Scale);
253 unsigned Threshold = (DestReg == ARM::SP) ? 3 : 2;
254 if (NumMIs > Threshold) {
255 // This will expand into too many instructions. Load the immediate from a
257 emitThumbRegPlusImmInReg(MBB, MBBI, DestReg, BaseReg, NumBytes, true, TII,
263 if (isARMLowRegister(DestReg) && isARMLowRegister(BaseReg)) {
264 // If both are low registers, emit DestReg = add BaseReg, max(Imm, 7)
265 unsigned Chunk = (1 << 3) - 1;
266 unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes;
268 const TargetInstrDesc &TID = TII.get(isSub ? ARM::tSUBi3 : ARM::tADDi3);
269 const MachineInstrBuilder MIB =
270 AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TID, DestReg));
271 AddDefaultPred(MIB.addReg(BaseReg, RegState::Kill).addImm(ThisVal));
273 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), DestReg)
274 .addReg(BaseReg, RegState::Kill);
279 unsigned Chunk = ((1 << NumBits) - 1) * Scale;
281 unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes;
284 // Build the new tADD / tSUB.
286 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg);
288 MIB = AddDefaultT1CC(MIB);
289 MIB .addReg(DestReg).addImm(ThisVal);
291 MIB = AddDefaultPred(MIB);
294 bool isKill = BaseReg != ARM::SP;
295 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg);
297 MIB = AddDefaultT1CC(MIB);
298 MIB.addReg(BaseReg, getKillRegState(isKill)).addImm(ThisVal);
300 MIB = AddDefaultPred(MIB);
303 if (Opc == ARM::tADDrSPi) {
309 Chunk = ((1 << NumBits) - 1) * Scale;
310 Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8;
311 NeedPred = NeedCC = isTwoAddr = true;
317 const TargetInstrDesc &TID = TII.get(ExtraOpc);
318 AddDefaultPred(AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TID, DestReg))
319 .addReg(DestReg, RegState::Kill)
320 .addImm(((unsigned)NumBytes) & 3));
324 static void emitSPUpdate(MachineBasicBlock &MBB,
325 MachineBasicBlock::iterator &MBBI,
326 const TargetInstrInfo &TII, DebugLoc dl,
327 const Thumb1RegisterInfo &MRI,
329 emitThumbRegPlusImmediate(MBB, MBBI, ARM::SP, ARM::SP, NumBytes, TII,
333 void Thumb1RegisterInfo::
334 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
335 MachineBasicBlock::iterator I) const {
336 if (!hasReservedCallFrame(MF)) {
337 // If we have alloca, convert as follows:
338 // ADJCALLSTACKDOWN -> sub, sp, sp, amount
339 // ADJCALLSTACKUP -> add, sp, sp, amount
340 MachineInstr *Old = I;
341 DebugLoc dl = Old->getDebugLoc();
342 unsigned Amount = Old->getOperand(0).getImm();
344 // We need to keep the stack aligned properly. To do this, we round the
345 // amount of space needed for the outgoing arguments up to the next
346 // alignment boundary.
347 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
348 Amount = (Amount+Align-1)/Align*Align;
350 // Replace the pseudo instruction with a new instruction...
351 unsigned Opc = Old->getOpcode();
352 if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
353 emitSPUpdate(MBB, I, TII, dl, *this, -Amount);
355 assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
356 emitSPUpdate(MBB, I, TII, dl, *this, Amount);
363 /// emitThumbConstant - Emit a series of instructions to materialize a
365 static void emitThumbConstant(MachineBasicBlock &MBB,
366 MachineBasicBlock::iterator &MBBI,
367 unsigned DestReg, int Imm,
368 const TargetInstrInfo &TII,
369 const Thumb1RegisterInfo& MRI,
371 bool isSub = Imm < 0;
372 if (isSub) Imm = -Imm;
374 int Chunk = (1 << 8) - 1;
375 int ThisVal = (Imm > Chunk) ? Chunk : Imm;
377 AddDefaultPred(AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8),
381 emitThumbRegPlusImmediate(MBB, MBBI, DestReg, DestReg, Imm, TII, MRI, dl);
383 const TargetInstrDesc &TID = TII.get(ARM::tRSB);
384 AddDefaultPred(AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TID, DestReg))
385 .addReg(DestReg, RegState::Kill));
389 static void removeOperands(MachineInstr &MI, unsigned i) {
391 for (unsigned e = MI.getNumOperands(); i != e; ++i)
392 MI.RemoveOperand(Op);
395 int Thumb1RegisterInfo::
396 rewriteFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
397 unsigned FrameReg, int Offset,
398 unsigned MOVOpc, unsigned ADDriOpc, unsigned SUBriOpc) const
400 // if/when eliminateFrameIndex() conforms with ARMBaseRegisterInfo
401 // version then can pull out Thumb1 specific parts here
405 /// saveScavengerRegister - Save the register so it can be used by the
406 /// register scavenger. Return true.
407 bool Thumb1RegisterInfo::saveScavengerRegister(MachineBasicBlock &MBB,
408 MachineBasicBlock::iterator I,
409 const TargetRegisterClass *RC,
410 unsigned Reg) const {
411 // Thumb1 can't use the emergency spill slot on the stack because
412 // ldr/str immediate offsets must be positive, and if we're referencing
413 // off the frame pointer (if, for example, there are alloca() calls in
414 // the function, the offset will be negative. Use R12 instead since that's
415 // a call clobbered register that we know won't be used in Thumb1 mode.
417 TII.copyRegToReg(MBB, I, ARM::R12, Reg, ARM::GPRRegisterClass, RC);
421 /// restoreScavengerRegister - restore a registers saved by
422 // saveScavengerRegister().
423 void Thumb1RegisterInfo::restoreScavengerRegister(MachineBasicBlock &MBB,
424 MachineBasicBlock::iterator I,
425 const TargetRegisterClass *RC,
426 unsigned Reg) const {
427 TII.copyRegToReg(MBB, I, Reg, ARM::R12, RC, ARM::GPRRegisterClass);
431 Thumb1RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
432 int SPAdj, int *Value,
433 RegScavenger *RS) const{
436 MachineInstr &MI = *II;
437 MachineBasicBlock &MBB = *MI.getParent();
438 MachineFunction &MF = *MBB.getParent();
439 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
440 DebugLoc dl = MI.getDebugLoc();
442 while (!MI.getOperand(i).isFI()) {
444 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
447 unsigned FrameReg = ARM::SP;
448 int FrameIndex = MI.getOperand(i).getIndex();
449 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
450 MF.getFrameInfo()->getStackSize() + SPAdj;
452 if (AFI->isGPRCalleeSavedArea1Frame(FrameIndex))
453 Offset -= AFI->getGPRCalleeSavedArea1Offset();
454 else if (AFI->isGPRCalleeSavedArea2Frame(FrameIndex))
455 Offset -= AFI->getGPRCalleeSavedArea2Offset();
456 else if (hasFP(MF)) {
457 assert(SPAdj == 0 && "Unexpected");
458 // There is alloca()'s in this function, must reference off the frame
460 FrameReg = getFrameRegister(MF);
461 Offset -= AFI->getFramePtrSpillOffset();
464 unsigned Opcode = MI.getOpcode();
465 const TargetInstrDesc &Desc = MI.getDesc();
466 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
468 if (Opcode == ARM::tADDrSPi) {
469 Offset += MI.getOperand(i+1).getImm();
471 // Can't use tADDrSPi if it's based off the frame pointer.
472 unsigned NumBits = 0;
474 if (FrameReg != ARM::SP) {
475 Opcode = ARM::tADDi3;
476 MI.setDesc(TII.get(Opcode));
481 assert((Offset & 3) == 0 &&
482 "Thumb add/sub sp, #imm immediate must be multiple of 4!");
486 // Turn it into a move.
487 MI.setDesc(TII.get(ARM::tMOVgpr2tgpr));
488 MI.getOperand(i).ChangeToRegister(FrameReg, false);
489 MI.RemoveOperand(i+1);
493 // Common case: small offset, fits into instruction.
494 unsigned Mask = (1 << NumBits) - 1;
495 if (((Offset / Scale) & ~Mask) == 0) {
496 // Replace the FrameIndex with sp / fp
497 if (Opcode == ARM::tADDi3) {
498 removeOperands(MI, i);
499 MachineInstrBuilder MIB(&MI);
500 AddDefaultPred(AddDefaultT1CC(MIB).addReg(FrameReg)
501 .addImm(Offset / Scale));
503 MI.getOperand(i).ChangeToRegister(FrameReg, false);
504 MI.getOperand(i+1).ChangeToImmediate(Offset / Scale);
509 unsigned DestReg = MI.getOperand(0).getReg();
510 unsigned Bytes = (Offset > 0) ? Offset : -Offset;
511 unsigned NumMIs = calcNumMI(Opcode, 0, Bytes, NumBits, Scale);
512 // MI would expand into a large number of instructions. Don't try to
513 // simplify the immediate.
515 emitThumbRegPlusImmediate(MBB, II, DestReg, FrameReg, Offset, TII,
522 // Translate r0 = add sp, imm to
523 // r0 = add sp, 255*4
524 // r0 = add r0, (imm - 255*4)
525 if (Opcode == ARM::tADDi3) {
526 removeOperands(MI, i);
527 MachineInstrBuilder MIB(&MI);
528 AddDefaultPred(AddDefaultT1CC(MIB).addReg(FrameReg).addImm(Mask));
530 MI.getOperand(i).ChangeToRegister(FrameReg, false);
531 MI.getOperand(i+1).ChangeToImmediate(Mask);
533 Offset = (Offset - Mask * Scale);
534 MachineBasicBlock::iterator NII = next(II);
535 emitThumbRegPlusImmediate(MBB, NII, DestReg, DestReg, Offset, TII,
538 // Translate r0 = add sp, -imm to
539 // r0 = -imm (this is then translated into a series of instructons)
541 emitThumbConstant(MBB, II, DestReg, Offset, TII, *this, dl);
543 MI.setDesc(TII.get(ARM::tADDhirr));
544 MI.getOperand(i).ChangeToRegister(DestReg, false, false, true);
545 MI.getOperand(i+1).ChangeToRegister(FrameReg, false);
546 if (Opcode == ARM::tADDi3) {
547 MachineInstrBuilder MIB(&MI);
555 unsigned NumBits = 0;
558 case ARMII::AddrModeT1_s: {
560 InstrOffs = MI.getOperand(ImmIdx).getImm();
561 NumBits = (FrameReg == ARM::SP) ? 8 : 5;
566 llvm_unreachable("Unsupported addressing mode!");
570 Offset += InstrOffs * Scale;
571 assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
573 // Common case: small offset, fits into instruction.
574 MachineOperand &ImmOp = MI.getOperand(ImmIdx);
575 int ImmedOffset = Offset / Scale;
576 unsigned Mask = (1 << NumBits) - 1;
577 if ((unsigned)Offset <= Mask * Scale) {
578 // Replace the FrameIndex with sp
579 MI.getOperand(i).ChangeToRegister(FrameReg, false);
580 ImmOp.ChangeToImmediate(ImmedOffset);
584 bool isThumSpillRestore = Opcode == ARM::tRestore || Opcode == ARM::tSpill;
585 if (AddrMode == ARMII::AddrModeT1_s) {
586 // Thumb tLDRspi, tSTRspi. These will change to instructions that use
587 // a different base register.
589 Mask = (1 << NumBits) - 1;
591 // If this is a thumb spill / restore, we will be using a constpool load to
592 // materialize the offset.
593 if (AddrMode == ARMII::AddrModeT1_s && isThumSpillRestore)
594 ImmOp.ChangeToImmediate(0);
596 // Otherwise, it didn't fit. Pull in what we can to simplify the immed.
597 ImmedOffset = ImmedOffset & Mask;
598 ImmOp.ChangeToImmediate(ImmedOffset);
599 Offset &= ~(Mask*Scale);
603 // If we get here, the immediate doesn't fit into the instruction. We folded
604 // as much as possible above, handle the rest, providing a register that is
606 assert(Offset && "This code isn't needed if offset already handled!");
608 // Remove predicate first.
609 int PIdx = MI.findFirstPredOperandIdx();
611 removeOperands(MI, PIdx);
613 if (Desc.mayLoad()) {
614 // Use the destination register to materialize sp + offset.
615 unsigned TmpReg = MI.getOperand(0).getReg();
617 if (Opcode == ARM::tRestore) {
618 if (FrameReg == ARM::SP)
619 emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,
620 Offset, false, TII, *this, dl);
622 emitLoadConstPool(MBB, II, dl, TmpReg, 0, Offset);
626 emitThumbRegPlusImmediate(MBB, II, TmpReg, FrameReg, Offset, TII,
630 MI.setDesc(TII.get(ARM::tLDR));
631 MI.getOperand(i).ChangeToRegister(TmpReg, false, false, true);
633 // Use [reg, reg] addrmode.
634 MI.addOperand(MachineOperand::CreateReg(FrameReg, false));
635 else // tLDR has an extra register operand.
636 MI.addOperand(MachineOperand::CreateReg(0, false));
637 } else if (Desc.mayStore()) {
638 if (FrameIndexVirtualScavenging) {
639 VReg = MF.getRegInfo().createVirtualRegister(ARM::tGPRRegisterClass);
640 assert (Value && "Frame index virtual allocated, but Value arg is NULL!");
644 if (Opcode == ARM::tSpill) {
645 if (FrameReg == ARM::SP)
646 emitThumbRegPlusImmInReg(MBB, II, VReg, FrameReg,
647 Offset, false, TII, *this, dl);
649 emitLoadConstPool(MBB, II, dl, VReg, 0, Offset);
653 emitThumbRegPlusImmediate(MBB, II, VReg, FrameReg, Offset, TII,
655 MI.setDesc(TII.get(ARM::tSTR));
656 MI.getOperand(i).ChangeToRegister(VReg, false, false, true);
657 if (UseRR) // Use [reg, reg] addrmode.
658 MI.addOperand(MachineOperand::CreateReg(FrameReg, false));
659 else // tSTR has an extra register operand.
660 MI.addOperand(MachineOperand::CreateReg(0, false));
662 // FIXME! This is horrific!!! We need register scavenging.
663 // Our temporary workaround has marked r3 unavailable. Of course, r3 is
664 // also a ABI register so it's possible that is is the register that is
665 // being storing here. If that's the case, we do the following:
667 // Use r2 to materialize sp + offset
670 unsigned ValReg = MI.getOperand(0).getReg();
671 unsigned TmpReg = ARM::R3;
673 if (ValReg == ARM::R3) {
674 BuildMI(MBB, II, dl, TII.get(ARM::tMOVtgpr2gpr), ARM::R12)
675 .addReg(ARM::R2, RegState::Kill);
678 if (TmpReg == ARM::R3 && AFI->isR3LiveIn())
679 BuildMI(MBB, II, dl, TII.get(ARM::tMOVtgpr2gpr), ARM::R12)
680 .addReg(ARM::R3, RegState::Kill);
681 if (Opcode == ARM::tSpill) {
682 if (FrameReg == ARM::SP)
683 emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,
684 Offset, false, TII, *this, dl);
686 emitLoadConstPool(MBB, II, dl, TmpReg, 0, Offset);
690 emitThumbRegPlusImmediate(MBB, II, TmpReg, FrameReg, Offset, TII,
692 MI.setDesc(TII.get(ARM::tSTR));
693 MI.getOperand(i).ChangeToRegister(TmpReg, false, false, true);
694 if (UseRR) // Use [reg, reg] addrmode.
695 MI.addOperand(MachineOperand::CreateReg(FrameReg, false));
696 else // tSTR has an extra register operand.
697 MI.addOperand(MachineOperand::CreateReg(0, false));
699 MachineBasicBlock::iterator NII = next(II);
700 if (ValReg == ARM::R3)
701 BuildMI(MBB, NII, dl, TII.get(ARM::tMOVgpr2tgpr), ARM::R2)
702 .addReg(ARM::R12, RegState::Kill);
703 if (TmpReg == ARM::R3 && AFI->isR3LiveIn())
704 BuildMI(MBB, NII, dl, TII.get(ARM::tMOVgpr2tgpr), ARM::R3)
705 .addReg(ARM::R12, RegState::Kill);
708 assert(false && "Unexpected opcode!");
710 // Add predicate back if it's needed.
711 if (MI.getDesc().isPredicable()) {
712 MachineInstrBuilder MIB(&MI);
718 void Thumb1RegisterInfo::emitPrologue(MachineFunction &MF) const {
719 MachineBasicBlock &MBB = MF.front();
720 MachineBasicBlock::iterator MBBI = MBB.begin();
721 MachineFrameInfo *MFI = MF.getFrameInfo();
722 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
723 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
724 unsigned NumBytes = MFI->getStackSize();
725 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
726 DebugLoc dl = (MBBI != MBB.end() ?
727 MBBI->getDebugLoc() : DebugLoc::getUnknownLoc());
729 // Check if R3 is live in. It might have to be used as a scratch register.
730 for (MachineRegisterInfo::livein_iterator I =MF.getRegInfo().livein_begin(),
731 E = MF.getRegInfo().livein_end(); I != E; ++I) {
732 if (I->first == ARM::R3) {
733 AFI->setR3IsLiveIn(true);
738 // Thumb add/sub sp, imm8 instructions implicitly multiply the offset by 4.
739 NumBytes = (NumBytes + 3) & ~3;
740 MFI->setStackSize(NumBytes);
742 // Determine the sizes of each callee-save spill areas and record which frame
743 // belongs to which callee-save spill areas.
744 unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
745 int FramePtrSpillFI = 0;
748 emitSPUpdate(MBB, MBBI, TII, dl, *this, -VARegSaveSize);
750 if (!AFI->hasStackFrame()) {
752 emitSPUpdate(MBB, MBBI, TII, dl, *this, -NumBytes);
756 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
757 unsigned Reg = CSI[i].getReg();
758 int FI = CSI[i].getFrameIdx();
766 FramePtrSpillFI = FI;
767 AFI->addGPRCalleeSavedArea1Frame(FI);
775 FramePtrSpillFI = FI;
776 if (STI.isTargetDarwin()) {
777 AFI->addGPRCalleeSavedArea2Frame(FI);
780 AFI->addGPRCalleeSavedArea1Frame(FI);
785 AFI->addDPRCalleeSavedAreaFrame(FI);
790 if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPUSH) {
792 if (MBBI != MBB.end())
793 dl = MBBI->getDebugLoc();
796 // Darwin ABI requires FP to point to the stack slot that contains the
798 if (STI.isTargetDarwin() || hasFP(MF)) {
799 BuildMI(MBB, MBBI, dl, TII.get(ARM::tADDrSPi), FramePtr)
800 .addFrameIndex(FramePtrSpillFI).addImm(0);
803 // Determine starting offsets of spill areas.
804 unsigned DPRCSOffset = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize);
805 unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize;
806 unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size;
807 AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) + NumBytes);
808 AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
809 AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
810 AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
812 NumBytes = DPRCSOffset;
814 // Insert it after all the callee-save spills.
815 emitSPUpdate(MBB, MBBI, TII, dl, *this, -NumBytes);
818 if (STI.isTargetELF() && hasFP(MF)) {
819 MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() -
820 AFI->getFramePtrSpillOffset());
823 AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
824 AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
825 AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
828 static bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) {
829 for (unsigned i = 0; CSRegs[i]; ++i)
830 if (Reg == CSRegs[i])
835 static bool isCSRestore(MachineInstr *MI, const unsigned *CSRegs) {
836 return (MI->getOpcode() == ARM::tRestore &&
837 MI->getOperand(1).isFI() &&
838 isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs));
841 void Thumb1RegisterInfo::emitEpilogue(MachineFunction &MF,
842 MachineBasicBlock &MBB) const {
843 MachineBasicBlock::iterator MBBI = prior(MBB.end());
844 assert((MBBI->getOpcode() == ARM::tBX_RET ||
845 MBBI->getOpcode() == ARM::tPOP_RET) &&
846 "Can only insert epilog into returning blocks");
847 DebugLoc dl = MBBI->getDebugLoc();
848 MachineFrameInfo *MFI = MF.getFrameInfo();
849 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
850 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
851 int NumBytes = (int)MFI->getStackSize();
853 if (!AFI->hasStackFrame()) {
855 emitSPUpdate(MBB, MBBI, TII, dl, *this, NumBytes);
857 // Unwind MBBI to point to first LDR / FLDD.
858 const unsigned *CSRegs = getCalleeSavedRegs();
859 if (MBBI != MBB.begin()) {
862 while (MBBI != MBB.begin() && isCSRestore(MBBI, CSRegs));
863 if (!isCSRestore(MBBI, CSRegs))
867 // Move SP to start of FP callee save spill area.
868 NumBytes -= (AFI->getGPRCalleeSavedArea1Size() +
869 AFI->getGPRCalleeSavedArea2Size() +
870 AFI->getDPRCalleeSavedAreaSize());
873 NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
874 // Reset SP based on frame pointer only if the stack frame extends beyond
875 // frame pointer stack slot or target is ELF and the function has FP.
877 emitThumbRegPlusImmediate(MBB, MBBI, ARM::SP, FramePtr, -NumBytes,
880 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVtgpr2gpr), ARM::SP)
883 if (MBBI->getOpcode() == ARM::tBX_RET &&
884 &MBB.front() != MBBI &&
885 prior(MBBI)->getOpcode() == ARM::tPOP) {
886 MachineBasicBlock::iterator PMBBI = prior(MBBI);
887 emitSPUpdate(MBB, PMBBI, TII, dl, *this, NumBytes);
889 emitSPUpdate(MBB, MBBI, TII, dl, *this, NumBytes);
894 // Epilogue for vararg functions: pop LR to R3 and branch off it.
895 // FIXME: Verify this is still ok when R3 is no longer being reserved.
896 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tPOP)))
897 .addReg(0) // No write back.
898 .addReg(ARM::R3, RegState::Define);
900 emitSPUpdate(MBB, MBBI, TII, dl, *this, VARegSaveSize);
902 BuildMI(MBB, MBBI, dl, TII.get(ARM::tBX_RET_vararg))
903 .addReg(ARM::R3, RegState::Kill);