1 //===-- Thumb1RegisterInfo.cpp - Thumb-1 Register Information -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Thumb-1 implementation of the TargetRegisterInfo
13 //===----------------------------------------------------------------------===//
15 #include "Thumb1RegisterInfo.h"
16 #include "ARMBaseInstrInfo.h"
17 #include "ARMMachineFunctionInfo.h"
18 #include "ARMSubtarget.h"
19 #include "MCTargetDesc/ARMAddressingModes.h"
20 #include "llvm/CodeGen/MachineConstantPool.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/RegisterScavenging.h"
26 #include "llvm/IR/Constants.h"
27 #include "llvm/IR/DerivedTypes.h"
28 #include "llvm/IR/Function.h"
29 #include "llvm/IR/LLVMContext.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Support/ErrorHandling.h"
32 #include "llvm/Target/TargetFrameLowering.h"
33 #include "llvm/Target/TargetMachine.h"
36 extern cl::opt<bool> ReuseFrameIndexVals;
41 Thumb1RegisterInfo::Thumb1RegisterInfo(const ARMSubtarget &sti)
42 : ARMBaseRegisterInfo(sti) {
45 const TargetRegisterClass*
46 Thumb1RegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC)
48 if (ARM::tGPRRegClass.hasSubClassEq(RC))
49 return &ARM::tGPRRegClass;
50 return ARMBaseRegisterInfo::getLargestLegalSuperClass(RC);
53 const TargetRegisterClass *
54 Thumb1RegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind)
56 return &ARM::tGPRRegClass;
59 /// emitLoadConstPool - Emits a load from constpool to materialize the
60 /// specified immediate.
62 Thumb1RegisterInfo::emitLoadConstPool(MachineBasicBlock &MBB,
63 MachineBasicBlock::iterator &MBBI,
65 unsigned DestReg, unsigned SubIdx,
67 ARMCC::CondCodes Pred, unsigned PredReg,
68 unsigned MIFlags) const {
69 MachineFunction &MF = *MBB.getParent();
70 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
71 MachineConstantPool *ConstantPool = MF.getConstantPool();
72 const Constant *C = ConstantInt::get(
73 Type::getInt32Ty(MBB.getParent()->getFunction()->getContext()), Val);
74 unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
76 BuildMI(MBB, MBBI, dl, TII.get(ARM::tLDRpci))
77 .addReg(DestReg, getDefRegState(true), SubIdx)
78 .addConstantPoolIndex(Idx).addImm(Pred).addReg(PredReg)
83 /// emitThumbRegPlusImmInReg - Emits a series of instructions to materialize
84 /// a destreg = basereg + immediate in Thumb code. Materialize the immediate
85 /// in a register using mov / mvn sequences or load the immediate from a
88 void emitThumbRegPlusImmInReg(MachineBasicBlock &MBB,
89 MachineBasicBlock::iterator &MBBI,
91 unsigned DestReg, unsigned BaseReg,
92 int NumBytes, bool CanChangeCC,
93 const TargetInstrInfo &TII,
94 const ARMBaseRegisterInfo& MRI,
95 unsigned MIFlags = MachineInstr::NoFlags) {
96 MachineFunction &MF = *MBB.getParent();
97 bool isHigh = !isARMLowRegister(DestReg) ||
98 (BaseReg != 0 && !isARMLowRegister(BaseReg));
100 // Subtract doesn't have high register version. Load the negative value
101 // if either base or dest register is a high register. Also, if do not
102 // issue sub as part of the sequence if condition register is to be
104 if (NumBytes < 0 && !isHigh && CanChangeCC) {
106 NumBytes = -NumBytes;
108 unsigned LdReg = DestReg;
109 if (DestReg == ARM::SP) {
110 assert(BaseReg == ARM::SP && "Unexpected!");
111 LdReg = MF.getRegInfo().createVirtualRegister(&ARM::tGPRRegClass);
114 if (NumBytes <= 255 && NumBytes >= 0)
115 AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), LdReg))
116 .addImm(NumBytes).setMIFlags(MIFlags);
117 else if (NumBytes < 0 && NumBytes >= -255) {
118 AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), LdReg))
119 .addImm(NumBytes).setMIFlags(MIFlags);
120 AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tRSB), LdReg))
121 .addReg(LdReg, RegState::Kill).setMIFlags(MIFlags);
123 MRI.emitLoadConstPool(MBB, MBBI, dl, LdReg, 0, NumBytes,
124 ARMCC::AL, 0, MIFlags);
127 int Opc = (isSub) ? ARM::tSUBrr : (isHigh ? ARM::tADDhirr : ARM::tADDrr);
128 MachineInstrBuilder MIB =
129 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg);
130 if (Opc != ARM::tADDhirr)
131 MIB = AddDefaultT1CC(MIB);
132 if (DestReg == ARM::SP || isSub)
133 MIB.addReg(BaseReg).addReg(LdReg, RegState::Kill);
135 MIB.addReg(LdReg).addReg(BaseReg, RegState::Kill);
139 /// calcNumMI - Returns the number of instructions required to materialize
140 /// the specific add / sub r, c instruction.
141 static unsigned calcNumMI(int Opc, int ExtraOpc, unsigned Bytes,
142 unsigned NumBits, unsigned Scale) {
144 unsigned Chunk = ((1 << NumBits) - 1) * Scale;
146 if (Opc == ARM::tADDrSPi) {
147 unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes;
151 Scale = 1; // Followed by a number of tADDi8.
152 Chunk = ((1 << NumBits) - 1) * Scale;
155 NumMIs += Bytes / Chunk;
156 if ((Bytes % Chunk) != 0)
163 /// emitThumbRegPlusImmediate - Emits a series of instructions to materialize
164 /// a destreg = basereg + immediate in Thumb code.
165 void llvm::emitThumbRegPlusImmediate(MachineBasicBlock &MBB,
166 MachineBasicBlock::iterator &MBBI,
168 unsigned DestReg, unsigned BaseReg,
169 int NumBytes, const TargetInstrInfo &TII,
170 const ARMBaseRegisterInfo& MRI,
172 bool isSub = NumBytes < 0;
173 unsigned Bytes = (unsigned)NumBytes;
174 if (isSub) Bytes = -NumBytes;
175 bool isMul4 = (Bytes & 3) == 0;
176 bool isTwoAddr = false;
177 bool DstNotEqBase = false;
178 unsigned NumBits = 1;
184 if (DestReg == BaseReg && BaseReg == ARM::SP) {
185 assert(isMul4 && "Thumb sp inc / dec size must be multiple of 4!");
188 Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
190 } else if (!isSub && BaseReg == ARM::SP) {
193 // r1 = add sp, 100 * 4
197 ExtraOpc = ARM::tADDi3;
206 if (DestReg != BaseReg)
209 if (DestReg == ARM::SP) {
210 Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
211 assert(isMul4 && "Thumb sp inc / dec size must be multiple of 4!");
215 Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8;
222 unsigned NumMIs = calcNumMI(Opc, ExtraOpc, Bytes, NumBits, Scale);
223 unsigned Threshold = (DestReg == ARM::SP) ? 3 : 2;
224 if (NumMIs > Threshold) {
225 // This will expand into too many instructions. Load the immediate from a
227 emitThumbRegPlusImmInReg(MBB, MBBI, dl,
228 DestReg, BaseReg, NumBytes, true,
234 if (isARMLowRegister(DestReg) && isARMLowRegister(BaseReg)) {
235 // If both are low registers, emit DestReg = add BaseReg, max(Imm, 7)
236 unsigned Chunk = (1 << 3) - 1;
237 unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes;
239 const MCInstrDesc &MCID = TII.get(isSub ? ARM::tSUBi3 : ARM::tADDi3);
240 const MachineInstrBuilder MIB =
241 AddDefaultT1CC(BuildMI(MBB, MBBI, dl, MCID, DestReg)
242 .setMIFlags(MIFlags));
243 AddDefaultPred(MIB.addReg(BaseReg, RegState::Kill).addImm(ThisVal));
245 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), DestReg)
246 .addReg(BaseReg, RegState::Kill))
247 .setMIFlags(MIFlags);
252 unsigned Chunk = ((1 << NumBits) - 1) * Scale;
254 unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes;
257 // Build the new tADD / tSUB.
259 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg);
261 MIB = AddDefaultT1CC(MIB);
262 MIB.addReg(DestReg).addImm(ThisVal);
263 MIB = AddDefaultPred(MIB);
264 MIB.setMIFlags(MIFlags);
266 bool isKill = BaseReg != ARM::SP;
267 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg);
269 MIB = AddDefaultT1CC(MIB);
270 MIB.addReg(BaseReg, getKillRegState(isKill)).addImm(ThisVal);
271 MIB = AddDefaultPred(MIB);
272 MIB.setMIFlags(MIFlags);
275 if (Opc == ARM::tADDrSPi) {
281 Chunk = ((1 << NumBits) - 1) * Scale;
282 Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8;
283 NeedCC = isTwoAddr = true;
289 const MCInstrDesc &MCID = TII.get(ExtraOpc);
290 AddDefaultPred(AddDefaultT1CC(BuildMI(MBB, MBBI, dl, MCID, DestReg))
291 .addReg(DestReg, RegState::Kill)
292 .addImm(((unsigned)NumBytes) & 3)
293 .setMIFlags(MIFlags));
297 /// emitThumbConstant - Emit a series of instructions to materialize a
299 static void emitThumbConstant(MachineBasicBlock &MBB,
300 MachineBasicBlock::iterator &MBBI,
301 unsigned DestReg, int Imm,
302 const TargetInstrInfo &TII,
303 const Thumb1RegisterInfo& MRI,
305 bool isSub = Imm < 0;
306 if (isSub) Imm = -Imm;
308 int Chunk = (1 << 8) - 1;
309 int ThisVal = (Imm > Chunk) ? Chunk : Imm;
311 AddDefaultPred(AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8),
315 emitThumbRegPlusImmediate(MBB, MBBI, dl, DestReg, DestReg, Imm, TII, MRI);
317 const MCInstrDesc &MCID = TII.get(ARM::tRSB);
318 AddDefaultPred(AddDefaultT1CC(BuildMI(MBB, MBBI, dl, MCID, DestReg))
319 .addReg(DestReg, RegState::Kill));
323 static void removeOperands(MachineInstr &MI, unsigned i) {
325 for (unsigned e = MI.getNumOperands(); i != e; ++i)
326 MI.RemoveOperand(Op);
329 /// convertToNonSPOpcode - Change the opcode to the non-SP version, because
330 /// we're replacing the frame index with a non-SP register.
331 static unsigned convertToNonSPOpcode(unsigned Opcode) {
343 bool Thumb1RegisterInfo::
344 rewriteFrameIndex(MachineBasicBlock::iterator II, unsigned FrameRegIdx,
345 unsigned FrameReg, int &Offset,
346 const ARMBaseInstrInfo &TII) const {
347 MachineInstr &MI = *II;
348 MachineBasicBlock &MBB = *MI.getParent();
349 DebugLoc dl = MI.getDebugLoc();
350 MachineInstrBuilder MIB(*MBB.getParent(), &MI);
351 unsigned Opcode = MI.getOpcode();
352 const MCInstrDesc &Desc = MI.getDesc();
353 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
355 if (Opcode == ARM::tADDrSPi) {
356 Offset += MI.getOperand(FrameRegIdx+1).getImm();
358 // Can't use tADDrSPi if it's based off the frame pointer.
359 unsigned NumBits = 0;
361 if (FrameReg != ARM::SP) {
362 Opcode = ARM::tADDi3;
367 assert((Offset & 3) == 0 &&
368 "Thumb add/sub sp, #imm immediate must be multiple of 4!");
372 if (Offset == 0 && getInstrPredicate(&MI, PredReg) == ARMCC::AL) {
373 // Turn it into a move.
374 MI.setDesc(TII.get(ARM::tMOVr));
375 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
377 MI.RemoveOperand(FrameRegIdx+1);
381 // Common case: small offset, fits into instruction.
382 unsigned Mask = (1 << NumBits) - 1;
383 if (((Offset / Scale) & ~Mask) == 0) {
384 // Replace the FrameIndex with sp / fp
385 if (Opcode == ARM::tADDi3) {
386 MI.setDesc(TII.get(Opcode));
387 removeOperands(MI, FrameRegIdx);
388 AddDefaultPred(AddDefaultT1CC(MIB).addReg(FrameReg)
389 .addImm(Offset / Scale));
391 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
392 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset / Scale);
397 unsigned DestReg = MI.getOperand(0).getReg();
398 unsigned Bytes = (Offset > 0) ? Offset : -Offset;
399 unsigned NumMIs = calcNumMI(Opcode, 0, Bytes, NumBits, Scale);
400 // MI would expand into a large number of instructions. Don't try to
401 // simplify the immediate.
403 emitThumbRegPlusImmediate(MBB, II, dl, DestReg, FrameReg, Offset, TII,
410 // Translate r0 = add sp, imm to
411 // r0 = add sp, 255*4
412 // r0 = add r0, (imm - 255*4)
413 if (Opcode == ARM::tADDi3) {
414 MI.setDesc(TII.get(Opcode));
415 removeOperands(MI, FrameRegIdx);
416 AddDefaultPred(AddDefaultT1CC(MIB).addReg(FrameReg).addImm(Mask));
418 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
419 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Mask);
421 Offset = (Offset - Mask * Scale);
422 MachineBasicBlock::iterator NII = std::next(II);
423 emitThumbRegPlusImmediate(MBB, NII, dl, DestReg, DestReg, Offset, TII,
426 // Translate r0 = add sp, -imm to
427 // r0 = -imm (this is then translated into a series of instructions)
429 emitThumbConstant(MBB, II, DestReg, Offset, TII, *this, dl);
431 MI.setDesc(TII.get(ARM::tADDhirr));
432 MI.getOperand(FrameRegIdx).ChangeToRegister(DestReg, false, false, true);
433 MI.getOperand(FrameRegIdx+1).ChangeToRegister(FrameReg, false);
437 if (AddrMode != ARMII::AddrModeT1_s)
438 llvm_unreachable("Unsupported addressing mode!");
440 unsigned ImmIdx = FrameRegIdx + 1;
441 int InstrOffs = MI.getOperand(ImmIdx).getImm();
442 unsigned NumBits = (FrameReg == ARM::SP) ? 8 : 5;
445 Offset += InstrOffs * Scale;
446 assert((Offset & (Scale - 1)) == 0 && "Can't encode this offset!");
448 // Common case: small offset, fits into instruction.
449 MachineOperand &ImmOp = MI.getOperand(ImmIdx);
450 int ImmedOffset = Offset / Scale;
451 unsigned Mask = (1 << NumBits) - 1;
453 if ((unsigned)Offset <= Mask * Scale) {
454 // Replace the FrameIndex with the frame register (e.g., sp).
455 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
456 ImmOp.ChangeToImmediate(ImmedOffset);
458 // If we're using a register where sp was stored, convert the instruction
459 // to the non-SP version.
460 unsigned NewOpc = convertToNonSPOpcode(Opcode);
461 if (NewOpc != Opcode && FrameReg != ARM::SP)
462 MI.setDesc(TII.get(NewOpc));
468 Mask = (1 << NumBits) - 1;
470 // If this is a thumb spill / restore, we will be using a constpool load to
471 // materialize the offset.
472 if (Opcode == ARM::tLDRspi || Opcode == ARM::tSTRspi) {
473 ImmOp.ChangeToImmediate(0);
475 // Otherwise, it didn't fit. Pull in what we can to simplify the immed.
476 ImmedOffset = ImmedOffset & Mask;
477 ImmOp.ChangeToImmediate(ImmedOffset);
478 Offset &= ~(Mask * Scale);
485 void Thumb1RegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
486 int64_t Offset) const {
487 const ARMBaseInstrInfo &TII =
488 *static_cast<const ARMBaseInstrInfo *>(MI.getParent()
493 int Off = Offset; // ARM doesn't need the general 64-bit offsets
496 while (!MI.getOperand(i).isFI()) {
498 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
500 bool Done = rewriteFrameIndex(MI, i, BaseReg, Off, TII);
501 assert (Done && "Unable to resolve frame index!");
505 /// saveScavengerRegister - Spill the register so it can be used by the
506 /// register scavenger. Return true.
508 Thumb1RegisterInfo::saveScavengerRegister(MachineBasicBlock &MBB,
509 MachineBasicBlock::iterator I,
510 MachineBasicBlock::iterator &UseMI,
511 const TargetRegisterClass *RC,
512 unsigned Reg) const {
513 // Thumb1 can't use the emergency spill slot on the stack because
514 // ldr/str immediate offsets must be positive, and if we're referencing
515 // off the frame pointer (if, for example, there are alloca() calls in
516 // the function, the offset will be negative. Use R12 instead since that's
517 // a call clobbered register that we know won't be used in Thumb1 mode.
518 const TargetInstrInfo &TII = *MBB.getParent()->getSubtarget().getInstrInfo();
520 AddDefaultPred(BuildMI(MBB, I, DL, TII.get(ARM::tMOVr))
521 .addReg(ARM::R12, RegState::Define)
522 .addReg(Reg, RegState::Kill));
524 // The UseMI is where we would like to restore the register. If there's
525 // interference with R12 before then, however, we'll need to restore it
526 // before that instead and adjust the UseMI.
528 for (MachineBasicBlock::iterator II = I; !done && II != UseMI ; ++II) {
529 if (II->isDebugValue())
531 // If this instruction affects R12, adjust our restore point.
532 for (unsigned i = 0, e = II->getNumOperands(); i != e; ++i) {
533 const MachineOperand &MO = II->getOperand(i);
534 if (MO.isRegMask() && MO.clobbersPhysReg(ARM::R12)) {
539 if (!MO.isReg() || MO.isUndef() || !MO.getReg() ||
540 TargetRegisterInfo::isVirtualRegister(MO.getReg()))
542 if (MO.getReg() == ARM::R12) {
549 // Restore the register from R12
550 AddDefaultPred(BuildMI(MBB, UseMI, DL, TII.get(ARM::tMOVr)).
551 addReg(Reg, RegState::Define).addReg(ARM::R12, RegState::Kill));
557 Thumb1RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
558 int SPAdj, unsigned FIOperandNum,
559 RegScavenger *RS) const {
561 MachineInstr &MI = *II;
562 MachineBasicBlock &MBB = *MI.getParent();
563 MachineFunction &MF = *MBB.getParent();
564 const ARMBaseInstrInfo &TII =
565 *static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo());
566 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
567 DebugLoc dl = MI.getDebugLoc();
568 MachineInstrBuilder MIB(*MBB.getParent(), &MI);
570 unsigned FrameReg = ARM::SP;
571 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
572 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
573 MF.getFrameInfo()->getStackSize() + SPAdj;
575 if (MF.getFrameInfo()->hasVarSizedObjects()) {
576 assert(SPAdj == 0 && MF.getSubtarget().getFrameLowering()->hasFP(MF) &&
578 // There are alloca()'s in this function, must reference off the frame
579 // pointer or base pointer instead.
580 if (!hasBasePointer(MF)) {
581 FrameReg = getFrameRegister(MF);
582 Offset -= AFI->getFramePtrSpillOffset();
587 // PEI::scavengeFrameVirtualRegs() cannot accurately track SPAdj because the
588 // call frame setup/destroy instructions have already been eliminated. That
589 // means the stack pointer cannot be used to access the emergency spill slot
590 // when !hasReservedCallFrame().
592 if (RS && FrameReg == ARM::SP && RS->isScavengingFrameIndex(FrameIndex)){
593 assert(MF.getTarget()
596 ->hasReservedCallFrame(MF) &&
597 "Cannot use SP to access the emergency spill slot in "
598 "functions without a reserved call frame");
599 assert(!MF.getFrameInfo()->hasVarSizedObjects() &&
600 "Cannot use SP to access the emergency spill slot in "
601 "functions with variable sized frame objects");
605 // Special handling of dbg_value instructions.
606 if (MI.isDebugValue()) {
607 MI.getOperand(FIOperandNum). ChangeToRegister(FrameReg, false /*isDef*/);
608 MI.getOperand(FIOperandNum+1).ChangeToImmediate(Offset);
612 // Modify MI as necessary to handle as much of 'Offset' as possible
613 assert(AFI->isThumbFunction() &&
614 "This eliminateFrameIndex only supports Thumb1!");
615 if (rewriteFrameIndex(MI, FIOperandNum, FrameReg, Offset, TII))
618 // If we get here, the immediate doesn't fit into the instruction. We folded
619 // as much as possible above, handle the rest, providing a register that is
621 assert(Offset && "This code isn't needed if offset already handled!");
623 unsigned Opcode = MI.getOpcode();
625 // Remove predicate first.
626 int PIdx = MI.findFirstPredOperandIdx();
628 removeOperands(MI, PIdx);
631 // Use the destination register to materialize sp + offset.
632 unsigned TmpReg = MI.getOperand(0).getReg();
634 if (Opcode == ARM::tLDRspi) {
635 if (FrameReg == ARM::SP)
636 emitThumbRegPlusImmInReg(MBB, II, dl, TmpReg, FrameReg,
637 Offset, false, TII, *this);
639 emitLoadConstPool(MBB, II, dl, TmpReg, 0, Offset);
643 emitThumbRegPlusImmediate(MBB, II, dl, TmpReg, FrameReg, Offset, TII,
647 MI.setDesc(TII.get(UseRR ? ARM::tLDRr : ARM::tLDRi));
648 MI.getOperand(FIOperandNum).ChangeToRegister(TmpReg, false, false, true);
650 // Use [reg, reg] addrmode. Replace the immediate operand w/ the frame
651 // register. The offset is already handled in the vreg value.
652 MI.getOperand(FIOperandNum+1).ChangeToRegister(FrameReg, false, false,
654 } else if (MI.mayStore()) {
655 VReg = MF.getRegInfo().createVirtualRegister(&ARM::tGPRRegClass);
658 if (Opcode == ARM::tSTRspi) {
659 if (FrameReg == ARM::SP)
660 emitThumbRegPlusImmInReg(MBB, II, dl, VReg, FrameReg,
661 Offset, false, TII, *this);
663 emitLoadConstPool(MBB, II, dl, VReg, 0, Offset);
667 emitThumbRegPlusImmediate(MBB, II, dl, VReg, FrameReg, Offset, TII,
669 MI.setDesc(TII.get(UseRR ? ARM::tSTRr : ARM::tSTRi));
670 MI.getOperand(FIOperandNum).ChangeToRegister(VReg, false, false, true);
672 // Use [reg, reg] addrmode. Replace the immediate operand w/ the frame
673 // register. The offset is already handled in the vreg value.
674 MI.getOperand(FIOperandNum+1).ChangeToRegister(FrameReg, false, false,
677 llvm_unreachable("Unexpected opcode!");
680 // Add predicate back if it's needed.
681 if (MI.isPredicable())