1 //===- Thumb1RegisterInfo.cpp - Thumb-1 Register Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Thumb-1 implementation of the TargetRegisterInfo class.
12 //===----------------------------------------------------------------------===//
15 #include "ARMAddressingModes.h"
16 #include "ARMBaseInstrInfo.h"
17 #include "ARMMachineFunctionInfo.h"
18 #include "ARMSubtarget.h"
19 #include "Thumb1InstrInfo.h"
20 #include "Thumb1RegisterInfo.h"
21 #include "llvm/Constants.h"
22 #include "llvm/DerivedTypes.h"
23 #include "llvm/CodeGen/MachineConstantPool.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineLocation.h"
28 #include "llvm/CodeGen/MachineRegisterInfo.h"
29 #include "llvm/Target/TargetFrameInfo.h"
30 #include "llvm/Target/TargetMachine.h"
31 #include "llvm/ADT/BitVector.h"
32 #include "llvm/ADT/SmallVector.h"
33 #include "llvm/Support/CommandLine.h"
34 #include "llvm/Support/ErrorHandling.h"
38 ThumbRegScavenging("enable-thumb-reg-scavenging",
40 cl::desc("Enable register scavenging on Thumb"));
42 Thumb1RegisterInfo::Thumb1RegisterInfo(const ARMBaseInstrInfo &tii,
43 const ARMSubtarget &sti)
44 : ARMBaseRegisterInfo(tii, sti) {
47 /// emitLoadConstPool - Emits a load from constpool to materialize the
48 /// specified immediate.
49 void Thumb1RegisterInfo::emitLoadConstPool(MachineBasicBlock &MBB,
50 MachineBasicBlock::iterator &MBBI,
52 unsigned DestReg, int Val,
53 ARMCC::CondCodes Pred,
54 unsigned PredReg) const {
55 MachineFunction &MF = *MBB.getParent();
56 MachineConstantPool *ConstantPool = MF.getConstantPool();
57 Constant *C = ConstantInt::get(Type::Int32Ty, Val);
58 unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
60 BuildMI(MBB, MBBI, dl, TII.get(ARM::tLDRcp), DestReg)
61 .addConstantPoolIndex(Idx);
64 const TargetRegisterClass*
65 Thumb1RegisterInfo::getPhysicalRegisterRegClass(unsigned Reg, MVT VT) const {
66 if (isARMLowRegister(Reg))
67 return ARM::tGPRRegisterClass;
71 case ARM::R8: case ARM::R9: case ARM::R10: case ARM::R11:
72 case ARM::R12: case ARM::SP: case ARM::LR: case ARM::PC:
73 return ARM::GPRRegisterClass;
76 return TargetRegisterInfo::getPhysicalRegisterRegClass(Reg, VT);
80 Thumb1RegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const {
81 return ThumbRegScavenging;
84 bool Thumb1RegisterInfo::hasReservedCallFrame(MachineFunction &MF) const {
85 const MachineFrameInfo *FFI = MF.getFrameInfo();
86 unsigned CFSize = FFI->getMaxCallFrameSize();
87 // It's not always a good idea to include the call frame as part of the
88 // stack frame. ARM (especially Thumb) has small immediate offset to
89 // address the stack frame. So a large call frame can cause poor codegen
90 // and may even makes it impossible to scavenge a register.
91 if (CFSize >= ((1 << 8) - 1) * 4 / 2) // Half of imm8 * 4
94 return !MF.getFrameInfo()->hasVarSizedObjects();
97 /// emitThumbRegPlusImmInReg - Emits a series of instructions to materialize
98 /// a destreg = basereg + immediate in Thumb code. Materialize the immediate
99 /// in a register using mov / mvn sequences or load the immediate from a
102 void emitThumbRegPlusImmInReg(MachineBasicBlock &MBB,
103 MachineBasicBlock::iterator &MBBI,
104 unsigned DestReg, unsigned BaseReg,
105 int NumBytes, bool CanChangeCC,
106 const TargetInstrInfo &TII,
107 const Thumb1RegisterInfo& MRI,
109 bool isHigh = !isARMLowRegister(DestReg) ||
110 (BaseReg != 0 && !isARMLowRegister(BaseReg));
112 // Subtract doesn't have high register version. Load the negative value
113 // if either base or dest register is a high register. Also, if do not
114 // issue sub as part of the sequence if condition register is to be
116 if (NumBytes < 0 && !isHigh && CanChangeCC) {
118 NumBytes = -NumBytes;
120 unsigned LdReg = DestReg;
121 if (DestReg == ARM::SP) {
122 assert(BaseReg == ARM::SP && "Unexpected!");
124 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVlor2hir), ARM::R12)
125 .addReg(ARM::R3, RegState::Kill);
128 if (NumBytes <= 255 && NumBytes >= 0)
129 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), LdReg).addImm(NumBytes);
130 else if (NumBytes < 0 && NumBytes >= -255) {
131 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), LdReg).addImm(NumBytes);
132 BuildMI(MBB, MBBI, dl, TII.get(ARM::tNEG), LdReg)
133 .addReg(LdReg, RegState::Kill);
135 MRI.emitLoadConstPool(MBB, MBBI, dl, LdReg, NumBytes);
138 int Opc = (isSub) ? ARM::tSUBrr : (isHigh ? ARM::tADDhirr : ARM::tADDrr);
139 const MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl,
140 TII.get(Opc), DestReg);
141 if (DestReg == ARM::SP || isSub)
142 MIB.addReg(BaseReg).addReg(LdReg, RegState::Kill);
144 MIB.addReg(LdReg).addReg(BaseReg, RegState::Kill);
145 if (DestReg == ARM::SP)
146 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVhir2lor), ARM::R3)
147 .addReg(ARM::R12, RegState::Kill);
150 /// calcNumMI - Returns the number of instructions required to materialize
151 /// the specific add / sub r, c instruction.
152 static unsigned calcNumMI(int Opc, int ExtraOpc, unsigned Bytes,
153 unsigned NumBits, unsigned Scale) {
155 unsigned Chunk = ((1 << NumBits) - 1) * Scale;
157 if (Opc == ARM::tADDrSPi) {
158 unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes;
162 Scale = 1; // Followed by a number of tADDi8.
163 Chunk = ((1 << NumBits) - 1) * Scale;
166 NumMIs += Bytes / Chunk;
167 if ((Bytes % Chunk) != 0)
174 /// emitThumbRegPlusImmediate - Emits a series of instructions to materialize
175 /// a destreg = basereg + immediate in Thumb code.
177 void emitThumbRegPlusImmediate(MachineBasicBlock &MBB,
178 MachineBasicBlock::iterator &MBBI,
179 unsigned DestReg, unsigned BaseReg,
180 int NumBytes, const TargetInstrInfo &TII,
181 const Thumb1RegisterInfo& MRI,
183 bool isSub = NumBytes < 0;
184 unsigned Bytes = (unsigned)NumBytes;
185 if (isSub) Bytes = -NumBytes;
186 bool isMul4 = (Bytes & 3) == 0;
187 bool isTwoAddr = false;
188 bool DstNotEqBase = false;
189 unsigned NumBits = 1;
194 if (DestReg == BaseReg && BaseReg == ARM::SP) {
195 assert(isMul4 && "Thumb sp inc / dec size must be multiple of 4!");
198 Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
200 } else if (!isSub && BaseReg == ARM::SP) {
203 // r1 = add sp, 100 * 4
207 ExtraOpc = ARM::tADDi3;
216 if (DestReg != BaseReg)
219 Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8;
223 unsigned NumMIs = calcNumMI(Opc, ExtraOpc, Bytes, NumBits, Scale);
224 unsigned Threshold = (DestReg == ARM::SP) ? 3 : 2;
225 if (NumMIs > Threshold) {
226 // This will expand into too many instructions. Load the immediate from a
228 emitThumbRegPlusImmInReg(MBB, MBBI, DestReg, BaseReg, NumBytes, true, TII,
234 if (isARMLowRegister(DestReg) && isARMLowRegister(BaseReg)) {
235 // If both are low registers, emit DestReg = add BaseReg, max(Imm, 7)
236 unsigned Chunk = (1 << 3) - 1;
237 unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes;
239 BuildMI(MBB, MBBI, dl,TII.get(isSub ? ARM::tSUBi3 : ARM::tADDi3), DestReg)
240 .addReg(BaseReg, RegState::Kill).addImm(ThisVal);
242 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), DestReg)
243 .addReg(BaseReg, RegState::Kill);
248 unsigned Chunk = ((1 << NumBits) - 1) * Scale;
250 unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes;
253 // Build the new tADD / tSUB.
255 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
256 .addReg(DestReg).addImm(ThisVal);
258 bool isKill = BaseReg != ARM::SP;
259 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
260 .addReg(BaseReg, getKillRegState(isKill)).addImm(ThisVal);
263 if (Opc == ARM::tADDrSPi) {
269 Chunk = ((1 << NumBits) - 1) * Scale;
270 Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8;
277 BuildMI(MBB, MBBI, dl, TII.get(ExtraOpc), DestReg)
278 .addReg(DestReg, RegState::Kill)
279 .addImm(((unsigned)NumBytes) & 3);
282 static void emitSPUpdate(MachineBasicBlock &MBB,
283 MachineBasicBlock::iterator &MBBI,
284 const TargetInstrInfo &TII, DebugLoc dl,
285 const Thumb1RegisterInfo &MRI,
287 emitThumbRegPlusImmediate(MBB, MBBI, ARM::SP, ARM::SP, NumBytes, TII,
291 void Thumb1RegisterInfo::
292 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
293 MachineBasicBlock::iterator I) const {
294 if (!hasReservedCallFrame(MF)) {
295 // If we have alloca, convert as follows:
296 // ADJCALLSTACKDOWN -> sub, sp, sp, amount
297 // ADJCALLSTACKUP -> add, sp, sp, amount
298 MachineInstr *Old = I;
299 DebugLoc dl = Old->getDebugLoc();
300 unsigned Amount = Old->getOperand(0).getImm();
302 // We need to keep the stack aligned properly. To do this, we round the
303 // amount of space needed for the outgoing arguments up to the next
304 // alignment boundary.
305 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
306 Amount = (Amount+Align-1)/Align*Align;
308 // Replace the pseudo instruction with a new instruction...
309 unsigned Opc = Old->getOpcode();
310 if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
311 emitSPUpdate(MBB, I, TII, dl, *this, -Amount);
313 assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
314 emitSPUpdate(MBB, I, TII, dl, *this, Amount);
321 /// emitThumbConstant - Emit a series of instructions to materialize a
323 static void emitThumbConstant(MachineBasicBlock &MBB,
324 MachineBasicBlock::iterator &MBBI,
325 unsigned DestReg, int Imm,
326 const TargetInstrInfo &TII,
327 const Thumb1RegisterInfo& MRI,
329 bool isSub = Imm < 0;
330 if (isSub) Imm = -Imm;
332 int Chunk = (1 << 8) - 1;
333 int ThisVal = (Imm > Chunk) ? Chunk : Imm;
335 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), DestReg).addImm(ThisVal);
337 emitThumbRegPlusImmediate(MBB, MBBI, DestReg, DestReg, Imm, TII, MRI, dl);
339 BuildMI(MBB, MBBI, dl, TII.get(ARM::tNEG), DestReg)
340 .addReg(DestReg, RegState::Kill);
343 void Thumb1RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
344 int SPAdj, RegScavenger *RS) const{
346 MachineInstr &MI = *II;
347 MachineBasicBlock &MBB = *MI.getParent();
348 MachineFunction &MF = *MBB.getParent();
349 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
350 DebugLoc dl = MI.getDebugLoc();
352 while (!MI.getOperand(i).isFI()) {
354 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
357 unsigned FrameReg = ARM::SP;
358 int FrameIndex = MI.getOperand(i).getIndex();
359 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
360 MF.getFrameInfo()->getStackSize() + SPAdj;
362 if (AFI->isGPRCalleeSavedArea1Frame(FrameIndex))
363 Offset -= AFI->getGPRCalleeSavedArea1Offset();
364 else if (AFI->isGPRCalleeSavedArea2Frame(FrameIndex))
365 Offset -= AFI->getGPRCalleeSavedArea2Offset();
366 else if (hasFP(MF)) {
367 assert(SPAdj == 0 && "Unexpected");
368 // There is alloca()'s in this function, must reference off the frame
370 FrameReg = getFrameRegister(MF);
371 Offset -= AFI->getFramePtrSpillOffset();
374 unsigned Opcode = MI.getOpcode();
375 const TargetInstrDesc &Desc = MI.getDesc();
376 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
378 if (Opcode == ARM::tADDrSPi) {
379 Offset += MI.getOperand(i+1).getImm();
381 // Can't use tADDrSPi if it's based off the frame pointer.
382 unsigned NumBits = 0;
384 if (FrameReg != ARM::SP) {
385 Opcode = ARM::tADDi3;
386 MI.setDesc(TII.get(ARM::tADDi3));
391 assert((Offset & 3) == 0 &&
392 "Thumb add/sub sp, #imm immediate must be multiple of 4!");
396 // Turn it into a move.
397 MI.setDesc(TII.get(ARM::tMOVhir2lor));
398 MI.getOperand(i).ChangeToRegister(FrameReg, false);
399 MI.RemoveOperand(i+1);
403 // Common case: small offset, fits into instruction.
404 unsigned Mask = (1 << NumBits) - 1;
405 if (((Offset / Scale) & ~Mask) == 0) {
406 // Replace the FrameIndex with sp / fp
407 MI.getOperand(i).ChangeToRegister(FrameReg, false);
408 MI.getOperand(i+1).ChangeToImmediate(Offset / Scale);
412 unsigned DestReg = MI.getOperand(0).getReg();
413 unsigned Bytes = (Offset > 0) ? Offset : -Offset;
414 unsigned NumMIs = calcNumMI(Opcode, 0, Bytes, NumBits, Scale);
415 // MI would expand into a large number of instructions. Don't try to
416 // simplify the immediate.
418 emitThumbRegPlusImmediate(MBB, II, DestReg, FrameReg, Offset, TII,
425 // Translate r0 = add sp, imm to
426 // r0 = add sp, 255*4
427 // r0 = add r0, (imm - 255*4)
428 MI.getOperand(i).ChangeToRegister(FrameReg, false);
429 MI.getOperand(i+1).ChangeToImmediate(Mask);
430 Offset = (Offset - Mask * Scale);
431 MachineBasicBlock::iterator NII = next(II);
432 emitThumbRegPlusImmediate(MBB, NII, DestReg, DestReg, Offset, TII,
435 // Translate r0 = add sp, -imm to
436 // r0 = -imm (this is then translated into a series of instructons)
438 emitThumbConstant(MBB, II, DestReg, Offset, TII, *this, dl);
439 MI.setDesc(TII.get(ARM::tADDhirr));
440 MI.getOperand(i).ChangeToRegister(DestReg, false, false, true);
441 MI.getOperand(i+1).ChangeToRegister(FrameReg, false);
447 unsigned NumBits = 0;
450 case ARMII::AddrModeT1_s: {
452 InstrOffs = MI.getOperand(ImmIdx).getImm();
453 NumBits = (FrameReg == ARM::SP) ? 8 : 5;
458 LLVM_UNREACHABLE("Unsupported addressing mode!");
462 Offset += InstrOffs * Scale;
463 assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
465 // Common case: small offset, fits into instruction.
466 MachineOperand &ImmOp = MI.getOperand(ImmIdx);
467 int ImmedOffset = Offset / Scale;
468 unsigned Mask = (1 << NumBits) - 1;
469 if ((unsigned)Offset <= Mask * Scale) {
470 // Replace the FrameIndex with sp
471 MI.getOperand(i).ChangeToRegister(FrameReg, false);
472 ImmOp.ChangeToImmediate(ImmedOffset);
476 bool isThumSpillRestore = Opcode == ARM::tRestore || Opcode == ARM::tSpill;
477 if (AddrMode == ARMII::AddrModeT1_s) {
478 // Thumb tLDRspi, tSTRspi. These will change to instructions that use
479 // a different base register.
481 Mask = (1 << NumBits) - 1;
483 // If this is a thumb spill / restore, we will be using a constpool load to
484 // materialize the offset.
485 if (AddrMode == ARMII::AddrModeT1_s && isThumSpillRestore)
486 ImmOp.ChangeToImmediate(0);
488 // Otherwise, it didn't fit. Pull in what we can to simplify the immed.
489 ImmedOffset = ImmedOffset & Mask;
490 ImmOp.ChangeToImmediate(ImmedOffset);
491 Offset &= ~(Mask*Scale);
495 // If we get here, the immediate doesn't fit into the instruction. We folded
496 // as much as possible above, handle the rest, providing a register that is
498 assert(Offset && "This code isn't needed if offset already handled!");
500 if (Desc.mayLoad()) {
501 // Use the destination register to materialize sp + offset.
502 unsigned TmpReg = MI.getOperand(0).getReg();
504 if (Opcode == ARM::tRestore) {
505 if (FrameReg == ARM::SP)
506 emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,
507 Offset, false, TII, *this, dl);
509 emitLoadConstPool(MBB, II, dl, TmpReg, Offset);
513 emitThumbRegPlusImmediate(MBB, II, TmpReg, FrameReg, Offset, TII,
515 MI.setDesc(TII.get(ARM::tLDR));
516 MI.getOperand(i).ChangeToRegister(TmpReg, false, false, true);
518 // Use [reg, reg] addrmode.
519 MI.addOperand(MachineOperand::CreateReg(FrameReg, false));
520 else // tLDR has an extra register operand.
521 MI.addOperand(MachineOperand::CreateReg(0, false));
522 } else if (Desc.mayStore()) {
523 // FIXME! This is horrific!!! We need register scavenging.
524 // Our temporary workaround has marked r3 unavailable. Of course, r3 is
525 // also a ABI register so it's possible that is is the register that is
526 // being storing here. If that's the case, we do the following:
528 // Use r2 to materialize sp + offset
531 unsigned ValReg = MI.getOperand(0).getReg();
532 unsigned TmpReg = ARM::R3;
534 if (ValReg == ARM::R3) {
535 BuildMI(MBB, II, dl, TII.get(ARM::tMOVlor2hir), ARM::R12)
536 .addReg(ARM::R2, RegState::Kill);
539 if (TmpReg == ARM::R3 && AFI->isR3LiveIn())
540 BuildMI(MBB, II, dl, TII.get(ARM::tMOVlor2hir), ARM::R12)
541 .addReg(ARM::R3, RegState::Kill);
542 if (Opcode == ARM::tSpill) {
543 if (FrameReg == ARM::SP)
544 emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,
545 Offset, false, TII, *this, dl);
547 emitLoadConstPool(MBB, II, dl, TmpReg, Offset);
551 emitThumbRegPlusImmediate(MBB, II, TmpReg, FrameReg, Offset, TII,
553 MI.setDesc(TII.get(ARM::tSTR));
554 MI.getOperand(i).ChangeToRegister(TmpReg, false, false, true);
555 if (UseRR) // Use [reg, reg] addrmode.
556 MI.addOperand(MachineOperand::CreateReg(FrameReg, false));
557 else // tSTR has an extra register operand.
558 MI.addOperand(MachineOperand::CreateReg(0, false));
560 MachineBasicBlock::iterator NII = next(II);
561 if (ValReg == ARM::R3)
562 BuildMI(MBB, NII, dl, TII.get(ARM::tMOVhir2lor), ARM::R2)
563 .addReg(ARM::R12, RegState::Kill);
564 if (TmpReg == ARM::R3 && AFI->isR3LiveIn())
565 BuildMI(MBB, NII, dl, TII.get(ARM::tMOVhir2lor), ARM::R3)
566 .addReg(ARM::R12, RegState::Kill);
568 assert(false && "Unexpected opcode!");
571 void Thumb1RegisterInfo::emitPrologue(MachineFunction &MF) const {
572 MachineBasicBlock &MBB = MF.front();
573 MachineBasicBlock::iterator MBBI = MBB.begin();
574 MachineFrameInfo *MFI = MF.getFrameInfo();
575 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
576 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
577 unsigned NumBytes = MFI->getStackSize();
578 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
579 DebugLoc dl = (MBBI != MBB.end() ?
580 MBBI->getDebugLoc() : DebugLoc::getUnknownLoc());
582 // Check if R3 is live in. It might have to be used as a scratch register.
583 for (MachineRegisterInfo::livein_iterator I =MF.getRegInfo().livein_begin(),
584 E = MF.getRegInfo().livein_end(); I != E; ++I) {
585 if (I->first == ARM::R3) {
586 AFI->setR3IsLiveIn(true);
591 // Thumb add/sub sp, imm8 instructions implicitly multiply the offset by 4.
592 NumBytes = (NumBytes + 3) & ~3;
593 MFI->setStackSize(NumBytes);
595 // Determine the sizes of each callee-save spill areas and record which frame
596 // belongs to which callee-save spill areas.
597 unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
598 int FramePtrSpillFI = 0;
601 emitSPUpdate(MBB, MBBI, TII, dl, *this, -VARegSaveSize);
603 if (!AFI->hasStackFrame()) {
605 emitSPUpdate(MBB, MBBI, TII, dl, *this, -NumBytes);
609 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
610 unsigned Reg = CSI[i].getReg();
611 int FI = CSI[i].getFrameIdx();
619 FramePtrSpillFI = FI;
620 AFI->addGPRCalleeSavedArea1Frame(FI);
628 FramePtrSpillFI = FI;
629 if (STI.isTargetDarwin()) {
630 AFI->addGPRCalleeSavedArea2Frame(FI);
633 AFI->addGPRCalleeSavedArea1Frame(FI);
638 AFI->addDPRCalleeSavedAreaFrame(FI);
643 if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPUSH) {
645 if (MBBI != MBB.end())
646 dl = MBBI->getDebugLoc();
649 // Darwin ABI requires FP to point to the stack slot that contains the
651 if (STI.isTargetDarwin() || hasFP(MF)) {
652 MachineInstrBuilder MIB =
653 BuildMI(MBB, MBBI, dl, TII.get(ARM::tADDrSPi), FramePtr)
654 .addFrameIndex(FramePtrSpillFI).addImm(0);
657 // Determine starting offsets of spill areas.
658 unsigned DPRCSOffset = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize);
659 unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize;
660 unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size;
661 AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) + NumBytes);
662 AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
663 AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
664 AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
666 NumBytes = DPRCSOffset;
668 // Insert it after all the callee-save spills.
669 emitSPUpdate(MBB, MBBI, TII, dl, *this, -NumBytes);
672 if (STI.isTargetELF() && hasFP(MF)) {
673 MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() -
674 AFI->getFramePtrSpillOffset());
677 AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
678 AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
679 AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
682 static bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) {
683 for (unsigned i = 0; CSRegs[i]; ++i)
684 if (Reg == CSRegs[i])
689 static bool isCSRestore(MachineInstr *MI, const unsigned *CSRegs) {
690 return (MI->getOpcode() == ARM::tRestore &&
691 MI->getOperand(1).isFI() &&
692 isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs));
695 void Thumb1RegisterInfo::emitEpilogue(MachineFunction &MF,
696 MachineBasicBlock &MBB) const {
697 MachineBasicBlock::iterator MBBI = prior(MBB.end());
698 assert((MBBI->getOpcode() == ARM::tBX_RET ||
699 MBBI->getOpcode() == ARM::tPOP_RET) &&
700 "Can only insert epilog into returning blocks");
701 DebugLoc dl = MBBI->getDebugLoc();
702 MachineFrameInfo *MFI = MF.getFrameInfo();
703 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
704 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
705 int NumBytes = (int)MFI->getStackSize();
707 if (!AFI->hasStackFrame()) {
709 emitSPUpdate(MBB, MBBI, TII, dl, *this, NumBytes);
711 // Unwind MBBI to point to first LDR / FLDD.
712 const unsigned *CSRegs = getCalleeSavedRegs();
713 if (MBBI != MBB.begin()) {
716 while (MBBI != MBB.begin() && isCSRestore(MBBI, CSRegs));
717 if (!isCSRestore(MBBI, CSRegs))
721 // Move SP to start of FP callee save spill area.
722 NumBytes -= (AFI->getGPRCalleeSavedArea1Size() +
723 AFI->getGPRCalleeSavedArea2Size() +
724 AFI->getDPRCalleeSavedAreaSize());
727 NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
728 // Reset SP based on frame pointer only if the stack frame extends beyond
729 // frame pointer stack slot or target is ELF and the function has FP.
731 emitThumbRegPlusImmediate(MBB, MBBI, ARM::SP, FramePtr, -NumBytes,
734 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVlor2hir), ARM::SP)
737 if (MBBI->getOpcode() == ARM::tBX_RET &&
738 &MBB.front() != MBBI &&
739 prior(MBBI)->getOpcode() == ARM::tPOP) {
740 MachineBasicBlock::iterator PMBBI = prior(MBBI);
741 emitSPUpdate(MBB, PMBBI, TII, dl, *this, NumBytes);
743 emitSPUpdate(MBB, MBBI, TII, dl, *this, NumBytes);
748 // Epilogue for vararg functions: pop LR to R3 and branch off it.
749 // FIXME: Verify this is still ok when R3 is no longer being reserved.
750 BuildMI(MBB, MBBI, dl, TII.get(ARM::tPOP)).addReg(ARM::R3);
752 emitSPUpdate(MBB, MBBI, TII, dl, *this, VARegSaveSize);
754 BuildMI(MBB, MBBI, dl, TII.get(ARM::tBX_RET_vararg)).addReg(ARM::R3);