1 //===- Thumb1RegisterInfo.cpp - Thumb-1 Register Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Thumb-1 implementation of the TargetRegisterInfo class.
12 //===----------------------------------------------------------------------===//
15 #include "ARMAddressingModes.h"
16 #include "ARMMachineFunctionInfo.h"
17 #include "ARMSubtarget.h"
18 #include "Thumb1InstrInfo.h"
19 #include "Thumb1RegisterInfo.h"
20 #include "llvm/Constants.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/CodeGen/MachineConstantPool.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/CodeGen/MachineFunction.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineLocation.h"
27 #include "llvm/CodeGen/MachineRegisterInfo.h"
28 #include "llvm/Target/TargetFrameInfo.h"
29 #include "llvm/Target/TargetMachine.h"
30 #include "llvm/ADT/BitVector.h"
31 #include "llvm/ADT/SmallVector.h"
32 #include "llvm/Support/CommandLine.h"
33 #include "llvm/Support/ErrorHandling.h"
37 ThumbRegScavenging("enable-thumb-reg-scavenging",
39 cl::desc("Enable register scavenging on Thumb"));
41 Thumb1RegisterInfo::Thumb1RegisterInfo(const ARMBaseInstrInfo &tii,
42 const ARMSubtarget &sti)
43 : ARMBaseRegisterInfo(tii, sti) {
46 /// emitLoadConstPool - Emits a load from constpool to materialize the
47 /// specified immediate.
48 void Thumb1RegisterInfo::emitLoadConstPool(MachineBasicBlock &MBB,
49 MachineBasicBlock::iterator &MBBI,
50 const TargetInstrInfo *TII, DebugLoc dl,
51 unsigned DestReg, int Val,
52 ARMCC::CondCodes Pred,
53 unsigned PredReg) const {
54 MachineFunction &MF = *MBB.getParent();
55 MachineConstantPool *ConstantPool = MF.getConstantPool();
56 Constant *C = ConstantInt::get(Type::Int32Ty, Val);
57 unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
59 BuildMI(MBB, MBBI, dl, TII->get(ARM::tLDRcp), DestReg)
60 .addConstantPoolIndex(Idx);
63 const TargetRegisterClass*
64 Thumb1RegisterInfo::getPhysicalRegisterRegClass(unsigned Reg, MVT VT) const {
65 if (isARMLowRegister(Reg))
66 return ARM::tGPRRegisterClass;
70 case ARM::R8: case ARM::R9: case ARM::R10: case ARM::R11:
71 case ARM::R12: case ARM::SP: case ARM::LR: case ARM::PC:
72 return ARM::GPRRegisterClass;
75 return TargetRegisterInfo::getPhysicalRegisterRegClass(Reg, VT);
79 Thumb1RegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const {
80 return ThumbRegScavenging;
83 bool Thumb1RegisterInfo::hasReservedCallFrame(MachineFunction &MF) const {
84 const MachineFrameInfo *FFI = MF.getFrameInfo();
85 unsigned CFSize = FFI->getMaxCallFrameSize();
86 // It's not always a good idea to include the call frame as part of the
87 // stack frame. ARM (especially Thumb) has small immediate offset to
88 // address the stack frame. So a large call frame can cause poor codegen
89 // and may even makes it impossible to scavenge a register.
90 if (CFSize >= ((1 << 8) - 1) * 4 / 2) // Half of imm8 * 4
93 return !MF.getFrameInfo()->hasVarSizedObjects();
96 /// emitThumbRegPlusImmInReg - Emits a series of instructions to materialize
97 /// a destreg = basereg + immediate in Thumb code. Materialize the immediate
98 /// in a register using mov / mvn sequences or load the immediate from a
101 void emitThumbRegPlusImmInReg(MachineBasicBlock &MBB,
102 MachineBasicBlock::iterator &MBBI,
103 unsigned DestReg, unsigned BaseReg,
104 int NumBytes, bool CanChangeCC,
105 const TargetInstrInfo &TII,
106 const Thumb1RegisterInfo& MRI,
108 bool isHigh = !isARMLowRegister(DestReg) ||
109 (BaseReg != 0 && !isARMLowRegister(BaseReg));
111 // Subtract doesn't have high register version. Load the negative value
112 // if either base or dest register is a high register. Also, if do not
113 // issue sub as part of the sequence if condition register is to be
115 if (NumBytes < 0 && !isHigh && CanChangeCC) {
117 NumBytes = -NumBytes;
119 unsigned LdReg = DestReg;
120 if (DestReg == ARM::SP) {
121 assert(BaseReg == ARM::SP && "Unexpected!");
123 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVlor2hir), ARM::R12)
124 .addReg(ARM::R3, RegState::Kill);
127 if (NumBytes <= 255 && NumBytes >= 0)
128 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), LdReg).addImm(NumBytes);
129 else if (NumBytes < 0 && NumBytes >= -255) {
130 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), LdReg).addImm(NumBytes);
131 BuildMI(MBB, MBBI, dl, TII.get(ARM::tNEG), LdReg)
132 .addReg(LdReg, RegState::Kill);
134 MRI.emitLoadConstPool(MBB, MBBI, &TII, dl, LdReg, NumBytes);
137 int Opc = (isSub) ? ARM::tSUBrr : (isHigh ? ARM::tADDhirr : ARM::tADDrr);
138 const MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl,
139 TII.get(Opc), DestReg);
140 if (DestReg == ARM::SP || isSub)
141 MIB.addReg(BaseReg).addReg(LdReg, RegState::Kill);
143 MIB.addReg(LdReg).addReg(BaseReg, RegState::Kill);
144 if (DestReg == ARM::SP)
145 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVhir2lor), ARM::R3)
146 .addReg(ARM::R12, RegState::Kill);
149 /// calcNumMI - Returns the number of instructions required to materialize
150 /// the specific add / sub r, c instruction.
151 static unsigned calcNumMI(int Opc, int ExtraOpc, unsigned Bytes,
152 unsigned NumBits, unsigned Scale) {
154 unsigned Chunk = ((1 << NumBits) - 1) * Scale;
156 if (Opc == ARM::tADDrSPi) {
157 unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes;
161 Scale = 1; // Followed by a number of tADDi8.
162 Chunk = ((1 << NumBits) - 1) * Scale;
165 NumMIs += Bytes / Chunk;
166 if ((Bytes % Chunk) != 0)
173 /// emitThumbRegPlusImmediate - Emits a series of instructions to materialize
174 /// a destreg = basereg + immediate in Thumb code.
176 void emitThumbRegPlusImmediate(MachineBasicBlock &MBB,
177 MachineBasicBlock::iterator &MBBI,
178 unsigned DestReg, unsigned BaseReg,
179 int NumBytes, const TargetInstrInfo &TII,
180 const Thumb1RegisterInfo& MRI,
182 bool isSub = NumBytes < 0;
183 unsigned Bytes = (unsigned)NumBytes;
184 if (isSub) Bytes = -NumBytes;
185 bool isMul4 = (Bytes & 3) == 0;
186 bool isTwoAddr = false;
187 bool DstNotEqBase = false;
188 unsigned NumBits = 1;
193 if (DestReg == BaseReg && BaseReg == ARM::SP) {
194 assert(isMul4 && "Thumb sp inc / dec size must be multiple of 4!");
197 Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
199 } else if (!isSub && BaseReg == ARM::SP) {
202 // r1 = add sp, 100 * 4
206 ExtraOpc = ARM::tADDi3;
215 if (DestReg != BaseReg)
218 Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8;
222 unsigned NumMIs = calcNumMI(Opc, ExtraOpc, Bytes, NumBits, Scale);
223 unsigned Threshold = (DestReg == ARM::SP) ? 3 : 2;
224 if (NumMIs > Threshold) {
225 // This will expand into too many instructions. Load the immediate from a
227 emitThumbRegPlusImmInReg(MBB, MBBI, DestReg, BaseReg, NumBytes, true, TII,
233 if (isARMLowRegister(DestReg) && isARMLowRegister(BaseReg)) {
234 // If both are low registers, emit DestReg = add BaseReg, max(Imm, 7)
235 unsigned Chunk = (1 << 3) - 1;
236 unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes;
238 BuildMI(MBB, MBBI, dl,TII.get(isSub ? ARM::tSUBi3 : ARM::tADDi3), DestReg)
239 .addReg(BaseReg, RegState::Kill).addImm(ThisVal);
241 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), DestReg)
242 .addReg(BaseReg, RegState::Kill);
247 unsigned Chunk = ((1 << NumBits) - 1) * Scale;
249 unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes;
252 // Build the new tADD / tSUB.
254 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
255 .addReg(DestReg).addImm(ThisVal);
257 bool isKill = BaseReg != ARM::SP;
258 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
259 .addReg(BaseReg, getKillRegState(isKill)).addImm(ThisVal);
262 if (Opc == ARM::tADDrSPi) {
268 Chunk = ((1 << NumBits) - 1) * Scale;
269 Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8;
276 BuildMI(MBB, MBBI, dl, TII.get(ExtraOpc), DestReg)
277 .addReg(DestReg, RegState::Kill)
278 .addImm(((unsigned)NumBytes) & 3);
281 static void emitSPUpdate(MachineBasicBlock &MBB,
282 MachineBasicBlock::iterator &MBBI,
283 const TargetInstrInfo &TII, DebugLoc dl,
284 const Thumb1RegisterInfo &MRI,
286 emitThumbRegPlusImmediate(MBB, MBBI, ARM::SP, ARM::SP, NumBytes, TII,
290 void Thumb1RegisterInfo::
291 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
292 MachineBasicBlock::iterator I) const {
293 if (!hasReservedCallFrame(MF)) {
294 // If we have alloca, convert as follows:
295 // ADJCALLSTACKDOWN -> sub, sp, sp, amount
296 // ADJCALLSTACKUP -> add, sp, sp, amount
297 MachineInstr *Old = I;
298 DebugLoc dl = Old->getDebugLoc();
299 unsigned Amount = Old->getOperand(0).getImm();
301 // We need to keep the stack aligned properly. To do this, we round the
302 // amount of space needed for the outgoing arguments up to the next
303 // alignment boundary.
304 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
305 Amount = (Amount+Align-1)/Align*Align;
307 // Replace the pseudo instruction with a new instruction...
308 unsigned Opc = Old->getOpcode();
309 if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
310 emitSPUpdate(MBB, I, TII, dl, *this, -Amount);
312 assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
313 emitSPUpdate(MBB, I, TII, dl, *this, Amount);
320 /// emitThumbConstant - Emit a series of instructions to materialize a
322 static void emitThumbConstant(MachineBasicBlock &MBB,
323 MachineBasicBlock::iterator &MBBI,
324 unsigned DestReg, int Imm,
325 const TargetInstrInfo &TII,
326 const Thumb1RegisterInfo& MRI,
328 bool isSub = Imm < 0;
329 if (isSub) Imm = -Imm;
331 int Chunk = (1 << 8) - 1;
332 int ThisVal = (Imm > Chunk) ? Chunk : Imm;
334 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), DestReg).addImm(ThisVal);
336 emitThumbRegPlusImmediate(MBB, MBBI, DestReg, DestReg, Imm, TII, MRI, dl);
338 BuildMI(MBB, MBBI, dl, TII.get(ARM::tNEG), DestReg)
339 .addReg(DestReg, RegState::Kill);
342 void Thumb1RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
343 int SPAdj, RegScavenger *RS) const{
345 MachineInstr &MI = *II;
346 MachineBasicBlock &MBB = *MI.getParent();
347 MachineFunction &MF = *MBB.getParent();
348 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
349 DebugLoc dl = MI.getDebugLoc();
351 while (!MI.getOperand(i).isFI()) {
353 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
356 unsigned FrameReg = ARM::SP;
357 int FrameIndex = MI.getOperand(i).getIndex();
358 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
359 MF.getFrameInfo()->getStackSize() + SPAdj;
361 if (AFI->isGPRCalleeSavedArea1Frame(FrameIndex))
362 Offset -= AFI->getGPRCalleeSavedArea1Offset();
363 else if (AFI->isGPRCalleeSavedArea2Frame(FrameIndex))
364 Offset -= AFI->getGPRCalleeSavedArea2Offset();
365 else if (hasFP(MF)) {
366 assert(SPAdj == 0 && "Unexpected");
367 // There is alloca()'s in this function, must reference off the frame
369 FrameReg = getFrameRegister(MF);
370 Offset -= AFI->getFramePtrSpillOffset();
373 unsigned Opcode = MI.getOpcode();
374 const TargetInstrDesc &Desc = MI.getDesc();
375 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
377 if (Opcode == ARM::tADDrSPi) {
378 Offset += MI.getOperand(i+1).getImm();
380 // Can't use tADDrSPi if it's based off the frame pointer.
381 unsigned NumBits = 0;
383 if (FrameReg != ARM::SP) {
384 Opcode = ARM::tADDi3;
385 MI.setDesc(TII.get(ARM::tADDi3));
390 assert((Offset & 3) == 0 &&
391 "Thumb add/sub sp, #imm immediate must be multiple of 4!");
395 // Turn it into a move.
396 MI.setDesc(TII.get(ARM::tMOVhir2lor));
397 MI.getOperand(i).ChangeToRegister(FrameReg, false);
398 MI.RemoveOperand(i+1);
402 // Common case: small offset, fits into instruction.
403 unsigned Mask = (1 << NumBits) - 1;
404 if (((Offset / Scale) & ~Mask) == 0) {
405 // Replace the FrameIndex with sp / fp
406 MI.getOperand(i).ChangeToRegister(FrameReg, false);
407 MI.getOperand(i+1).ChangeToImmediate(Offset / Scale);
411 unsigned DestReg = MI.getOperand(0).getReg();
412 unsigned Bytes = (Offset > 0) ? Offset : -Offset;
413 unsigned NumMIs = calcNumMI(Opcode, 0, Bytes, NumBits, Scale);
414 // MI would expand into a large number of instructions. Don't try to
415 // simplify the immediate.
417 emitThumbRegPlusImmediate(MBB, II, DestReg, FrameReg, Offset, TII,
424 // Translate r0 = add sp, imm to
425 // r0 = add sp, 255*4
426 // r0 = add r0, (imm - 255*4)
427 MI.getOperand(i).ChangeToRegister(FrameReg, false);
428 MI.getOperand(i+1).ChangeToImmediate(Mask);
429 Offset = (Offset - Mask * Scale);
430 MachineBasicBlock::iterator NII = next(II);
431 emitThumbRegPlusImmediate(MBB, NII, DestReg, DestReg, Offset, TII,
434 // Translate r0 = add sp, -imm to
435 // r0 = -imm (this is then translated into a series of instructons)
437 emitThumbConstant(MBB, II, DestReg, Offset, TII, *this, dl);
438 MI.setDesc(TII.get(ARM::tADDhirr));
439 MI.getOperand(i).ChangeToRegister(DestReg, false, false, true);
440 MI.getOperand(i+1).ChangeToRegister(FrameReg, false);
446 unsigned NumBits = 0;
449 case ARMII::AddrModeT1_s: {
451 InstrOffs = MI.getOperand(ImmIdx).getImm();
452 NumBits = (FrameReg == ARM::SP) ? 8 : 5;
457 LLVM_UNREACHABLE("Unsupported addressing mode!");
461 Offset += InstrOffs * Scale;
462 assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
464 // Common case: small offset, fits into instruction.
465 MachineOperand &ImmOp = MI.getOperand(ImmIdx);
466 int ImmedOffset = Offset / Scale;
467 unsigned Mask = (1 << NumBits) - 1;
468 if ((unsigned)Offset <= Mask * Scale) {
469 // Replace the FrameIndex with sp
470 MI.getOperand(i).ChangeToRegister(FrameReg, false);
471 ImmOp.ChangeToImmediate(ImmedOffset);
475 bool isThumSpillRestore = Opcode == ARM::tRestore || Opcode == ARM::tSpill;
476 if (AddrMode == ARMII::AddrModeT1_s) {
477 // Thumb tLDRspi, tSTRspi. These will change to instructions that use
478 // a different base register.
480 Mask = (1 << NumBits) - 1;
482 // If this is a thumb spill / restore, we will be using a constpool load to
483 // materialize the offset.
484 if (AddrMode == ARMII::AddrModeT1_s && isThumSpillRestore)
485 ImmOp.ChangeToImmediate(0);
487 // Otherwise, it didn't fit. Pull in what we can to simplify the immed.
488 ImmedOffset = ImmedOffset & Mask;
489 ImmOp.ChangeToImmediate(ImmedOffset);
490 Offset &= ~(Mask*Scale);
494 // If we get here, the immediate doesn't fit into the instruction. We folded
495 // as much as possible above, handle the rest, providing a register that is
497 assert(Offset && "This code isn't needed if offset already handled!");
499 if (Desc.mayLoad()) {
500 // Use the destination register to materialize sp + offset.
501 unsigned TmpReg = MI.getOperand(0).getReg();
503 if (Opcode == ARM::tRestore) {
504 if (FrameReg == ARM::SP)
505 emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,
506 Offset, false, TII, *this, dl);
508 emitLoadConstPool(MBB, II, &TII, dl, TmpReg, Offset);
512 emitThumbRegPlusImmediate(MBB, II, TmpReg, FrameReg, Offset, TII,
514 MI.setDesc(TII.get(ARM::tLDR));
515 MI.getOperand(i).ChangeToRegister(TmpReg, false, false, true);
517 // Use [reg, reg] addrmode.
518 MI.addOperand(MachineOperand::CreateReg(FrameReg, false));
519 else // tLDR has an extra register operand.
520 MI.addOperand(MachineOperand::CreateReg(0, false));
521 } else if (Desc.mayStore()) {
522 // FIXME! This is horrific!!! We need register scavenging.
523 // Our temporary workaround has marked r3 unavailable. Of course, r3 is
524 // also a ABI register so it's possible that is is the register that is
525 // being storing here. If that's the case, we do the following:
527 // Use r2 to materialize sp + offset
530 unsigned ValReg = MI.getOperand(0).getReg();
531 unsigned TmpReg = ARM::R3;
533 if (ValReg == ARM::R3) {
534 BuildMI(MBB, II, dl, TII.get(ARM::tMOVlor2hir), ARM::R12)
535 .addReg(ARM::R2, RegState::Kill);
538 if (TmpReg == ARM::R3 && AFI->isR3LiveIn())
539 BuildMI(MBB, II, dl, TII.get(ARM::tMOVlor2hir), ARM::R12)
540 .addReg(ARM::R3, RegState::Kill);
541 if (Opcode == ARM::tSpill) {
542 if (FrameReg == ARM::SP)
543 emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,
544 Offset, false, TII, *this, dl);
546 emitLoadConstPool(MBB, II, &TII, dl, TmpReg, Offset);
550 emitThumbRegPlusImmediate(MBB, II, TmpReg, FrameReg, Offset, TII,
552 MI.setDesc(TII.get(ARM::tSTR));
553 MI.getOperand(i).ChangeToRegister(TmpReg, false, false, true);
554 if (UseRR) // Use [reg, reg] addrmode.
555 MI.addOperand(MachineOperand::CreateReg(FrameReg, false));
556 else // tSTR has an extra register operand.
557 MI.addOperand(MachineOperand::CreateReg(0, false));
559 MachineBasicBlock::iterator NII = next(II);
560 if (ValReg == ARM::R3)
561 BuildMI(MBB, NII, dl, TII.get(ARM::tMOVhir2lor), ARM::R2)
562 .addReg(ARM::R12, RegState::Kill);
563 if (TmpReg == ARM::R3 && AFI->isR3LiveIn())
564 BuildMI(MBB, NII, dl, TII.get(ARM::tMOVhir2lor), ARM::R3)
565 .addReg(ARM::R12, RegState::Kill);
567 assert(false && "Unexpected opcode!");
570 void Thumb1RegisterInfo::emitPrologue(MachineFunction &MF) const {
571 MachineBasicBlock &MBB = MF.front();
572 MachineBasicBlock::iterator MBBI = MBB.begin();
573 MachineFrameInfo *MFI = MF.getFrameInfo();
574 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
575 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
576 unsigned NumBytes = MFI->getStackSize();
577 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
578 DebugLoc dl = (MBBI != MBB.end() ?
579 MBBI->getDebugLoc() : DebugLoc::getUnknownLoc());
581 // Check if R3 is live in. It might have to be used as a scratch register.
582 for (MachineRegisterInfo::livein_iterator I =MF.getRegInfo().livein_begin(),
583 E = MF.getRegInfo().livein_end(); I != E; ++I) {
584 if (I->first == ARM::R3) {
585 AFI->setR3IsLiveIn(true);
590 // Thumb add/sub sp, imm8 instructions implicitly multiply the offset by 4.
591 NumBytes = (NumBytes + 3) & ~3;
592 MFI->setStackSize(NumBytes);
594 // Determine the sizes of each callee-save spill areas and record which frame
595 // belongs to which callee-save spill areas.
596 unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
597 int FramePtrSpillFI = 0;
600 emitSPUpdate(MBB, MBBI, TII, dl, *this, -VARegSaveSize);
602 if (!AFI->hasStackFrame()) {
604 emitSPUpdate(MBB, MBBI, TII, dl, *this, -NumBytes);
608 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
609 unsigned Reg = CSI[i].getReg();
610 int FI = CSI[i].getFrameIdx();
618 FramePtrSpillFI = FI;
619 AFI->addGPRCalleeSavedArea1Frame(FI);
627 FramePtrSpillFI = FI;
628 if (STI.isTargetDarwin()) {
629 AFI->addGPRCalleeSavedArea2Frame(FI);
632 AFI->addGPRCalleeSavedArea1Frame(FI);
637 AFI->addDPRCalleeSavedAreaFrame(FI);
642 if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPUSH) {
644 if (MBBI != MBB.end())
645 dl = MBBI->getDebugLoc();
648 // Darwin ABI requires FP to point to the stack slot that contains the
650 if (STI.isTargetDarwin() || hasFP(MF)) {
651 MachineInstrBuilder MIB =
652 BuildMI(MBB, MBBI, dl, TII.get(ARM::tADDrSPi), FramePtr)
653 .addFrameIndex(FramePtrSpillFI).addImm(0);
656 // Determine starting offsets of spill areas.
657 unsigned DPRCSOffset = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize);
658 unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize;
659 unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size;
660 AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) + NumBytes);
661 AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
662 AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
663 AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
665 NumBytes = DPRCSOffset;
667 // Insert it after all the callee-save spills.
668 emitSPUpdate(MBB, MBBI, TII, dl, *this, -NumBytes);
671 if (STI.isTargetELF() && hasFP(MF)) {
672 MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() -
673 AFI->getFramePtrSpillOffset());
676 AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
677 AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
678 AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
681 static bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) {
682 for (unsigned i = 0; CSRegs[i]; ++i)
683 if (Reg == CSRegs[i])
688 static bool isCSRestore(MachineInstr *MI, const unsigned *CSRegs) {
689 return (MI->getOpcode() == ARM::tRestore &&
690 MI->getOperand(1).isFI() &&
691 isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs));
694 void Thumb1RegisterInfo::emitEpilogue(MachineFunction &MF,
695 MachineBasicBlock &MBB) const {
696 MachineBasicBlock::iterator MBBI = prior(MBB.end());
697 assert((MBBI->getOpcode() == ARM::tBX_RET ||
698 MBBI->getOpcode() == ARM::tPOP_RET) &&
699 "Can only insert epilog into returning blocks");
700 DebugLoc dl = MBBI->getDebugLoc();
701 MachineFrameInfo *MFI = MF.getFrameInfo();
702 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
703 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
704 int NumBytes = (int)MFI->getStackSize();
706 if (!AFI->hasStackFrame()) {
708 emitSPUpdate(MBB, MBBI, TII, dl, *this, NumBytes);
710 // Unwind MBBI to point to first LDR / FLDD.
711 const unsigned *CSRegs = getCalleeSavedRegs();
712 if (MBBI != MBB.begin()) {
715 while (MBBI != MBB.begin() && isCSRestore(MBBI, CSRegs));
716 if (!isCSRestore(MBBI, CSRegs))
720 // Move SP to start of FP callee save spill area.
721 NumBytes -= (AFI->getGPRCalleeSavedArea1Size() +
722 AFI->getGPRCalleeSavedArea2Size() +
723 AFI->getDPRCalleeSavedAreaSize());
726 NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
727 // Reset SP based on frame pointer only if the stack frame extends beyond
728 // frame pointer stack slot or target is ELF and the function has FP.
730 emitThumbRegPlusImmediate(MBB, MBBI, ARM::SP, FramePtr, -NumBytes,
733 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVlor2hir), ARM::SP)
736 if (MBBI->getOpcode() == ARM::tBX_RET &&
737 &MBB.front() != MBBI &&
738 prior(MBBI)->getOpcode() == ARM::tPOP) {
739 MachineBasicBlock::iterator PMBBI = prior(MBBI);
740 emitSPUpdate(MBB, PMBBI, TII, dl, *this, NumBytes);
742 emitSPUpdate(MBB, MBBI, TII, dl, *this, NumBytes);
747 // Epilogue for vararg functions: pop LR to R3 and branch off it.
748 // FIXME: Verify this is still ok when R3 is no longer being reserved.
749 BuildMI(MBB, MBBI, dl, TII.get(ARM::tPOP)).addReg(ARM::R3);
751 emitSPUpdate(MBB, MBBI, TII, dl, *this, VARegSaveSize);
753 BuildMI(MBB, MBBI, dl, TII.get(ARM::tBX_RET_vararg)).addReg(ARM::R3);