The BLX instruction is encoded differently than the BL, because why not? In
[oota-llvm.git] / lib / Target / ARM / Thumb1RegisterInfo.h
1 //===- Thumb1RegisterInfo.h - Thumb-1 Register Information Impl -*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the Thumb-1 implementation of the TargetRegisterInfo
11 // class.
12 //
13 //===----------------------------------------------------------------------===//
14
15 #ifndef THUMB1REGISTERINFO_H
16 #define THUMB1REGISTERINFO_H
17
18 #include "ARM.h"
19 #include "ARMRegisterInfo.h"
20 #include "llvm/Target/TargetRegisterInfo.h"
21
22 namespace llvm {
23   class ARMSubtarget;
24   class ARMBaseInstrInfo;
25   class Type;
26
27 struct Thumb1RegisterInfo : public ARMBaseRegisterInfo {
28 public:
29   Thumb1RegisterInfo(const ARMBaseInstrInfo &tii, const ARMSubtarget &STI);
30
31   /// emitLoadConstPool - Emits a load from constpool to materialize the
32   /// specified immediate.
33  void emitLoadConstPool(MachineBasicBlock &MBB,
34                         MachineBasicBlock::iterator &MBBI,
35                         DebugLoc dl,
36                         unsigned DestReg, unsigned SubIdx, int Val,
37                         ARMCC::CondCodes Pred = ARMCC::AL,
38                         unsigned PredReg = 0) const;
39
40   /// Code Generation virtual methods...
41   void eliminateCallFramePseudoInstr(MachineFunction &MF,
42                                      MachineBasicBlock &MBB,
43                                      MachineBasicBlock::iterator I) const;
44
45   // rewrite MI to access 'Offset' bytes from the FP. Update Offset to be
46   // however much remains to be handled. Return 'true' if no further
47   // work is required.
48   bool rewriteFrameIndex(MachineBasicBlock::iterator II, unsigned FrameRegIdx,
49                          unsigned FrameReg, int &Offset,
50                          const ARMBaseInstrInfo &TII) const;
51   void resolveFrameIndex(MachineBasicBlock::iterator I,
52                          unsigned BaseReg, int64_t Offset) const;
53   bool saveScavengerRegister(MachineBasicBlock &MBB,
54                              MachineBasicBlock::iterator I,
55                              MachineBasicBlock::iterator &UseMI,
56                              const TargetRegisterClass *RC,
57                              unsigned Reg) const;
58   void eliminateFrameIndex(MachineBasicBlock::iterator II,
59                            int SPAdj, RegScavenger *RS = NULL) const;
60 };
61 }
62
63 #endif // THUMB1REGISTERINFO_H