1 //===-- Thumb2ITBlockPass.cpp - Insert Thumb-2 IT blocks ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 #include "ARMMachineFunctionInfo.h"
12 #include "Thumb2InstrInfo.h"
13 #include "llvm/ADT/SmallSet.h"
14 #include "llvm/ADT/Statistic.h"
15 #include "llvm/CodeGen/MachineFunctionPass.h"
16 #include "llvm/CodeGen/MachineInstr.h"
17 #include "llvm/CodeGen/MachineInstrBuilder.h"
18 #include "llvm/CodeGen/MachineInstrBundle.h"
21 #define DEBUG_TYPE "thumb2-it"
23 STATISTIC(NumITs, "Number of IT blocks inserted");
24 STATISTIC(NumMovedInsts, "Number of predicated instructions moved");
27 class Thumb2ITBlockPass : public MachineFunctionPass {
30 Thumb2ITBlockPass() : MachineFunctionPass(ID) {}
33 const Thumb2InstrInfo *TII;
34 const TargetRegisterInfo *TRI;
37 bool runOnMachineFunction(MachineFunction &Fn) override;
39 const char *getPassName() const override {
40 return "Thumb IT blocks insertion pass";
44 bool MoveCopyOutOfITBlock(MachineInstr *MI,
45 ARMCC::CondCodes CC, ARMCC::CondCodes OCC,
46 SmallSet<unsigned, 4> &Defs,
47 SmallSet<unsigned, 4> &Uses);
48 bool InsertITInstructions(MachineBasicBlock &MBB);
50 char Thumb2ITBlockPass::ID = 0;
53 /// TrackDefUses - Tracking what registers are being defined and used by
54 /// instructions in the IT block. This also tracks "dependencies", i.e. uses
55 /// in the IT block that are defined before the IT instruction.
56 static void TrackDefUses(MachineInstr *MI,
57 SmallSet<unsigned, 4> &Defs,
58 SmallSet<unsigned, 4> &Uses,
59 const TargetRegisterInfo *TRI) {
60 SmallVector<unsigned, 4> LocalDefs;
61 SmallVector<unsigned, 4> LocalUses;
63 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
64 MachineOperand &MO = MI->getOperand(i);
67 unsigned Reg = MO.getReg();
68 if (!Reg || Reg == ARM::ITSTATE || Reg == ARM::SP)
71 LocalUses.push_back(Reg);
73 LocalDefs.push_back(Reg);
76 for (unsigned i = 0, e = LocalUses.size(); i != e; ++i) {
77 unsigned Reg = LocalUses[i];
78 for (MCSubRegIterator Subreg(Reg, TRI, /*IncludeSelf=*/true);
79 Subreg.isValid(); ++Subreg)
83 for (unsigned i = 0, e = LocalDefs.size(); i != e; ++i) {
84 unsigned Reg = LocalDefs[i];
85 for (MCSubRegIterator Subreg(Reg, TRI, /*IncludeSelf=*/true);
86 Subreg.isValid(); ++Subreg)
93 /// Clear kill flags for any uses in the given set. This will likely
94 /// conservatively remove more kill flags than are necessary, but removing them
95 /// is safer than incorrect kill flags remaining on instructions.
96 static void ClearKillFlags(MachineInstr *MI, SmallSet<unsigned, 4> &Uses) {
97 for (MachineOperand &MO : MI->operands()) {
98 if (!MO.isReg() || MO.isDef() || !MO.isKill())
100 if (!Uses.count(MO.getReg()))
106 static bool isCopy(MachineInstr *MI) {
107 switch (MI->getOpcode()) {
119 Thumb2ITBlockPass::MoveCopyOutOfITBlock(MachineInstr *MI,
120 ARMCC::CondCodes CC, ARMCC::CondCodes OCC,
121 SmallSet<unsigned, 4> &Defs,
122 SmallSet<unsigned, 4> &Uses) {
125 // llvm models select's as two-address instructions. That means a copy
126 // is inserted before a t2MOVccr, etc. If the copy is scheduled in
127 // between selects we would end up creating multiple IT blocks.
128 assert(MI->getOperand(0).getSubReg() == 0 &&
129 MI->getOperand(1).getSubReg() == 0 &&
130 "Sub-register indices still around?");
132 unsigned DstReg = MI->getOperand(0).getReg();
133 unsigned SrcReg = MI->getOperand(1).getReg();
135 // First check if it's safe to move it.
136 if (Uses.count(DstReg) || Defs.count(SrcReg))
139 // If the CPSR is defined by this copy, then we don't want to move it. E.g.,
147 // we don't want this to be converted to:
155 const MCInstrDesc &MCID = MI->getDesc();
156 if (MI->hasOptionalDef() &&
157 MI->getOperand(MCID.getNumOperands() - 1).getReg() == ARM::CPSR)
160 // Then peek at the next instruction to see if it's predicated on CC or OCC.
161 // If not, then there is nothing to be gained by moving the copy.
162 MachineBasicBlock::iterator I = MI; ++I;
163 MachineBasicBlock::iterator E = MI->getParent()->end();
164 while (I != E && I->isDebugValue())
167 unsigned NPredReg = 0;
168 ARMCC::CondCodes NCC = getITInstrPredicate(I, NPredReg);
169 if (NCC == CC || NCC == OCC)
175 bool Thumb2ITBlockPass::InsertITInstructions(MachineBasicBlock &MBB) {
176 bool Modified = false;
178 SmallSet<unsigned, 4> Defs;
179 SmallSet<unsigned, 4> Uses;
180 MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
182 MachineInstr *MI = &*MBBI;
183 DebugLoc dl = MI->getDebugLoc();
184 unsigned PredReg = 0;
185 ARMCC::CondCodes CC = getITInstrPredicate(MI, PredReg);
186 if (CC == ARMCC::AL) {
193 TrackDefUses(MI, Defs, Uses, TRI);
195 // Insert an IT instruction.
196 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII->get(ARM::t2IT))
199 // Add implicit use of ITSTATE to IT block instructions.
200 MI->addOperand(MachineOperand::CreateReg(ARM::ITSTATE, false/*ifDef*/,
201 true/*isImp*/, false/*isKill*/));
203 MachineInstr *LastITMI = MI;
204 MachineBasicBlock::iterator InsertPos = MIB.getInstr();
208 ARMCC::CondCodes OCC = ARMCC::getOppositeCondition(CC);
209 unsigned Mask = 0, Pos = 3;
211 // v8 IT blocks are limited to one conditional op unless -arm-no-restrict-it
212 // is set: skip the loop
214 // Branches, including tricky ones like LDM_RET, need to end an IT
215 // block so check the instruction we just put in the block.
216 for (; MBBI != E && Pos &&
217 (!MI->isBranch() && !MI->isReturn()) ; ++MBBI) {
218 if (MBBI->isDebugValue())
221 MachineInstr *NMI = &*MBBI;
224 unsigned NPredReg = 0;
225 ARMCC::CondCodes NCC = getITInstrPredicate(NMI, NPredReg);
226 if (NCC == CC || NCC == OCC) {
227 Mask |= (NCC & 1) << Pos;
228 // Add implicit use of ITSTATE.
229 NMI->addOperand(MachineOperand::CreateReg(ARM::ITSTATE, false/*ifDef*/,
230 true/*isImp*/, false/*isKill*/));
233 if (NCC == ARMCC::AL &&
234 MoveCopyOutOfITBlock(NMI, CC, OCC, Defs, Uses)) {
237 MBB.insert(InsertPos, NMI);
238 ClearKillFlags(MI, Uses);
244 TrackDefUses(NMI, Defs, Uses, TRI);
251 // Tag along (firstcond[0] << 4) with the mask.
252 Mask |= (CC & 1) << 4;
255 // Last instruction in IT block kills ITSTATE.
256 LastITMI->findRegisterUseOperand(ARM::ITSTATE)->setIsKill();
258 // Finalize the bundle.
259 finalizeBundle(MBB, InsertPos.getInstrIterator(),
260 ++LastITMI->getIterator());
269 bool Thumb2ITBlockPass::runOnMachineFunction(MachineFunction &Fn) {
270 const ARMSubtarget &STI =
271 static_cast<const ARMSubtarget &>(Fn.getSubtarget());
274 AFI = Fn.getInfo<ARMFunctionInfo>();
275 TII = static_cast<const Thumb2InstrInfo *>(STI.getInstrInfo());
276 TRI = STI.getRegisterInfo();
277 restrictIT = STI.restrictIT();
279 if (!AFI->isThumbFunction())
282 bool Modified = false;
283 for (MachineFunction::iterator MFI = Fn.begin(), E = Fn.end(); MFI != E; ) {
284 MachineBasicBlock &MBB = *MFI;
286 Modified |= InsertITInstructions(MBB);
290 AFI->setHasITBlocks(true);
295 /// createThumb2ITBlockPass - Returns an instance of the Thumb2 IT blocks
297 FunctionPass *llvm::createThumb2ITBlockPass() {
298 return new Thumb2ITBlockPass();