1 //===-- Thumb2ITBlockPass.cpp - Insert Thumb IT blocks ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #define DEBUG_TYPE "thumb2-it"
12 #include "ARMMachineFunctionInfo.h"
13 #include "Thumb2InstrInfo.h"
14 #include "llvm/CodeGen/MachineInstr.h"
15 #include "llvm/CodeGen/MachineInstrBuilder.h"
16 #include "llvm/CodeGen/MachineFunctionPass.h"
17 #include "llvm/ADT/SmallSet.h"
18 #include "llvm/ADT/Statistic.h"
21 STATISTIC(NumITs, "Number of IT blocks inserted");
22 STATISTIC(NumMovedInsts, "Number of predicated instructions moved");
25 class Thumb2ITBlockPass : public MachineFunctionPass {
30 Thumb2ITBlockPass(bool PreRA) :
31 MachineFunctionPass(&ID), PreRegAlloc(PreRA) {}
33 const Thumb2InstrInfo *TII;
36 virtual bool runOnMachineFunction(MachineFunction &Fn);
38 virtual const char *getPassName() const {
39 return "Thumb IT blocks insertion pass";
43 bool MoveCPSRUseUp(MachineBasicBlock &MBB,
44 MachineBasicBlock::iterator MBBI,
45 MachineBasicBlock::iterator E,
47 ARMCC::CondCodes CC, ARMCC::CondCodes OCC,
50 void FindITBlockRanges(MachineBasicBlock &MBB,
51 SmallVector<MachineInstr*,4> &FirstUses,
52 SmallVector<MachineInstr*,4> &LastUses);
53 bool InsertITBlock(MachineInstr *First, MachineInstr *Last);
54 bool InsertITBlocks(MachineBasicBlock &MBB);
55 bool InsertITInstructions(MachineBasicBlock &MBB);
57 char Thumb2ITBlockPass::ID = 0;
60 static ARMCC::CondCodes getPredicate(const MachineInstr *MI, unsigned &PredReg){
61 unsigned Opc = MI->getOpcode();
62 if (Opc == ARM::tBcc || Opc == ARM::t2Bcc)
64 return llvm::getInstrPredicate(MI, PredReg);
68 Thumb2ITBlockPass::MoveCPSRUseUp(MachineBasicBlock &MBB,
69 MachineBasicBlock::iterator MBBI,
70 MachineBasicBlock::iterator E,
72 ARMCC::CondCodes CC, ARMCC::CondCodes OCC,
74 SmallSet<unsigned, 4> Defs, Uses;
75 MachineBasicBlock::iterator I = MBBI;
76 // Look for next CPSR use by scanning up to 4 instructions.
77 for (unsigned i = 0; i < 4; ++i) {
78 MachineInstr *MI = &*I;
79 unsigned MPredReg = 0;
80 ARMCC::CondCodes MCC = getPredicate(MI, MPredReg);
81 if (MCC != ARMCC::AL) {
82 if (MPredReg != PredReg || (MCC != CC && MCC != OCC))
85 // Check if the instruction is using any register that's defined
86 // below the previous predicated instruction. Also return false if
87 // it defines any register which is used in between.
88 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
89 const MachineOperand &MO = MI->getOperand(i);
92 unsigned Reg = MO.getReg();
96 if (Reg == PredReg || Uses.count(Reg))
106 MBB.insert(MBBI, MI);
111 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
112 const MachineOperand &MO = MI->getOperand(i);
115 unsigned Reg = MO.getReg();
133 static bool isCPSRLiveout(MachineBasicBlock &MBB) {
134 for (MachineBasicBlock::succ_iterator I = MBB.succ_begin(),
135 E = MBB.succ_end(); I != E; ++I) {
136 if ((*I)->isLiveIn(ARM::CPSR))
142 void Thumb2ITBlockPass::FindITBlockRanges(MachineBasicBlock &MBB,
143 SmallVector<MachineInstr*,4> &FirstUses,
144 SmallVector<MachineInstr*,4> &LastUses) {
145 bool SeenUse = false;
146 MachineOperand *LastDef = 0;
147 MachineOperand *LastUse = 0;
148 MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
150 MachineInstr *MI = &*MBBI;
153 MachineOperand *Def = 0;
154 MachineOperand *Use = 0;
155 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
156 MachineOperand &MO = MI->getOperand(i);
157 if (!MO.isReg() || MO.getReg() != ARM::CPSR)
160 assert(Def == 0 && "Multiple defs of CPSR?");
163 assert(Use == 0 && "Multiple uses of CPSR?");
171 FirstUses.push_back(MI);
177 LastUses.push_back(LastUse->getParent());
186 // Is the last use a kill?
187 if (isCPSRLiveout(MBB))
188 LastUses.push_back(0);
190 LastUses.push_back(LastUse->getParent());
194 bool Thumb2ITBlockPass::InsertITBlock(MachineInstr *First, MachineInstr *Last) {
198 bool Modified = false;
199 MachineBasicBlock *MBB = First->getParent();
200 MachineBasicBlock::iterator MBBI = First;
201 MachineBasicBlock::iterator E = Last;
203 if (First->getDesc().isBranch() || First->getDesc().isReturn())
206 unsigned PredReg = 0;
207 ARMCC::CondCodes CC = getPredicate(First, PredReg);
211 // Move uses of the CPSR together if possible.
212 ARMCC::CondCodes OCC = ARMCC::getOppositeCondition(CC);
216 if (MBBI->getDesc().isBranch() || MBBI->getDesc().isReturn())
218 MachineInstr *NMI = &*MBBI;
219 unsigned NPredReg = 0;
220 ARMCC::CondCodes NCC = getPredicate(NMI, NPredReg);
221 if (NCC != CC && NCC != OCC) {
222 if (NCC != ARMCC::AL)
226 if (!MoveCPSRUseUp(*MBB, MBBI, E, PredReg, CC, OCC, Done))
236 bool Thumb2ITBlockPass::InsertITBlocks(MachineBasicBlock &MBB) {
237 SmallVector<MachineInstr*, 4> FirstUses;
238 SmallVector<MachineInstr*, 4> LastUses;
239 FindITBlockRanges(MBB, FirstUses, LastUses);
240 assert(FirstUses.size() == LastUses.size() && "Incorrect range information!");
242 bool Modified = false;
243 for (unsigned i = 0, e = FirstUses.size(); i != e; ++i) {
244 if (LastUses[i] == 0)
245 // Must be the last pair where CPSR is live out of the block.
247 Modified |= InsertITBlock(FirstUses[i], LastUses[i]);
252 static void TrackDefUses(MachineInstr *MI, SmallSet<unsigned, 4> &Defs,
253 SmallSet<unsigned, 4> &Uses) {
254 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
255 MachineOperand &MO = MI->getOperand(i);
258 unsigned Reg = MO.getReg();
268 bool Thumb2ITBlockPass::InsertITInstructions(MachineBasicBlock &MBB) {
269 bool Modified = false;
271 SmallSet<unsigned, 4> Defs;
272 SmallSet<unsigned, 4> Uses;
273 MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
275 MachineInstr *MI = &*MBBI;
276 DebugLoc dl = MI->getDebugLoc();
277 unsigned PredReg = 0;
278 ARMCC::CondCodes CC = getPredicate(MI, PredReg);
279 if (CC == ARMCC::AL) {
286 TrackDefUses(MI, Defs, Uses);
288 // Insert an IT instruction.
289 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII->get(ARM::t2IT))
291 MachineBasicBlock::iterator InsertPos = MIB;
295 ARMCC::CondCodes OCC = ARMCC::getOppositeCondition(CC);
296 unsigned Mask = 0, Pos = 3;
297 // Branches, including tricky ones like LDM_RET, need to end an IT
298 // block so check the instruction we just put in the block.
299 for (; MBBI != E && Pos &&
300 (!MI->getDesc().isBranch() && !MI->getDesc().isReturn()) ; ++MBBI) {
301 if (MBBI->isDebugValue())
304 MachineInstr *NMI = &*MBBI;
307 unsigned NPredReg = 0;
308 ARMCC::CondCodes NCC = getPredicate(NMI, NPredReg);
309 if (NCC == CC || NCC == OCC)
310 Mask |= (NCC & 1) << Pos;
312 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
313 if (NCC == ARMCC::AL &&
314 TII->isMoveInstr(*NMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx)) {
315 assert(SrcSubIdx == 0 && DstSubIdx == 0 &&
316 "Sub-register indices still around?");
317 // llvm models select's as two-address instructions. That means a copy
318 // is inserted before a t2MOVccr, etc. If the copy is scheduled in
319 // between selects we would end up creating multiple IT blocks.
320 if (!Uses.count(DstReg) && !Defs.count(SrcReg)) {
323 MBB.insert(InsertPos, NMI);
330 TrackDefUses(NMI, Defs, Uses);
335 // Tag along (firstcond[0] << 4) with the mask.
336 Mask |= (CC & 1) << 4;
345 bool Thumb2ITBlockPass::runOnMachineFunction(MachineFunction &Fn) {
346 const TargetMachine &TM = Fn.getTarget();
347 AFI = Fn.getInfo<ARMFunctionInfo>();
348 TII = static_cast<const Thumb2InstrInfo*>(TM.getInstrInfo());
350 if (!AFI->isThumbFunction())
353 bool Modified = false;
354 for (MachineFunction::iterator MFI = Fn.begin(), E = Fn.end(); MFI != E; ) {
355 MachineBasicBlock &MBB = *MFI;
358 Modified |= InsertITBlocks(MBB);
360 Modified |= InsertITInstructions(MBB);
366 /// createThumb2ITBlockPass - Returns an instance of the Thumb2 IT blocks
368 FunctionPass *llvm::createThumb2ITBlockPass(bool PreAlloc) {
369 return new Thumb2ITBlockPass(PreAlloc);