1 //===-- Thumb2ITBlockPass.cpp - Insert Thumb IT blocks ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #define DEBUG_TYPE "thumb2-it"
12 #include "ARMMachineFunctionInfo.h"
13 #include "Thumb2InstrInfo.h"
14 #include "llvm/CodeGen/MachineInstr.h"
15 #include "llvm/CodeGen/MachineInstrBuilder.h"
16 #include "llvm/CodeGen/MachineFunctionPass.h"
17 #include "llvm/ADT/SmallSet.h"
18 #include "llvm/ADT/Statistic.h"
21 STATISTIC(NumITs, "Number of IT blocks inserted");
22 STATISTIC(NumMovedInsts, "Number of predicated instructions moved");
25 class Thumb2ITBlockPass : public MachineFunctionPass {
30 Thumb2ITBlockPass() : MachineFunctionPass(&ID) {}
32 const Thumb2InstrInfo *TII;
33 const TargetRegisterInfo *TRI;
36 virtual bool runOnMachineFunction(MachineFunction &Fn);
38 virtual const char *getPassName() const {
39 return "Thumb IT blocks insertion pass";
43 bool MoveCopyOutOfITBlock(MachineInstr *MI,
44 ARMCC::CondCodes CC, ARMCC::CondCodes OCC,
45 SmallSet<unsigned, 4> &Defs,
46 SmallSet<unsigned, 4> &Uses);
47 bool InsertITInstructions(MachineBasicBlock &MBB);
49 char Thumb2ITBlockPass::ID = 0;
52 /// TrackDefUses - Tracking what registers are being defined and used by
53 /// instructions in the IT block. This also tracks "dependencies", i.e. uses
54 /// in the IT block that are defined before the IT instruction.
55 static void TrackDefUses(MachineInstr *MI,
56 SmallSet<unsigned, 4> &Defs,
57 SmallSet<unsigned, 4> &Uses,
58 const TargetRegisterInfo *TRI) {
59 SmallVector<unsigned, 4> LocalDefs;
60 SmallVector<unsigned, 4> LocalUses;
62 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
63 MachineOperand &MO = MI->getOperand(i);
66 unsigned Reg = MO.getReg();
67 if (!Reg || Reg == ARM::ITSTATE || Reg == ARM::SP)
70 LocalUses.push_back(Reg);
72 LocalDefs.push_back(Reg);
75 for (unsigned i = 0, e = LocalUses.size(); i != e; ++i) {
76 unsigned Reg = LocalUses[i];
78 for (const unsigned *Subreg = TRI->getSubRegisters(Reg);
83 for (unsigned i = 0, e = LocalDefs.size(); i != e; ++i) {
84 unsigned Reg = LocalDefs[i];
86 for (const unsigned *Subreg = TRI->getSubRegisters(Reg);
95 Thumb2ITBlockPass::MoveCopyOutOfITBlock(MachineInstr *MI,
96 ARMCC::CondCodes CC, ARMCC::CondCodes OCC,
97 SmallSet<unsigned, 4> &Defs,
98 SmallSet<unsigned, 4> &Uses) {
99 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
100 if (TII->isMoveInstr(*MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx)) {
101 assert(SrcSubIdx == 0 && DstSubIdx == 0 &&
102 "Sub-register indices still around?");
103 // llvm models select's as two-address instructions. That means a copy
104 // is inserted before a t2MOVccr, etc. If the copy is scheduled in
105 // between selects we would end up creating multiple IT blocks.
107 // First check if it's safe to move it.
108 if (Uses.count(DstReg) || Defs.count(SrcReg))
111 // Then peek at the next instruction to see if it's predicated on CC or OCC.
112 // If not, then there is nothing to be gained by moving the copy.
113 MachineBasicBlock::iterator I = MI; ++I;
114 MachineBasicBlock::iterator E = MI->getParent()->end();
115 while (I != E && I->isDebugValue())
118 unsigned NPredReg = 0;
119 ARMCC::CondCodes NCC = llvm::getITInstrPredicate(I, NPredReg);
120 if (NCC == CC || NCC == OCC)
127 bool Thumb2ITBlockPass::InsertITInstructions(MachineBasicBlock &MBB) {
128 bool Modified = false;
130 SmallSet<unsigned, 4> Defs;
131 SmallSet<unsigned, 4> Uses;
132 MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
134 MachineInstr *MI = &*MBBI;
135 DebugLoc dl = MI->getDebugLoc();
136 unsigned PredReg = 0;
137 ARMCC::CondCodes CC = llvm::getITInstrPredicate(MI, PredReg);
138 if (CC == ARMCC::AL) {
145 TrackDefUses(MI, Defs, Uses, TRI);
147 // Insert an IT instruction.
148 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII->get(ARM::t2IT))
151 // Add implicit use of ITSTATE to IT block instructions.
152 MI->addOperand(MachineOperand::CreateReg(ARM::ITSTATE, false/*ifDef*/,
153 true/*isImp*/, false/*isKill*/));
155 MachineInstr *LastITMI = MI;
156 MachineBasicBlock::iterator InsertPos = MIB;
160 ARMCC::CondCodes OCC = ARMCC::getOppositeCondition(CC);
161 unsigned Mask = 0, Pos = 3;
162 // Branches, including tricky ones like LDM_RET, need to end an IT
163 // block so check the instruction we just put in the block.
164 for (; MBBI != E && Pos &&
165 (!MI->getDesc().isBranch() && !MI->getDesc().isReturn()) ; ++MBBI) {
166 if (MBBI->isDebugValue())
169 MachineInstr *NMI = &*MBBI;
172 unsigned NPredReg = 0;
173 ARMCC::CondCodes NCC = llvm::getITInstrPredicate(NMI, NPredReg);
174 if (NCC == CC || NCC == OCC) {
175 Mask |= (NCC & 1) << Pos;
176 // Add implicit use of ITSTATE.
177 NMI->addOperand(MachineOperand::CreateReg(ARM::ITSTATE, false/*ifDef*/,
178 true/*isImp*/, false/*isKill*/));
181 if (NCC == ARMCC::AL &&
182 MoveCopyOutOfITBlock(NMI, CC, OCC, Defs, Uses)) {
185 MBB.insert(InsertPos, NMI);
191 TrackDefUses(NMI, Defs, Uses, TRI);
197 // Tag along (firstcond[0] << 4) with the mask.
198 Mask |= (CC & 1) << 4;
201 // Last instruction in IT block kills ITSTATE.
202 LastITMI->findRegisterUseOperand(ARM::ITSTATE)->setIsKill();
211 bool Thumb2ITBlockPass::runOnMachineFunction(MachineFunction &Fn) {
212 const TargetMachine &TM = Fn.getTarget();
213 AFI = Fn.getInfo<ARMFunctionInfo>();
214 TII = static_cast<const Thumb2InstrInfo*>(TM.getInstrInfo());
215 TRI = TM.getRegisterInfo();
217 if (!AFI->isThumbFunction())
220 bool Modified = false;
221 for (MachineFunction::iterator MFI = Fn.begin(), E = Fn.end(); MFI != E; ) {
222 MachineBasicBlock &MBB = *MFI;
224 Modified |= InsertITInstructions(MBB);
228 AFI->setHasITBlocks(true);
233 /// createThumb2ITBlockPass - Returns an instance of the Thumb2 IT blocks
235 FunctionPass *llvm::createThumb2ITBlockPass() {
236 return new Thumb2ITBlockPass();