1 //===- Thumb2InstrInfo.cpp - Thumb-2 Instruction Information ----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Thumb-2 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "Thumb2InstrInfo.h"
16 #include "ARMConstantPoolValue.h"
17 #include "ARMAddressingModes.h"
18 #include "ARMGenInstrInfo.inc"
19 #include "ARMMachineFunctionInfo.h"
20 #include "Thumb2HazardRecognizer.h"
21 #include "Thumb2InstrInfo.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineMemOperand.h"
25 #include "llvm/CodeGen/PseudoSourceValue.h"
26 #include "llvm/ADT/SmallVector.h"
27 #include "llvm/Support/CommandLine.h"
32 OldT2IfCvt("old-thumb2-ifcvt", cl::Hidden,
33 cl::desc("Use old-style Thumb2 if-conversion heuristics"),
36 Thumb2InstrInfo::Thumb2InstrInfo(const ARMSubtarget &STI)
37 : ARMBaseInstrInfo(STI), RI(*this, STI) {
40 unsigned Thumb2InstrInfo::getUnindexedOpcode(unsigned Opc) const {
45 bool Thumb2InstrInfo::isProfitableToIfCvt(MachineBasicBlock &MBB,
48 float Confidence) const {
50 return ARMBaseInstrInfo::isProfitableToIfCvt(MBB, NumInstrs,
51 Prediction, Confidence);
52 return NumInstrs && NumInstrs <= 3;
55 bool Thumb2InstrInfo::
56 isProfitableToIfCvt(MachineBasicBlock &TMBB, unsigned NumT,
57 MachineBasicBlock &FMBB, unsigned NumF,
58 float Prediction, float Confidence) const {
60 return ARMBaseInstrInfo::isProfitableToIfCvt(TMBB, NumT,
62 Prediction, Confidence);
64 // FIXME: Catch optimization such as:
67 return NumT && NumF &&
68 NumT <= 3 && NumF <= 3;
73 Thumb2InstrInfo::ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail,
74 MachineBasicBlock *NewDest) const {
75 MachineBasicBlock *MBB = Tail->getParent();
76 ARMFunctionInfo *AFI = MBB->getParent()->getInfo<ARMFunctionInfo>();
77 if (!AFI->hasITBlocks()) {
78 TargetInstrInfoImpl::ReplaceTailWithBranchTo(Tail, NewDest);
82 // If the first instruction of Tail is predicated, we may have to update
83 // the IT instruction.
85 ARMCC::CondCodes CC = llvm::getInstrPredicate(Tail, PredReg);
86 MachineBasicBlock::iterator MBBI = Tail;
88 // Expecting at least the t2IT instruction before it.
91 // Actually replace the tail.
92 TargetInstrInfoImpl::ReplaceTailWithBranchTo(Tail, NewDest);
95 if (CC != ARMCC::AL) {
96 MachineBasicBlock::iterator E = MBB->begin();
97 unsigned Count = 4; // At most 4 instructions in an IT block.
98 while (Count && MBBI != E) {
99 if (MBBI->isDebugValue()) {
103 if (MBBI->getOpcode() == ARM::t2IT) {
104 unsigned Mask = MBBI->getOperand(1).getImm();
106 MBBI->eraseFromParent();
108 unsigned MaskOn = 1 << Count;
109 unsigned MaskOff = ~(MaskOn - 1);
110 MBBI->getOperand(1).setImm((Mask & MaskOff) | MaskOn);
118 // Ctrl flow can reach here if branch folding is run before IT block
124 Thumb2InstrInfo::isLegalToSplitMBBAt(MachineBasicBlock &MBB,
125 MachineBasicBlock::iterator MBBI) const {
126 unsigned PredReg = 0;
127 return llvm::getITInstrPredicate(MBBI, PredReg) == ARMCC::AL;
130 void Thumb2InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
131 MachineBasicBlock::iterator I, DebugLoc DL,
132 unsigned DestReg, unsigned SrcReg,
133 bool KillSrc) const {
134 // Handle SPR, DPR, and QPR copies.
135 if (!ARM::GPRRegClass.contains(DestReg, SrcReg))
136 return ARMBaseInstrInfo::copyPhysReg(MBB, I, DL, DestReg, SrcReg, KillSrc);
138 bool tDest = ARM::tGPRRegClass.contains(DestReg);
139 bool tSrc = ARM::tGPRRegClass.contains(SrcReg);
140 unsigned Opc = ARM::tMOVgpr2gpr;
144 Opc = ARM::tMOVtgpr2gpr;
146 Opc = ARM::tMOVgpr2tgpr;
148 BuildMI(MBB, I, DL, get(Opc), DestReg)
149 .addReg(SrcReg, getKillRegState(KillSrc));
152 void Thumb2InstrInfo::
153 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
154 unsigned SrcReg, bool isKill, int FI,
155 const TargetRegisterClass *RC,
156 const TargetRegisterInfo *TRI) const {
157 if (RC == ARM::GPRRegisterClass || RC == ARM::tGPRRegisterClass ||
158 RC == ARM::tcGPRRegisterClass || RC == ARM::rGPRRegisterClass) {
160 if (I != MBB.end()) DL = I->getDebugLoc();
162 MachineFunction &MF = *MBB.getParent();
163 MachineFrameInfo &MFI = *MF.getFrameInfo();
164 MachineMemOperand *MMO =
165 MF.getMachineMemOperand(
166 MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)),
167 MachineMemOperand::MOStore,
168 MFI.getObjectSize(FI),
169 MFI.getObjectAlignment(FI));
170 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::t2STRi12))
171 .addReg(SrcReg, getKillRegState(isKill))
172 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
176 ARMBaseInstrInfo::storeRegToStackSlot(MBB, I, SrcReg, isKill, FI, RC, TRI);
179 void Thumb2InstrInfo::
180 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
181 unsigned DestReg, int FI,
182 const TargetRegisterClass *RC,
183 const TargetRegisterInfo *TRI) const {
184 if (RC == ARM::GPRRegisterClass || RC == ARM::tGPRRegisterClass ||
185 RC == ARM::tcGPRRegisterClass || RC == ARM::rGPRRegisterClass) {
187 if (I != MBB.end()) DL = I->getDebugLoc();
189 MachineFunction &MF = *MBB.getParent();
190 MachineFrameInfo &MFI = *MF.getFrameInfo();
191 MachineMemOperand *MMO =
192 MF.getMachineMemOperand(
193 MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)),
194 MachineMemOperand::MOLoad,
195 MFI.getObjectSize(FI),
196 MFI.getObjectAlignment(FI));
197 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::t2LDRi12), DestReg)
198 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
202 ARMBaseInstrInfo::loadRegFromStackSlot(MBB, I, DestReg, FI, RC, TRI);
205 ScheduleHazardRecognizer *Thumb2InstrInfo::
206 CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II) const {
207 return (ScheduleHazardRecognizer *)new Thumb2HazardRecognizer(II);
210 void llvm::emitT2RegPlusImmediate(MachineBasicBlock &MBB,
211 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
212 unsigned DestReg, unsigned BaseReg, int NumBytes,
213 ARMCC::CondCodes Pred, unsigned PredReg,
214 const ARMBaseInstrInfo &TII) {
215 bool isSub = NumBytes < 0;
216 if (isSub) NumBytes = -NumBytes;
218 // If profitable, use a movw or movt to materialize the offset.
219 // FIXME: Use the scavenger to grab a scratch register.
220 if (DestReg != ARM::SP && DestReg != BaseReg &&
222 ARM_AM::getT2SOImmVal(NumBytes) == -1) {
224 if (NumBytes < 65536) {
225 // Use a movw to materialize the 16-bit constant.
226 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi16), DestReg)
228 .addImm((unsigned)Pred).addReg(PredReg);
230 } else if ((NumBytes & 0xffff) == 0) {
231 // Use a movt to materialize the 32-bit constant.
232 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVTi16), DestReg)
234 .addImm(NumBytes >> 16)
235 .addImm((unsigned)Pred).addReg(PredReg);
241 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2SUBrr), DestReg)
242 .addReg(BaseReg, RegState::Kill)
243 .addReg(DestReg, RegState::Kill)
244 .addImm((unsigned)Pred).addReg(PredReg).addReg(0);
246 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2ADDrr), DestReg)
247 .addReg(DestReg, RegState::Kill)
248 .addReg(BaseReg, RegState::Kill)
249 .addImm((unsigned)Pred).addReg(PredReg).addReg(0);
256 unsigned ThisVal = NumBytes;
258 if (DestReg == ARM::SP && BaseReg != ARM::SP) {
259 // mov sp, rn. Note t2MOVr cannot be used.
260 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr),DestReg).addReg(BaseReg);
265 bool HasCCOut = true;
266 if (BaseReg == ARM::SP) {
268 if (DestReg == ARM::SP && (ThisVal < ((1 << 7)-1) * 4)) {
269 assert((ThisVal & 3) == 0 && "Stack update is not multiple of 4?");
270 Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
271 // FIXME: Fix Thumb1 immediate encoding.
272 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
273 .addReg(BaseReg).addImm(ThisVal/4);
278 // sub rd, sp, so_imm
279 Opc = isSub ? ARM::t2SUBrSPi : ARM::t2ADDrSPi;
280 if (ARM_AM::getT2SOImmVal(NumBytes) != -1) {
283 // FIXME: Move this to ARMAddressingModes.h?
284 unsigned RotAmt = CountLeadingZeros_32(ThisVal);
285 ThisVal = ThisVal & ARM_AM::rotr32(0xff000000U, RotAmt);
286 NumBytes &= ~ThisVal;
287 assert(ARM_AM::getT2SOImmVal(ThisVal) != -1 &&
288 "Bit extraction didn't work?");
291 assert(DestReg != ARM::SP && BaseReg != ARM::SP);
292 Opc = isSub ? ARM::t2SUBri : ARM::t2ADDri;
293 if (ARM_AM::getT2SOImmVal(NumBytes) != -1) {
295 } else if (ThisVal < 4096) {
296 Opc = isSub ? ARM::t2SUBri12 : ARM::t2ADDri12;
300 // FIXME: Move this to ARMAddressingModes.h?
301 unsigned RotAmt = CountLeadingZeros_32(ThisVal);
302 ThisVal = ThisVal & ARM_AM::rotr32(0xff000000U, RotAmt);
303 NumBytes &= ~ThisVal;
304 assert(ARM_AM::getT2SOImmVal(ThisVal) != -1 &&
305 "Bit extraction didn't work?");
309 // Build the new ADD / SUB.
310 MachineInstrBuilder MIB =
311 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
312 .addReg(BaseReg, RegState::Kill)
322 negativeOffsetOpcode(unsigned opcode)
325 case ARM::t2LDRi12: return ARM::t2LDRi8;
326 case ARM::t2LDRHi12: return ARM::t2LDRHi8;
327 case ARM::t2LDRBi12: return ARM::t2LDRBi8;
328 case ARM::t2LDRSHi12: return ARM::t2LDRSHi8;
329 case ARM::t2LDRSBi12: return ARM::t2LDRSBi8;
330 case ARM::t2STRi12: return ARM::t2STRi8;
331 case ARM::t2STRBi12: return ARM::t2STRBi8;
332 case ARM::t2STRHi12: return ARM::t2STRHi8;
352 positiveOffsetOpcode(unsigned opcode)
355 case ARM::t2LDRi8: return ARM::t2LDRi12;
356 case ARM::t2LDRHi8: return ARM::t2LDRHi12;
357 case ARM::t2LDRBi8: return ARM::t2LDRBi12;
358 case ARM::t2LDRSHi8: return ARM::t2LDRSHi12;
359 case ARM::t2LDRSBi8: return ARM::t2LDRSBi12;
360 case ARM::t2STRi8: return ARM::t2STRi12;
361 case ARM::t2STRBi8: return ARM::t2STRBi12;
362 case ARM::t2STRHi8: return ARM::t2STRHi12;
367 case ARM::t2LDRSHi12:
368 case ARM::t2LDRSBi12:
382 immediateOffsetOpcode(unsigned opcode)
385 case ARM::t2LDRs: return ARM::t2LDRi12;
386 case ARM::t2LDRHs: return ARM::t2LDRHi12;
387 case ARM::t2LDRBs: return ARM::t2LDRBi12;
388 case ARM::t2LDRSHs: return ARM::t2LDRSHi12;
389 case ARM::t2LDRSBs: return ARM::t2LDRSBi12;
390 case ARM::t2STRs: return ARM::t2STRi12;
391 case ARM::t2STRBs: return ARM::t2STRBi12;
392 case ARM::t2STRHs: return ARM::t2STRHi12;
397 case ARM::t2LDRSHi12:
398 case ARM::t2LDRSBi12:
419 bool llvm::rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
420 unsigned FrameReg, int &Offset,
421 const ARMBaseInstrInfo &TII) {
422 unsigned Opcode = MI.getOpcode();
423 const TargetInstrDesc &Desc = MI.getDesc();
424 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
427 // Memory operands in inline assembly always use AddrModeT2_i12.
428 if (Opcode == ARM::INLINEASM)
429 AddrMode = ARMII::AddrModeT2_i12; // FIXME. mode for thumb2?
431 if (Opcode == ARM::t2ADDri || Opcode == ARM::t2ADDri12) {
432 Offset += MI.getOperand(FrameRegIdx+1).getImm();
435 if (Offset == 0 && getInstrPredicate(&MI, PredReg) == ARMCC::AL) {
436 // Turn it into a move.
437 MI.setDesc(TII.get(ARM::tMOVgpr2gpr));
438 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
439 // Remove offset and remaining explicit predicate operands.
440 do MI.RemoveOperand(FrameRegIdx+1);
441 while (MI.getNumOperands() > FrameRegIdx+1 &&
442 (!MI.getOperand(FrameRegIdx+1).isReg() ||
443 !MI.getOperand(FrameRegIdx+1).isImm()));
447 bool isSP = FrameReg == ARM::SP;
448 bool HasCCOut = Opcode != ARM::t2ADDri12;
453 MI.setDesc(TII.get(isSP ? ARM::t2SUBrSPi : ARM::t2SUBri));
455 MI.setDesc(TII.get(isSP ? ARM::t2ADDrSPi : ARM::t2ADDri));
458 // Common case: small offset, fits into instruction.
459 if (ARM_AM::getT2SOImmVal(Offset) != -1) {
460 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
461 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
462 // Add cc_out operand if the original instruction did not have one.
464 MI.addOperand(MachineOperand::CreateReg(0, false));
468 // Another common case: imm12.
470 (!HasCCOut || MI.getOperand(MI.getNumOperands()-1).getReg() == 0)) {
471 unsigned NewOpc = isSP
472 ? (isSub ? ARM::t2SUBrSPi12 : ARM::t2ADDrSPi12)
473 : (isSub ? ARM::t2SUBri12 : ARM::t2ADDri12);
474 MI.setDesc(TII.get(NewOpc));
475 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
476 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
477 // Remove the cc_out operand.
479 MI.RemoveOperand(MI.getNumOperands()-1);
484 // Otherwise, extract 8 adjacent bits from the immediate into this
486 unsigned RotAmt = CountLeadingZeros_32(Offset);
487 unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xff000000U, RotAmt);
489 // We will handle these bits from offset, clear them.
490 Offset &= ~ThisImmVal;
492 assert(ARM_AM::getT2SOImmVal(ThisImmVal) != -1 &&
493 "Bit extraction didn't work?");
494 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal);
495 // Add cc_out operand if the original instruction did not have one.
497 MI.addOperand(MachineOperand::CreateReg(0, false));
501 // AddrMode4 and AddrMode6 cannot handle any offset.
502 if (AddrMode == ARMII::AddrMode4 || AddrMode == ARMII::AddrMode6)
505 // AddrModeT2_so cannot handle any offset. If there is no offset
506 // register then we change to an immediate version.
507 unsigned NewOpc = Opcode;
508 if (AddrMode == ARMII::AddrModeT2_so) {
509 unsigned OffsetReg = MI.getOperand(FrameRegIdx+1).getReg();
510 if (OffsetReg != 0) {
511 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
515 MI.RemoveOperand(FrameRegIdx+1);
516 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(0);
517 NewOpc = immediateOffsetOpcode(Opcode);
518 AddrMode = ARMII::AddrModeT2_i12;
521 unsigned NumBits = 0;
523 if (AddrMode == ARMII::AddrModeT2_i8 || AddrMode == ARMII::AddrModeT2_i12) {
524 // i8 supports only negative, and i12 supports only positive, so
525 // based on Offset sign convert Opcode to the appropriate
527 Offset += MI.getOperand(FrameRegIdx+1).getImm();
529 NewOpc = negativeOffsetOpcode(Opcode);
534 NewOpc = positiveOffsetOpcode(Opcode);
537 } else if (AddrMode == ARMII::AddrMode5) {
539 const MachineOperand &OffOp = MI.getOperand(FrameRegIdx+1);
540 int InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm());
541 if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM::sub)
545 Offset += InstrOffs * 4;
546 assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
552 llvm_unreachable("Unsupported addressing mode!");
555 if (NewOpc != Opcode)
556 MI.setDesc(TII.get(NewOpc));
558 MachineOperand &ImmOp = MI.getOperand(FrameRegIdx+1);
560 // Attempt to fold address computation
561 // Common case: small offset, fits into instruction.
562 int ImmedOffset = Offset / Scale;
563 unsigned Mask = (1 << NumBits) - 1;
564 if ((unsigned)Offset <= Mask * Scale) {
565 // Replace the FrameIndex with fp/sp
566 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
568 if (AddrMode == ARMII::AddrMode5)
569 // FIXME: Not consistent.
570 ImmedOffset |= 1 << NumBits;
572 ImmedOffset = -ImmedOffset;
574 ImmOp.ChangeToImmediate(ImmedOffset);
579 // Otherwise, offset doesn't fit. Pull in what we can to simplify
580 ImmedOffset = ImmedOffset & Mask;
582 if (AddrMode == ARMII::AddrMode5)
583 // FIXME: Not consistent.
584 ImmedOffset |= 1 << NumBits;
586 ImmedOffset = -ImmedOffset;
587 if (ImmedOffset == 0)
588 // Change the opcode back if the encoded offset is zero.
589 MI.setDesc(TII.get(positiveOffsetOpcode(NewOpc)));
592 ImmOp.ChangeToImmediate(ImmedOffset);
593 Offset &= ~(Mask*Scale);
596 Offset = (isSub) ? -Offset : Offset;
600 /// scheduleTwoAddrSource - Schedule the copy / re-mat of the source of the
601 /// two-addrss instruction inserted by two-address pass.
603 Thumb2InstrInfo::scheduleTwoAddrSource(MachineInstr *SrcMI,
605 const TargetRegisterInfo &TRI) const {
606 if (SrcMI->getOpcode() != ARM::tMOVgpr2gpr ||
607 SrcMI->getOperand(1).isKill())
610 unsigned PredReg = 0;
611 ARMCC::CondCodes CC = llvm::getInstrPredicate(UseMI, PredReg);
612 if (CC == ARMCC::AL || PredReg != ARM::CPSR)
615 // Schedule the copy so it doesn't come between previous instructions
616 // and UseMI which can form an IT block.
617 unsigned SrcReg = SrcMI->getOperand(1).getReg();
618 ARMCC::CondCodes OCC = ARMCC::getOppositeCondition(CC);
619 MachineBasicBlock *MBB = UseMI->getParent();
620 MachineBasicBlock::iterator MBBI = SrcMI;
621 unsigned NumInsts = 0;
622 while (--MBBI != MBB->begin()) {
623 if (MBBI->isDebugValue())
626 MachineInstr *NMI = &*MBBI;
627 ARMCC::CondCodes NCC = llvm::getInstrPredicate(NMI, PredReg);
628 if (!(NCC == CC || NCC == OCC) ||
629 NMI->modifiesRegister(SrcReg, &TRI) ||
630 NMI->definesRegister(ARM::CPSR))
633 // Too many in a row!
639 MBB->insert(++MBBI, SrcMI);
644 llvm::getITInstrPredicate(const MachineInstr *MI, unsigned &PredReg) {
645 unsigned Opc = MI->getOpcode();
646 if (Opc == ARM::tBcc || Opc == ARM::t2Bcc)
648 return llvm::getInstrPredicate(MI, PredReg);