1 //===- Thumb2InstrInfo.cpp - Thumb-2 Instruction Information ----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Thumb-2 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "Thumb2InstrInfo.h"
16 #include "ARMConstantPoolValue.h"
17 #include "ARMAddressingModes.h"
18 #include "ARMGenInstrInfo.inc"
19 #include "ARMMachineFunctionInfo.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineMemOperand.h"
23 #include "llvm/CodeGen/PseudoSourceValue.h"
24 #include "llvm/ADT/SmallVector.h"
25 #include "Thumb2InstrInfo.h"
29 Thumb2InstrInfo::Thumb2InstrInfo(const ARMSubtarget &STI)
30 : ARMBaseInstrInfo(STI), RI(*this, STI) {
33 unsigned Thumb2InstrInfo::getUnindexedOpcode(unsigned Opc) const {
39 Thumb2InstrInfo::BlockHasNoFallThrough(const MachineBasicBlock &MBB) const {
40 if (MBB.empty()) return false;
42 switch (MBB.back().getOpcode()) {
44 case ARM::t2B: // Uncond branch.
45 case ARM::t2BR_JT: // Jumptable branch.
46 case ARM::t2TBB: // Table branch byte.
47 case ARM::t2TBH: // Table branch halfword.
48 case ARM::tBR_JTr: // Jumptable branch (16-bit version).
50 case ARM::tBX_RET_vararg:
63 Thumb2InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
64 MachineBasicBlock::iterator I,
65 unsigned DestReg, unsigned SrcReg,
66 const TargetRegisterClass *DestRC,
67 const TargetRegisterClass *SrcRC) const {
68 DebugLoc DL = DebugLoc::getUnknownLoc();
69 if (I != MBB.end()) DL = I->getDebugLoc();
71 if (DestRC == ARM::GPRRegisterClass &&
72 SrcRC == ARM::GPRRegisterClass) {
73 BuildMI(MBB, I, DL, get(ARM::tMOVgpr2gpr), DestReg).addReg(SrcReg);
75 } else if (DestRC == ARM::GPRRegisterClass &&
76 SrcRC == ARM::tGPRRegisterClass) {
77 BuildMI(MBB, I, DL, get(ARM::tMOVtgpr2gpr), DestReg).addReg(SrcReg);
79 } else if (DestRC == ARM::tGPRRegisterClass &&
80 SrcRC == ARM::GPRRegisterClass) {
81 BuildMI(MBB, I, DL, get(ARM::tMOVgpr2tgpr), DestReg).addReg(SrcReg);
85 // Handle SPR, DPR, and QPR copies.
86 return ARMBaseInstrInfo::copyRegToReg(MBB, I, DestReg, SrcReg, DestRC, SrcRC);
89 void Thumb2InstrInfo::
90 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
91 unsigned SrcReg, bool isKill, int FI,
92 const TargetRegisterClass *RC) const {
93 DebugLoc DL = DebugLoc::getUnknownLoc();
94 if (I != MBB.end()) DL = I->getDebugLoc();
96 if (RC == ARM::GPRRegisterClass) {
97 MachineFunction &MF = *MBB.getParent();
98 MachineFrameInfo &MFI = *MF.getFrameInfo();
99 MachineMemOperand *MMO =
100 MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI),
101 MachineMemOperand::MOStore, 0,
102 MFI.getObjectSize(FI),
103 MFI.getObjectAlignment(FI));
104 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::t2STRi12))
105 .addReg(SrcReg, getKillRegState(isKill))
106 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
110 ARMBaseInstrInfo::storeRegToStackSlot(MBB, I, SrcReg, isKill, FI, RC);
113 void Thumb2InstrInfo::
114 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
115 unsigned DestReg, int FI,
116 const TargetRegisterClass *RC) const {
117 DebugLoc DL = DebugLoc::getUnknownLoc();
118 if (I != MBB.end()) DL = I->getDebugLoc();
120 if (RC == ARM::GPRRegisterClass) {
121 MachineFunction &MF = *MBB.getParent();
122 MachineFrameInfo &MFI = *MF.getFrameInfo();
123 MachineMemOperand *MMO =
124 MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI),
125 MachineMemOperand::MOLoad, 0,
126 MFI.getObjectSize(FI),
127 MFI.getObjectAlignment(FI));
128 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::t2LDRi12), DestReg)
129 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
133 ARMBaseInstrInfo::loadRegFromStackSlot(MBB, I, DestReg, FI, RC);
136 void llvm::emitT2RegPlusImmediate(MachineBasicBlock &MBB,
137 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
138 unsigned DestReg, unsigned BaseReg, int NumBytes,
139 ARMCC::CondCodes Pred, unsigned PredReg,
140 const ARMBaseInstrInfo &TII) {
141 bool isSub = NumBytes < 0;
142 if (isSub) NumBytes = -NumBytes;
144 // If profitable, use a movw or movt to materialize the offset.
145 // FIXME: Use the scavenger to grab a scratch register.
146 if (DestReg != ARM::SP && DestReg != BaseReg &&
148 ARM_AM::getT2SOImmVal(NumBytes) == -1) {
150 if (NumBytes < 65536) {
151 // Use a movw to materialize the 16-bit constant.
152 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi16), DestReg)
154 .addImm((unsigned)Pred).addReg(PredReg).addReg(0);
156 } else if ((NumBytes & 0xffff) == 0) {
157 // Use a movt to materialize the 32-bit constant.
158 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVTi16), DestReg)
160 .addImm(NumBytes >> 16)
161 .addImm((unsigned)Pred).addReg(PredReg).addReg(0);
167 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2SUBrr), DestReg)
168 .addReg(BaseReg, RegState::Kill)
169 .addReg(DestReg, RegState::Kill)
170 .addImm((unsigned)Pred).addReg(PredReg).addReg(0);
172 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2ADDrr), DestReg)
173 .addReg(DestReg, RegState::Kill)
174 .addReg(BaseReg, RegState::Kill)
175 .addImm((unsigned)Pred).addReg(PredReg).addReg(0);
182 unsigned ThisVal = NumBytes;
184 if (DestReg == ARM::SP && BaseReg != ARM::SP) {
185 // mov sp, rn. Note t2MOVr cannot be used.
186 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr),DestReg).addReg(BaseReg);
191 if (BaseReg == ARM::SP) {
193 if (DestReg == ARM::SP && (ThisVal < ((1 << 7)-1) * 4)) {
194 assert((ThisVal & 3) == 0 && "Stack update is not multiple of 4?");
195 Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
196 // FIXME: Fix Thumb1 immediate encoding.
197 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
198 .addReg(BaseReg).addImm(ThisVal/4);
203 // sub rd, sp, so_imm
204 Opc = isSub ? ARM::t2SUBrSPi : ARM::t2ADDrSPi;
205 if (ARM_AM::getT2SOImmVal(NumBytes) != -1) {
208 // FIXME: Move this to ARMAddressingModes.h?
209 unsigned RotAmt = CountLeadingZeros_32(ThisVal);
210 ThisVal = ThisVal & ARM_AM::rotr32(0xff000000U, RotAmt);
211 NumBytes &= ~ThisVal;
212 assert(ARM_AM::getT2SOImmVal(ThisVal) != -1 &&
213 "Bit extraction didn't work?");
216 assert(DestReg != ARM::SP && BaseReg != ARM::SP);
217 Opc = isSub ? ARM::t2SUBri : ARM::t2ADDri;
218 if (ARM_AM::getT2SOImmVal(NumBytes) != -1) {
220 } else if (ThisVal < 4096) {
221 Opc = isSub ? ARM::t2SUBri12 : ARM::t2ADDri12;
224 // FIXME: Move this to ARMAddressingModes.h?
225 unsigned RotAmt = CountLeadingZeros_32(ThisVal);
226 ThisVal = ThisVal & ARM_AM::rotr32(0xff000000U, RotAmt);
227 NumBytes &= ~ThisVal;
228 assert(ARM_AM::getT2SOImmVal(ThisVal) != -1 &&
229 "Bit extraction didn't work?");
233 // Build the new ADD / SUB.
234 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
235 .addReg(BaseReg, RegState::Kill)
243 negativeOffsetOpcode(unsigned opcode)
246 case ARM::t2LDRi12: return ARM::t2LDRi8;
247 case ARM::t2LDRHi12: return ARM::t2LDRHi8;
248 case ARM::t2LDRBi12: return ARM::t2LDRBi8;
249 case ARM::t2LDRSHi12: return ARM::t2LDRSHi8;
250 case ARM::t2LDRSBi12: return ARM::t2LDRSBi8;
251 case ARM::t2STRi12: return ARM::t2STRi8;
252 case ARM::t2STRBi12: return ARM::t2STRBi8;
253 case ARM::t2STRHi12: return ARM::t2STRHi8;
273 positiveOffsetOpcode(unsigned opcode)
276 case ARM::t2LDRi8: return ARM::t2LDRi12;
277 case ARM::t2LDRHi8: return ARM::t2LDRHi12;
278 case ARM::t2LDRBi8: return ARM::t2LDRBi12;
279 case ARM::t2LDRSHi8: return ARM::t2LDRSHi12;
280 case ARM::t2LDRSBi8: return ARM::t2LDRSBi12;
281 case ARM::t2STRi8: return ARM::t2STRi12;
282 case ARM::t2STRBi8: return ARM::t2STRBi12;
283 case ARM::t2STRHi8: return ARM::t2STRHi12;
288 case ARM::t2LDRSHi12:
289 case ARM::t2LDRSBi12:
303 immediateOffsetOpcode(unsigned opcode)
306 case ARM::t2LDRs: return ARM::t2LDRi12;
307 case ARM::t2LDRHs: return ARM::t2LDRHi12;
308 case ARM::t2LDRBs: return ARM::t2LDRBi12;
309 case ARM::t2LDRSHs: return ARM::t2LDRSHi12;
310 case ARM::t2LDRSBs: return ARM::t2LDRSBi12;
311 case ARM::t2STRs: return ARM::t2STRi12;
312 case ARM::t2STRBs: return ARM::t2STRBi12;
313 case ARM::t2STRHs: return ARM::t2STRHi12;
318 case ARM::t2LDRSHi12:
319 case ARM::t2LDRSBi12:
340 bool llvm::rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
341 unsigned FrameReg, int &Offset,
342 const ARMBaseInstrInfo &TII) {
343 unsigned Opcode = MI.getOpcode();
344 const TargetInstrDesc &Desc = MI.getDesc();
345 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
348 // Memory operands in inline assembly always use AddrModeT2_i12.
349 if (Opcode == ARM::INLINEASM)
350 AddrMode = ARMII::AddrModeT2_i12; // FIXME. mode for thumb2?
352 if (Opcode == ARM::t2ADDri || Opcode == ARM::t2ADDri12) {
353 Offset += MI.getOperand(FrameRegIdx+1).getImm();
355 bool isSP = FrameReg == ARM::SP;
357 // Turn it into a move.
358 MI.setDesc(TII.get(ARM::tMOVgpr2gpr));
359 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
360 MI.RemoveOperand(FrameRegIdx+1);
368 MI.setDesc(TII.get(isSP ? ARM::t2SUBrSPi : ARM::t2SUBri));
370 MI.setDesc(TII.get(isSP ? ARM::t2ADDrSPi : ARM::t2ADDri));
373 // Common case: small offset, fits into instruction.
374 if (ARM_AM::getT2SOImmVal(Offset) != -1) {
375 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
376 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
380 // Another common case: imm12.
382 unsigned NewOpc = isSP
383 ? (isSub ? ARM::t2SUBrSPi12 : ARM::t2ADDrSPi12)
384 : (isSub ? ARM::t2SUBri12 : ARM::t2ADDri12);
385 MI.setDesc(TII.get(NewOpc));
386 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
387 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
392 // Otherwise, extract 8 adjacent bits from the immediate into this
394 unsigned RotAmt = CountLeadingZeros_32(Offset);
395 unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xff000000U, RotAmt);
397 // We will handle these bits from offset, clear them.
398 Offset &= ~ThisImmVal;
400 assert(ARM_AM::getT2SOImmVal(ThisImmVal) != -1 &&
401 "Bit extraction didn't work?");
402 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal);
405 // AddrMode4 cannot handle any offset.
406 if (AddrMode == ARMII::AddrMode4)
409 // AddrModeT2_so cannot handle any offset. If there is no offset
410 // register then we change to an immediate version.
411 unsigned NewOpc = Opcode;
412 if (AddrMode == ARMII::AddrModeT2_so) {
413 unsigned OffsetReg = MI.getOperand(FrameRegIdx+1).getReg();
414 if (OffsetReg != 0) {
415 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
419 MI.RemoveOperand(FrameRegIdx+1);
420 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(0);
421 NewOpc = immediateOffsetOpcode(Opcode);
422 AddrMode = ARMII::AddrModeT2_i12;
425 unsigned NumBits = 0;
427 if (AddrMode == ARMII::AddrModeT2_i8 || AddrMode == ARMII::AddrModeT2_i12) {
428 // i8 supports only negative, and i12 supports only positive, so
429 // based on Offset sign convert Opcode to the appropriate
431 Offset += MI.getOperand(FrameRegIdx+1).getImm();
433 NewOpc = negativeOffsetOpcode(Opcode);
438 NewOpc = positiveOffsetOpcode(Opcode);
442 // VFP and NEON address modes.
444 if (AddrMode == ARMII::AddrMode5) {
445 const MachineOperand &OffOp = MI.getOperand(FrameRegIdx+1);
446 InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm());
447 if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM::sub)
452 Offset += InstrOffs * 4;
453 assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
460 if (NewOpc != Opcode)
461 MI.setDesc(TII.get(NewOpc));
463 MachineOperand &ImmOp = MI.getOperand(FrameRegIdx+1);
465 // Attempt to fold address computation
466 // Common case: small offset, fits into instruction.
467 int ImmedOffset = Offset / Scale;
468 unsigned Mask = (1 << NumBits) - 1;
469 if ((unsigned)Offset <= Mask * Scale) {
470 // Replace the FrameIndex with fp/sp
471 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
473 if (AddrMode == ARMII::AddrMode5)
474 // FIXME: Not consistent.
475 ImmedOffset |= 1 << NumBits;
477 ImmedOffset = -ImmedOffset;
479 ImmOp.ChangeToImmediate(ImmedOffset);
484 // Otherwise, offset doesn't fit. Pull in what we can to simplify
485 ImmedOffset = ImmedOffset & Mask;
487 if (AddrMode == ARMII::AddrMode5)
488 // FIXME: Not consistent.
489 ImmedOffset |= 1 << NumBits;
491 ImmedOffset = -ImmedOffset;
492 if (ImmedOffset == 0)
493 // Change the opcode back if the encoded offset is zero.
494 MI.setDesc(TII.get(positiveOffsetOpcode(NewOpc)));
497 ImmOp.ChangeToImmediate(ImmedOffset);
498 Offset &= ~(Mask*Scale);
501 Offset = (isSub) ? -Offset : Offset;