1 //===- Thumb2InstrInfo.cpp - Thumb-2 Instruction Information ----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Thumb-2 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "Thumb2InstrInfo.h"
16 #include "ARMConstantPoolValue.h"
17 #include "ARMAddressingModes.h"
18 #include "ARMGenInstrInfo.inc"
19 #include "ARMMachineFunctionInfo.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineMemOperand.h"
23 #include "llvm/CodeGen/PseudoSourceValue.h"
24 #include "llvm/ADT/SmallVector.h"
25 #include "Thumb2InstrInfo.h"
29 Thumb2InstrInfo::Thumb2InstrInfo(const ARMSubtarget &STI)
30 : ARMBaseInstrInfo(STI), RI(*this, STI) {
33 unsigned Thumb2InstrInfo::getUnindexedOpcode(unsigned Opc) const {
39 Thumb2InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
40 MachineBasicBlock::iterator I,
41 unsigned DestReg, unsigned SrcReg,
42 const TargetRegisterClass *DestRC,
43 const TargetRegisterClass *SrcRC) const {
44 DebugLoc DL = DebugLoc::getUnknownLoc();
45 if (I != MBB.end()) DL = I->getDebugLoc();
47 if (DestRC == ARM::GPRRegisterClass &&
48 SrcRC == ARM::GPRRegisterClass) {
49 BuildMI(MBB, I, DL, get(ARM::tMOVgpr2gpr), DestReg).addReg(SrcReg);
51 } else if (DestRC == ARM::GPRRegisterClass &&
52 SrcRC == ARM::tGPRRegisterClass) {
53 BuildMI(MBB, I, DL, get(ARM::tMOVtgpr2gpr), DestReg).addReg(SrcReg);
55 } else if (DestRC == ARM::tGPRRegisterClass &&
56 SrcRC == ARM::GPRRegisterClass) {
57 BuildMI(MBB, I, DL, get(ARM::tMOVgpr2tgpr), DestReg).addReg(SrcReg);
61 // Handle SPR, DPR, and QPR copies.
62 return ARMBaseInstrInfo::copyRegToReg(MBB, I, DestReg, SrcReg, DestRC, SrcRC);
65 void Thumb2InstrInfo::
66 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
67 unsigned SrcReg, bool isKill, int FI,
68 const TargetRegisterClass *RC) const {
69 DebugLoc DL = DebugLoc::getUnknownLoc();
70 if (I != MBB.end()) DL = I->getDebugLoc();
72 if (RC == ARM::GPRRegisterClass) {
73 MachineFunction &MF = *MBB.getParent();
74 MachineFrameInfo &MFI = *MF.getFrameInfo();
75 MachineMemOperand *MMO =
76 MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI),
77 MachineMemOperand::MOStore, 0,
78 MFI.getObjectSize(FI),
79 MFI.getObjectAlignment(FI));
80 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::t2STRi12))
81 .addReg(SrcReg, getKillRegState(isKill))
82 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
86 ARMBaseInstrInfo::storeRegToStackSlot(MBB, I, SrcReg, isKill, FI, RC);
89 void Thumb2InstrInfo::
90 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
91 unsigned DestReg, int FI,
92 const TargetRegisterClass *RC) const {
93 DebugLoc DL = DebugLoc::getUnknownLoc();
94 if (I != MBB.end()) DL = I->getDebugLoc();
96 if (RC == ARM::GPRRegisterClass) {
97 MachineFunction &MF = *MBB.getParent();
98 MachineFrameInfo &MFI = *MF.getFrameInfo();
99 MachineMemOperand *MMO =
100 MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI),
101 MachineMemOperand::MOLoad, 0,
102 MFI.getObjectSize(FI),
103 MFI.getObjectAlignment(FI));
104 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::t2LDRi12), DestReg)
105 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
109 ARMBaseInstrInfo::loadRegFromStackSlot(MBB, I, DestReg, FI, RC);
112 void llvm::emitT2RegPlusImmediate(MachineBasicBlock &MBB,
113 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
114 unsigned DestReg, unsigned BaseReg, int NumBytes,
115 ARMCC::CondCodes Pred, unsigned PredReg,
116 const ARMBaseInstrInfo &TII) {
117 bool isSub = NumBytes < 0;
118 if (isSub) NumBytes = -NumBytes;
120 // If profitable, use a movw or movt to materialize the offset.
121 // FIXME: Use the scavenger to grab a scratch register.
122 if (DestReg != ARM::SP && DestReg != BaseReg &&
124 ARM_AM::getT2SOImmVal(NumBytes) == -1) {
126 if (NumBytes < 65536) {
127 // Use a movw to materialize the 16-bit constant.
128 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi16), DestReg)
130 .addImm((unsigned)Pred).addReg(PredReg).addReg(0);
132 } else if ((NumBytes & 0xffff) == 0) {
133 // Use a movt to materialize the 32-bit constant.
134 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVTi16), DestReg)
136 .addImm(NumBytes >> 16)
137 .addImm((unsigned)Pred).addReg(PredReg).addReg(0);
143 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2SUBrr), DestReg)
144 .addReg(BaseReg, RegState::Kill)
145 .addReg(DestReg, RegState::Kill)
146 .addImm((unsigned)Pred).addReg(PredReg).addReg(0);
148 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2ADDrr), DestReg)
149 .addReg(DestReg, RegState::Kill)
150 .addReg(BaseReg, RegState::Kill)
151 .addImm((unsigned)Pred).addReg(PredReg).addReg(0);
158 unsigned ThisVal = NumBytes;
160 if (DestReg == ARM::SP && BaseReg != ARM::SP) {
161 // mov sp, rn. Note t2MOVr cannot be used.
162 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr),DestReg).addReg(BaseReg);
167 if (BaseReg == ARM::SP) {
169 if (DestReg == ARM::SP && (ThisVal < ((1 << 7)-1) * 4)) {
170 assert((ThisVal & 3) == 0 && "Stack update is not multiple of 4?");
171 Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
172 // FIXME: Fix Thumb1 immediate encoding.
173 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
174 .addReg(BaseReg).addImm(ThisVal/4);
179 // sub rd, sp, so_imm
180 Opc = isSub ? ARM::t2SUBrSPi : ARM::t2ADDrSPi;
181 if (ARM_AM::getT2SOImmVal(NumBytes) != -1) {
184 // FIXME: Move this to ARMAddressingModes.h?
185 unsigned RotAmt = CountLeadingZeros_32(ThisVal);
186 ThisVal = ThisVal & ARM_AM::rotr32(0xff000000U, RotAmt);
187 NumBytes &= ~ThisVal;
188 assert(ARM_AM::getT2SOImmVal(ThisVal) != -1 &&
189 "Bit extraction didn't work?");
192 assert(DestReg != ARM::SP && BaseReg != ARM::SP);
193 Opc = isSub ? ARM::t2SUBri : ARM::t2ADDri;
194 if (ARM_AM::getT2SOImmVal(NumBytes) != -1) {
196 } else if (ThisVal < 4096) {
197 Opc = isSub ? ARM::t2SUBri12 : ARM::t2ADDri12;
200 // FIXME: Move this to ARMAddressingModes.h?
201 unsigned RotAmt = CountLeadingZeros_32(ThisVal);
202 ThisVal = ThisVal & ARM_AM::rotr32(0xff000000U, RotAmt);
203 NumBytes &= ~ThisVal;
204 assert(ARM_AM::getT2SOImmVal(ThisVal) != -1 &&
205 "Bit extraction didn't work?");
209 // Build the new ADD / SUB.
210 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
211 .addReg(BaseReg, RegState::Kill)
219 negativeOffsetOpcode(unsigned opcode)
222 case ARM::t2LDRi12: return ARM::t2LDRi8;
223 case ARM::t2LDRHi12: return ARM::t2LDRHi8;
224 case ARM::t2LDRBi12: return ARM::t2LDRBi8;
225 case ARM::t2LDRSHi12: return ARM::t2LDRSHi8;
226 case ARM::t2LDRSBi12: return ARM::t2LDRSBi8;
227 case ARM::t2STRi12: return ARM::t2STRi8;
228 case ARM::t2STRBi12: return ARM::t2STRBi8;
229 case ARM::t2STRHi12: return ARM::t2STRHi8;
249 positiveOffsetOpcode(unsigned opcode)
252 case ARM::t2LDRi8: return ARM::t2LDRi12;
253 case ARM::t2LDRHi8: return ARM::t2LDRHi12;
254 case ARM::t2LDRBi8: return ARM::t2LDRBi12;
255 case ARM::t2LDRSHi8: return ARM::t2LDRSHi12;
256 case ARM::t2LDRSBi8: return ARM::t2LDRSBi12;
257 case ARM::t2STRi8: return ARM::t2STRi12;
258 case ARM::t2STRBi8: return ARM::t2STRBi12;
259 case ARM::t2STRHi8: return ARM::t2STRHi12;
264 case ARM::t2LDRSHi12:
265 case ARM::t2LDRSBi12:
279 immediateOffsetOpcode(unsigned opcode)
282 case ARM::t2LDRs: return ARM::t2LDRi12;
283 case ARM::t2LDRHs: return ARM::t2LDRHi12;
284 case ARM::t2LDRBs: return ARM::t2LDRBi12;
285 case ARM::t2LDRSHs: return ARM::t2LDRSHi12;
286 case ARM::t2LDRSBs: return ARM::t2LDRSBi12;
287 case ARM::t2STRs: return ARM::t2STRi12;
288 case ARM::t2STRBs: return ARM::t2STRBi12;
289 case ARM::t2STRHs: return ARM::t2STRHi12;
294 case ARM::t2LDRSHi12:
295 case ARM::t2LDRSBi12:
316 bool llvm::rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
317 unsigned FrameReg, int &Offset,
318 const ARMBaseInstrInfo &TII) {
319 unsigned Opcode = MI.getOpcode();
320 const TargetInstrDesc &Desc = MI.getDesc();
321 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
324 // Memory operands in inline assembly always use AddrModeT2_i12.
325 if (Opcode == ARM::INLINEASM)
326 AddrMode = ARMII::AddrModeT2_i12; // FIXME. mode for thumb2?
328 if (Opcode == ARM::t2ADDri || Opcode == ARM::t2ADDri12) {
329 Offset += MI.getOperand(FrameRegIdx+1).getImm();
331 bool isSP = FrameReg == ARM::SP;
333 if (Offset == 0 && getInstrPredicate(&MI, PredReg) == ARMCC::AL) {
334 // Turn it into a move.
335 MI.setDesc(TII.get(ARM::tMOVgpr2gpr));
336 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
337 // Remove offset and remaining explicit predicate operands.
338 do MI.RemoveOperand(FrameRegIdx+1);
339 while (MI.getNumOperands() > FrameRegIdx+1 &&
340 (!MI.getOperand(FrameRegIdx+1).isReg() ||
341 !MI.getOperand(FrameRegIdx+1).isImm()));
348 MI.setDesc(TII.get(isSP ? ARM::t2SUBrSPi : ARM::t2SUBri));
350 MI.setDesc(TII.get(isSP ? ARM::t2ADDrSPi : ARM::t2ADDri));
353 // Common case: small offset, fits into instruction.
354 if (ARM_AM::getT2SOImmVal(Offset) != -1) {
355 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
356 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
360 // Another common case: imm12.
362 unsigned NewOpc = isSP
363 ? (isSub ? ARM::t2SUBrSPi12 : ARM::t2ADDrSPi12)
364 : (isSub ? ARM::t2SUBri12 : ARM::t2ADDri12);
365 MI.setDesc(TII.get(NewOpc));
366 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
367 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
372 // Otherwise, extract 8 adjacent bits from the immediate into this
374 unsigned RotAmt = CountLeadingZeros_32(Offset);
375 unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xff000000U, RotAmt);
377 // We will handle these bits from offset, clear them.
378 Offset &= ~ThisImmVal;
380 assert(ARM_AM::getT2SOImmVal(ThisImmVal) != -1 &&
381 "Bit extraction didn't work?");
382 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal);
385 // AddrMode4 and AddrMode6 cannot handle any offset.
386 if (AddrMode == ARMII::AddrMode4 || AddrMode == ARMII::AddrMode6)
389 // AddrModeT2_so cannot handle any offset. If there is no offset
390 // register then we change to an immediate version.
391 unsigned NewOpc = Opcode;
392 if (AddrMode == ARMII::AddrModeT2_so) {
393 unsigned OffsetReg = MI.getOperand(FrameRegIdx+1).getReg();
394 if (OffsetReg != 0) {
395 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
399 MI.RemoveOperand(FrameRegIdx+1);
400 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(0);
401 NewOpc = immediateOffsetOpcode(Opcode);
402 AddrMode = ARMII::AddrModeT2_i12;
405 unsigned NumBits = 0;
407 if (AddrMode == ARMII::AddrModeT2_i8 || AddrMode == ARMII::AddrModeT2_i12) {
408 // i8 supports only negative, and i12 supports only positive, so
409 // based on Offset sign convert Opcode to the appropriate
411 Offset += MI.getOperand(FrameRegIdx+1).getImm();
413 NewOpc = negativeOffsetOpcode(Opcode);
418 NewOpc = positiveOffsetOpcode(Opcode);
421 } else if (AddrMode == ARMII::AddrMode5) {
423 const MachineOperand &OffOp = MI.getOperand(FrameRegIdx+1);
424 int InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm());
425 if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM::sub)
429 Offset += InstrOffs * 4;
430 assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
436 llvm_unreachable("Unsupported addressing mode!");
439 if (NewOpc != Opcode)
440 MI.setDesc(TII.get(NewOpc));
442 MachineOperand &ImmOp = MI.getOperand(FrameRegIdx+1);
444 // Attempt to fold address computation
445 // Common case: small offset, fits into instruction.
446 int ImmedOffset = Offset / Scale;
447 unsigned Mask = (1 << NumBits) - 1;
448 if ((unsigned)Offset <= Mask * Scale) {
449 // Replace the FrameIndex with fp/sp
450 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
452 if (AddrMode == ARMII::AddrMode5)
453 // FIXME: Not consistent.
454 ImmedOffset |= 1 << NumBits;
456 ImmedOffset = -ImmedOffset;
458 ImmOp.ChangeToImmediate(ImmedOffset);
463 // Otherwise, offset doesn't fit. Pull in what we can to simplify
464 ImmedOffset = ImmedOffset & Mask;
466 if (AddrMode == ARMII::AddrMode5)
467 // FIXME: Not consistent.
468 ImmedOffset |= 1 << NumBits;
470 ImmedOffset = -ImmedOffset;
471 if (ImmedOffset == 0)
472 // Change the opcode back if the encoded offset is zero.
473 MI.setDesc(TII.get(positiveOffsetOpcode(NewOpc)));
476 ImmOp.ChangeToImmediate(ImmedOffset);
477 Offset &= ~(Mask*Scale);
480 Offset = (isSub) ? -Offset : Offset;