1 //===-- Thumb2InstrInfo.cpp - Thumb-2 Instruction Information -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Thumb-2 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "Thumb2InstrInfo.h"
16 #include "ARMConstantPoolValue.h"
17 #include "ARMMachineFunctionInfo.h"
18 #include "MCTargetDesc/ARMAddressingModes.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/MachineMemOperand.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/MC/MCInst.h"
24 #include "llvm/Support/CommandLine.h"
29 OldT2IfCvt("old-thumb2-ifcvt", cl::Hidden,
30 cl::desc("Use old-style Thumb2 if-conversion heuristics"),
33 Thumb2InstrInfo::Thumb2InstrInfo(const ARMSubtarget &STI)
34 : ARMBaseInstrInfo(STI), RI(STI) {
37 /// getNoopForMachoTarget - Return the noop instruction to use for a noop.
38 void Thumb2InstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {
39 NopInst.setOpcode(ARM::tNOP);
40 NopInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
41 NopInst.addOperand(MCOperand::CreateReg(0));
44 unsigned Thumb2InstrInfo::getUnindexedOpcode(unsigned Opc) const {
50 Thumb2InstrInfo::ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail,
51 MachineBasicBlock *NewDest) const {
52 MachineBasicBlock *MBB = Tail->getParent();
53 ARMFunctionInfo *AFI = MBB->getParent()->getInfo<ARMFunctionInfo>();
54 if (!AFI->hasITBlocks()) {
55 TargetInstrInfo::ReplaceTailWithBranchTo(Tail, NewDest);
59 // If the first instruction of Tail is predicated, we may have to update
60 // the IT instruction.
62 ARMCC::CondCodes CC = getInstrPredicate(Tail, PredReg);
63 MachineBasicBlock::iterator MBBI = Tail;
65 // Expecting at least the t2IT instruction before it.
68 // Actually replace the tail.
69 TargetInstrInfo::ReplaceTailWithBranchTo(Tail, NewDest);
72 if (CC != ARMCC::AL) {
73 MachineBasicBlock::iterator E = MBB->begin();
74 unsigned Count = 4; // At most 4 instructions in an IT block.
75 while (Count && MBBI != E) {
76 if (MBBI->isDebugValue()) {
80 if (MBBI->getOpcode() == ARM::t2IT) {
81 unsigned Mask = MBBI->getOperand(1).getImm();
83 MBBI->eraseFromParent();
85 unsigned MaskOn = 1 << Count;
86 unsigned MaskOff = ~(MaskOn - 1);
87 MBBI->getOperand(1).setImm((Mask & MaskOff) | MaskOn);
95 // Ctrl flow can reach here if branch folding is run before IT block
101 Thumb2InstrInfo::isLegalToSplitMBBAt(MachineBasicBlock &MBB,
102 MachineBasicBlock::iterator MBBI) const {
103 while (MBBI->isDebugValue()) {
105 if (MBBI == MBB.end())
109 unsigned PredReg = 0;
110 return getITInstrPredicate(MBBI, PredReg) == ARMCC::AL;
113 void Thumb2InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
114 MachineBasicBlock::iterator I, DebugLoc DL,
115 unsigned DestReg, unsigned SrcReg,
116 bool KillSrc) const {
117 // Handle SPR, DPR, and QPR copies.
118 if (!ARM::GPRRegClass.contains(DestReg, SrcReg))
119 return ARMBaseInstrInfo::copyPhysReg(MBB, I, DL, DestReg, SrcReg, KillSrc);
121 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg)
122 .addReg(SrcReg, getKillRegState(KillSrc)));
125 void Thumb2InstrInfo::
126 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
127 unsigned SrcReg, bool isKill, int FI,
128 const TargetRegisterClass *RC,
129 const TargetRegisterInfo *TRI) const {
131 if (I != MBB.end()) DL = I->getDebugLoc();
133 MachineFunction &MF = *MBB.getParent();
134 MachineFrameInfo &MFI = *MF.getFrameInfo();
135 MachineMemOperand *MMO =
136 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
137 MachineMemOperand::MOStore,
138 MFI.getObjectSize(FI),
139 MFI.getObjectAlignment(FI));
141 if (RC == &ARM::GPRRegClass || RC == &ARM::tGPRRegClass ||
142 RC == &ARM::tcGPRRegClass || RC == &ARM::rGPRRegClass ||
143 RC == &ARM::GPRnopcRegClass) {
144 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::t2STRi12))
145 .addReg(SrcReg, getKillRegState(isKill))
146 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
150 if (ARM::GPRPairRegClass.hasSubClassEq(RC)) {
151 // Thumb2 STRD expects its dest-registers to be in rGPR. Not a problem for
152 // gsub_0, but needs an extra constraint for gsub_1 (which could be sp
154 MachineRegisterInfo *MRI = &MF.getRegInfo();
155 MRI->constrainRegClass(SrcReg, &ARM::GPRPair_with_gsub_1_in_rGPRRegClass);
157 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::t2STRDi8));
158 AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI);
159 AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI);
160 MIB.addFrameIndex(FI).addImm(0).addMemOperand(MMO);
165 ARMBaseInstrInfo::storeRegToStackSlot(MBB, I, SrcReg, isKill, FI, RC, TRI);
168 void Thumb2InstrInfo::
169 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
170 unsigned DestReg, int FI,
171 const TargetRegisterClass *RC,
172 const TargetRegisterInfo *TRI) const {
173 MachineFunction &MF = *MBB.getParent();
174 MachineFrameInfo &MFI = *MF.getFrameInfo();
175 MachineMemOperand *MMO =
176 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
177 MachineMemOperand::MOLoad,
178 MFI.getObjectSize(FI),
179 MFI.getObjectAlignment(FI));
181 if (I != MBB.end()) DL = I->getDebugLoc();
183 if (RC == &ARM::GPRRegClass || RC == &ARM::tGPRRegClass ||
184 RC == &ARM::tcGPRRegClass || RC == &ARM::rGPRRegClass ||
185 RC == &ARM::GPRnopcRegClass) {
186 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::t2LDRi12), DestReg)
187 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
191 if (ARM::GPRPairRegClass.hasSubClassEq(RC)) {
192 // Thumb2 LDRD expects its dest-registers to be in rGPR. Not a problem for
193 // gsub_0, but needs an extra constraint for gsub_1 (which could be sp
195 MachineRegisterInfo *MRI = &MF.getRegInfo();
196 MRI->constrainRegClass(DestReg, &ARM::GPRPair_with_gsub_1_in_rGPRRegClass);
198 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::t2LDRDi8));
199 AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI);
200 AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI);
201 MIB.addFrameIndex(FI).addImm(0).addMemOperand(MMO);
204 if (TargetRegisterInfo::isPhysicalRegister(DestReg))
205 MIB.addReg(DestReg, RegState::ImplicitDefine);
209 ARMBaseInstrInfo::loadRegFromStackSlot(MBB, I, DestReg, FI, RC, TRI);
212 void llvm::emitT2RegPlusImmediate(MachineBasicBlock &MBB,
213 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
214 unsigned DestReg, unsigned BaseReg, int NumBytes,
215 ARMCC::CondCodes Pred, unsigned PredReg,
216 const ARMBaseInstrInfo &TII, unsigned MIFlags) {
217 bool isSub = NumBytes < 0;
218 if (isSub) NumBytes = -NumBytes;
220 // If profitable, use a movw or movt to materialize the offset.
221 // FIXME: Use the scavenger to grab a scratch register.
222 if (DestReg != ARM::SP && DestReg != BaseReg &&
224 ARM_AM::getT2SOImmVal(NumBytes) == -1) {
226 if (NumBytes < 65536) {
227 // Use a movw to materialize the 16-bit constant.
228 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi16), DestReg)
230 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags);
232 } else if ((NumBytes & 0xffff) == 0) {
233 // Use a movt to materialize the 32-bit constant.
234 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVTi16), DestReg)
236 .addImm(NumBytes >> 16)
237 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags);
243 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2SUBrr), DestReg)
244 .addReg(BaseReg, RegState::Kill)
245 .addReg(DestReg, RegState::Kill)
246 .addImm((unsigned)Pred).addReg(PredReg).addReg(0)
247 .setMIFlags(MIFlags);
249 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2ADDrr), DestReg)
250 .addReg(DestReg, RegState::Kill)
251 .addReg(BaseReg, RegState::Kill)
252 .addImm((unsigned)Pred).addReg(PredReg).addReg(0)
253 .setMIFlags(MIFlags);
260 unsigned ThisVal = NumBytes;
262 if (DestReg == ARM::SP && BaseReg != ARM::SP) {
263 // mov sp, rn. Note t2MOVr cannot be used.
264 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),DestReg)
265 .addReg(BaseReg).setMIFlags(MIFlags));
270 bool HasCCOut = true;
271 if (BaseReg == ARM::SP) {
273 if (DestReg == ARM::SP && (ThisVal < ((1 << 7)-1) * 4)) {
274 assert((ThisVal & 3) == 0 && "Stack update is not multiple of 4?");
275 Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
276 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
277 .addReg(BaseReg).addImm(ThisVal/4).setMIFlags(MIFlags));
282 // sub rd, sp, so_imm
283 Opc = isSub ? ARM::t2SUBri : ARM::t2ADDri;
284 if (ARM_AM::getT2SOImmVal(NumBytes) != -1) {
287 // FIXME: Move this to ARMAddressingModes.h?
288 unsigned RotAmt = countLeadingZeros(ThisVal);
289 ThisVal = ThisVal & ARM_AM::rotr32(0xff000000U, RotAmt);
290 NumBytes &= ~ThisVal;
291 assert(ARM_AM::getT2SOImmVal(ThisVal) != -1 &&
292 "Bit extraction didn't work?");
295 assert(DestReg != ARM::SP && BaseReg != ARM::SP);
296 Opc = isSub ? ARM::t2SUBri : ARM::t2ADDri;
297 if (ARM_AM::getT2SOImmVal(NumBytes) != -1) {
299 } else if (ThisVal < 4096) {
300 Opc = isSub ? ARM::t2SUBri12 : ARM::t2ADDri12;
304 // FIXME: Move this to ARMAddressingModes.h?
305 unsigned RotAmt = countLeadingZeros(ThisVal);
306 ThisVal = ThisVal & ARM_AM::rotr32(0xff000000U, RotAmt);
307 NumBytes &= ~ThisVal;
308 assert(ARM_AM::getT2SOImmVal(ThisVal) != -1 &&
309 "Bit extraction didn't work?");
313 // Build the new ADD / SUB.
314 MachineInstrBuilder MIB =
315 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
316 .addReg(BaseReg, RegState::Kill)
317 .addImm(ThisVal)).setMIFlags(MIFlags);
326 negativeOffsetOpcode(unsigned opcode)
329 case ARM::t2LDRi12: return ARM::t2LDRi8;
330 case ARM::t2LDRHi12: return ARM::t2LDRHi8;
331 case ARM::t2LDRBi12: return ARM::t2LDRBi8;
332 case ARM::t2LDRSHi12: return ARM::t2LDRSHi8;
333 case ARM::t2LDRSBi12: return ARM::t2LDRSBi8;
334 case ARM::t2STRi12: return ARM::t2STRi8;
335 case ARM::t2STRBi12: return ARM::t2STRBi8;
336 case ARM::t2STRHi12: return ARM::t2STRHi8;
356 positiveOffsetOpcode(unsigned opcode)
359 case ARM::t2LDRi8: return ARM::t2LDRi12;
360 case ARM::t2LDRHi8: return ARM::t2LDRHi12;
361 case ARM::t2LDRBi8: return ARM::t2LDRBi12;
362 case ARM::t2LDRSHi8: return ARM::t2LDRSHi12;
363 case ARM::t2LDRSBi8: return ARM::t2LDRSBi12;
364 case ARM::t2STRi8: return ARM::t2STRi12;
365 case ARM::t2STRBi8: return ARM::t2STRBi12;
366 case ARM::t2STRHi8: return ARM::t2STRHi12;
371 case ARM::t2LDRSHi12:
372 case ARM::t2LDRSBi12:
386 immediateOffsetOpcode(unsigned opcode)
389 case ARM::t2LDRs: return ARM::t2LDRi12;
390 case ARM::t2LDRHs: return ARM::t2LDRHi12;
391 case ARM::t2LDRBs: return ARM::t2LDRBi12;
392 case ARM::t2LDRSHs: return ARM::t2LDRSHi12;
393 case ARM::t2LDRSBs: return ARM::t2LDRSBi12;
394 case ARM::t2STRs: return ARM::t2STRi12;
395 case ARM::t2STRBs: return ARM::t2STRBi12;
396 case ARM::t2STRHs: return ARM::t2STRHi12;
401 case ARM::t2LDRSHi12:
402 case ARM::t2LDRSBi12:
423 bool llvm::rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
424 unsigned FrameReg, int &Offset,
425 const ARMBaseInstrInfo &TII) {
426 unsigned Opcode = MI.getOpcode();
427 const MCInstrDesc &Desc = MI.getDesc();
428 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
431 // Memory operands in inline assembly always use AddrModeT2_i12.
432 if (Opcode == ARM::INLINEASM)
433 AddrMode = ARMII::AddrModeT2_i12; // FIXME. mode for thumb2?
435 if (Opcode == ARM::t2ADDri || Opcode == ARM::t2ADDri12) {
436 Offset += MI.getOperand(FrameRegIdx+1).getImm();
439 if (Offset == 0 && getInstrPredicate(&MI, PredReg) == ARMCC::AL) {
440 // Turn it into a move.
441 MI.setDesc(TII.get(ARM::tMOVr));
442 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
443 // Remove offset and remaining explicit predicate operands.
444 do MI.RemoveOperand(FrameRegIdx+1);
445 while (MI.getNumOperands() > FrameRegIdx+1);
446 MachineInstrBuilder MIB(*MI.getParent()->getParent(), &MI);
451 bool HasCCOut = Opcode != ARM::t2ADDri12;
456 MI.setDesc(TII.get(ARM::t2SUBri));
458 MI.setDesc(TII.get(ARM::t2ADDri));
461 // Common case: small offset, fits into instruction.
462 if (ARM_AM::getT2SOImmVal(Offset) != -1) {
463 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
464 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
465 // Add cc_out operand if the original instruction did not have one.
467 MI.addOperand(MachineOperand::CreateReg(0, false));
471 // Another common case: imm12.
473 (!HasCCOut || MI.getOperand(MI.getNumOperands()-1).getReg() == 0)) {
474 unsigned NewOpc = isSub ? ARM::t2SUBri12 : ARM::t2ADDri12;
475 MI.setDesc(TII.get(NewOpc));
476 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
477 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
478 // Remove the cc_out operand.
480 MI.RemoveOperand(MI.getNumOperands()-1);
485 // Otherwise, extract 8 adjacent bits from the immediate into this
487 unsigned RotAmt = countLeadingZeros<unsigned>(Offset);
488 unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xff000000U, RotAmt);
490 // We will handle these bits from offset, clear them.
491 Offset &= ~ThisImmVal;
493 assert(ARM_AM::getT2SOImmVal(ThisImmVal) != -1 &&
494 "Bit extraction didn't work?");
495 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal);
496 // Add cc_out operand if the original instruction did not have one.
498 MI.addOperand(MachineOperand::CreateReg(0, false));
502 // AddrMode4 and AddrMode6 cannot handle any offset.
503 if (AddrMode == ARMII::AddrMode4 || AddrMode == ARMII::AddrMode6)
506 // AddrModeT2_so cannot handle any offset. If there is no offset
507 // register then we change to an immediate version.
508 unsigned NewOpc = Opcode;
509 if (AddrMode == ARMII::AddrModeT2_so) {
510 unsigned OffsetReg = MI.getOperand(FrameRegIdx+1).getReg();
511 if (OffsetReg != 0) {
512 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
516 MI.RemoveOperand(FrameRegIdx+1);
517 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(0);
518 NewOpc = immediateOffsetOpcode(Opcode);
519 AddrMode = ARMII::AddrModeT2_i12;
522 unsigned NumBits = 0;
524 if (AddrMode == ARMII::AddrModeT2_i8 || AddrMode == ARMII::AddrModeT2_i12) {
525 // i8 supports only negative, and i12 supports only positive, so
526 // based on Offset sign convert Opcode to the appropriate
528 Offset += MI.getOperand(FrameRegIdx+1).getImm();
530 NewOpc = negativeOffsetOpcode(Opcode);
535 NewOpc = positiveOffsetOpcode(Opcode);
538 } else if (AddrMode == ARMII::AddrMode5) {
540 const MachineOperand &OffOp = MI.getOperand(FrameRegIdx+1);
541 int InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm());
542 if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM::sub)
546 Offset += InstrOffs * 4;
547 assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
552 } else if (AddrMode == ARMII::AddrModeT2_i8s4) {
553 Offset += MI.getOperand(FrameRegIdx + 1).getImm() * 4;
555 // MCInst operand has already scaled value.
562 llvm_unreachable("Unsupported addressing mode!");
565 if (NewOpc != Opcode)
566 MI.setDesc(TII.get(NewOpc));
568 MachineOperand &ImmOp = MI.getOperand(FrameRegIdx+1);
570 // Attempt to fold address computation
571 // Common case: small offset, fits into instruction.
572 int ImmedOffset = Offset / Scale;
573 unsigned Mask = (1 << NumBits) - 1;
574 if ((unsigned)Offset <= Mask * Scale) {
575 // Replace the FrameIndex with fp/sp
576 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
578 if (AddrMode == ARMII::AddrMode5)
579 // FIXME: Not consistent.
580 ImmedOffset |= 1 << NumBits;
582 ImmedOffset = -ImmedOffset;
584 ImmOp.ChangeToImmediate(ImmedOffset);
589 // Otherwise, offset doesn't fit. Pull in what we can to simplify
590 ImmedOffset = ImmedOffset & Mask;
592 if (AddrMode == ARMII::AddrMode5)
593 // FIXME: Not consistent.
594 ImmedOffset |= 1 << NumBits;
596 ImmedOffset = -ImmedOffset;
597 if (ImmedOffset == 0)
598 // Change the opcode back if the encoded offset is zero.
599 MI.setDesc(TII.get(positiveOffsetOpcode(NewOpc)));
602 ImmOp.ChangeToImmediate(ImmedOffset);
603 Offset &= ~(Mask*Scale);
606 Offset = (isSub) ? -Offset : Offset;
611 llvm::getITInstrPredicate(const MachineInstr *MI, unsigned &PredReg) {
612 unsigned Opc = MI->getOpcode();
613 if (Opc == ARM::tBcc || Opc == ARM::t2Bcc)
615 return getInstrPredicate(MI, PredReg);