1 //===- Thumb2InstrInfo.cpp - Thumb-2 Instruction Information ----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Thumb-2 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "Thumb2InstrInfo.h"
16 #include "ARMConstantPoolValue.h"
17 #include "ARMAddressingModes.h"
18 #include "ARMGenInstrInfo.inc"
19 #include "ARMMachineFunctionInfo.h"
20 #include "Thumb2HazardRecognizer.h"
21 #include "Thumb2InstrInfo.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineMemOperand.h"
25 #include "llvm/CodeGen/PseudoSourceValue.h"
26 #include "llvm/ADT/SmallVector.h"
27 #include "llvm/Support/CommandLine.h"
31 Thumb2InstrInfo::Thumb2InstrInfo(const ARMSubtarget &STI)
32 : ARMBaseInstrInfo(STI), RI(*this, STI) {
35 unsigned Thumb2InstrInfo::getUnindexedOpcode(unsigned Opc) const {
41 Thumb2InstrInfo::ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail,
42 MachineBasicBlock *NewDest) const {
43 MachineBasicBlock *MBB = Tail->getParent();
44 ARMFunctionInfo *AFI = MBB->getParent()->getInfo<ARMFunctionInfo>();
45 if (!AFI->hasITBlocks()) {
46 TargetInstrInfoImpl::ReplaceTailWithBranchTo(Tail, NewDest);
50 // If the first instruction of Tail is predicated, we may have to update
51 // the IT instruction.
53 ARMCC::CondCodes CC = llvm::getInstrPredicate(Tail, PredReg);
54 MachineBasicBlock::iterator MBBI = Tail;
56 // Expecting at least the t2IT instruction before it.
59 // Actually replace the tail.
60 TargetInstrInfoImpl::ReplaceTailWithBranchTo(Tail, NewDest);
63 if (CC != ARMCC::AL) {
64 MachineBasicBlock::iterator E = MBB->begin();
65 unsigned Count = 4; // At most 4 instructions in an IT block.
66 while (Count && MBBI != E) {
67 if (MBBI->isDebugValue()) {
71 if (MBBI->getOpcode() == ARM::t2IT) {
72 unsigned Mask = MBBI->getOperand(1).getImm();
74 MBBI->eraseFromParent();
76 unsigned MaskOn = 1 << Count;
77 unsigned MaskOff = ~(MaskOn - 1);
78 MBBI->getOperand(1).setImm((Mask & MaskOff) | MaskOn);
86 // Ctrl flow can reach here if branch folding is run before IT block
92 Thumb2InstrInfo::isLegalToSplitMBBAt(MachineBasicBlock &MBB,
93 MachineBasicBlock::iterator MBBI) const {
95 return llvm::getITInstrPredicate(MBBI, PredReg) == ARMCC::AL;
98 void Thumb2InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
99 MachineBasicBlock::iterator I, DebugLoc DL,
100 unsigned DestReg, unsigned SrcReg,
101 bool KillSrc) const {
102 // Handle SPR, DPR, and QPR copies.
103 if (!ARM::GPRRegClass.contains(DestReg, SrcReg))
104 return ARMBaseInstrInfo::copyPhysReg(MBB, I, DL, DestReg, SrcReg, KillSrc);
106 bool tDest = ARM::tGPRRegClass.contains(DestReg);
107 bool tSrc = ARM::tGPRRegClass.contains(SrcReg);
108 unsigned Opc = ARM::tMOVgpr2gpr;
112 Opc = ARM::tMOVtgpr2gpr;
114 Opc = ARM::tMOVgpr2tgpr;
116 BuildMI(MBB, I, DL, get(Opc), DestReg)
117 .addReg(SrcReg, getKillRegState(KillSrc));
120 void Thumb2InstrInfo::
121 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
122 unsigned SrcReg, bool isKill, int FI,
123 const TargetRegisterClass *RC,
124 const TargetRegisterInfo *TRI) const {
125 if (RC == ARM::GPRRegisterClass || RC == ARM::tGPRRegisterClass ||
126 RC == ARM::tcGPRRegisterClass || RC == ARM::rGPRRegisterClass) {
128 if (I != MBB.end()) DL = I->getDebugLoc();
130 MachineFunction &MF = *MBB.getParent();
131 MachineFrameInfo &MFI = *MF.getFrameInfo();
132 MachineMemOperand *MMO =
133 MF.getMachineMemOperand(
134 MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)),
135 MachineMemOperand::MOStore,
136 MFI.getObjectSize(FI),
137 MFI.getObjectAlignment(FI));
138 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::t2STRi12))
139 .addReg(SrcReg, getKillRegState(isKill))
140 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
144 ARMBaseInstrInfo::storeRegToStackSlot(MBB, I, SrcReg, isKill, FI, RC, TRI);
147 void Thumb2InstrInfo::
148 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
149 unsigned DestReg, int FI,
150 const TargetRegisterClass *RC,
151 const TargetRegisterInfo *TRI) const {
152 if (RC == ARM::GPRRegisterClass || RC == ARM::tGPRRegisterClass ||
153 RC == ARM::tcGPRRegisterClass || RC == ARM::rGPRRegisterClass) {
155 if (I != MBB.end()) DL = I->getDebugLoc();
157 MachineFunction &MF = *MBB.getParent();
158 MachineFrameInfo &MFI = *MF.getFrameInfo();
159 MachineMemOperand *MMO =
160 MF.getMachineMemOperand(
161 MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)),
162 MachineMemOperand::MOLoad,
163 MFI.getObjectSize(FI),
164 MFI.getObjectAlignment(FI));
165 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::t2LDRi12), DestReg)
166 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
170 ARMBaseInstrInfo::loadRegFromStackSlot(MBB, I, DestReg, FI, RC, TRI);
173 ScheduleHazardRecognizer *Thumb2InstrInfo::
174 CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II) const {
175 return (ScheduleHazardRecognizer *)new Thumb2HazardRecognizer(II);
178 void llvm::emitT2RegPlusImmediate(MachineBasicBlock &MBB,
179 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
180 unsigned DestReg, unsigned BaseReg, int NumBytes,
181 ARMCC::CondCodes Pred, unsigned PredReg,
182 const ARMBaseInstrInfo &TII) {
183 bool isSub = NumBytes < 0;
184 if (isSub) NumBytes = -NumBytes;
186 // If profitable, use a movw or movt to materialize the offset.
187 // FIXME: Use the scavenger to grab a scratch register.
188 if (DestReg != ARM::SP && DestReg != BaseReg &&
190 ARM_AM::getT2SOImmVal(NumBytes) == -1) {
192 if (NumBytes < 65536) {
193 // Use a movw to materialize the 16-bit constant.
194 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi16), DestReg)
196 .addImm((unsigned)Pred).addReg(PredReg);
198 } else if ((NumBytes & 0xffff) == 0) {
199 // Use a movt to materialize the 32-bit constant.
200 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVTi16), DestReg)
202 .addImm(NumBytes >> 16)
203 .addImm((unsigned)Pred).addReg(PredReg);
209 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2SUBrr), DestReg)
210 .addReg(BaseReg, RegState::Kill)
211 .addReg(DestReg, RegState::Kill)
212 .addImm((unsigned)Pred).addReg(PredReg).addReg(0);
214 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2ADDrr), DestReg)
215 .addReg(DestReg, RegState::Kill)
216 .addReg(BaseReg, RegState::Kill)
217 .addImm((unsigned)Pred).addReg(PredReg).addReg(0);
224 unsigned ThisVal = NumBytes;
226 if (DestReg == ARM::SP && BaseReg != ARM::SP) {
227 // mov sp, rn. Note t2MOVr cannot be used.
228 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr),DestReg).addReg(BaseReg);
233 bool HasCCOut = true;
234 if (BaseReg == ARM::SP) {
236 if (DestReg == ARM::SP && (ThisVal < ((1 << 7)-1) * 4)) {
237 assert((ThisVal & 3) == 0 && "Stack update is not multiple of 4?");
238 Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
239 // FIXME: Fix Thumb1 immediate encoding.
240 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
241 .addReg(BaseReg).addImm(ThisVal/4);
246 // sub rd, sp, so_imm
247 Opc = isSub ? ARM::t2SUBrSPi : ARM::t2ADDrSPi;
248 if (ARM_AM::getT2SOImmVal(NumBytes) != -1) {
251 // FIXME: Move this to ARMAddressingModes.h?
252 unsigned RotAmt = CountLeadingZeros_32(ThisVal);
253 ThisVal = ThisVal & ARM_AM::rotr32(0xff000000U, RotAmt);
254 NumBytes &= ~ThisVal;
255 assert(ARM_AM::getT2SOImmVal(ThisVal) != -1 &&
256 "Bit extraction didn't work?");
259 assert(DestReg != ARM::SP && BaseReg != ARM::SP);
260 Opc = isSub ? ARM::t2SUBri : ARM::t2ADDri;
261 if (ARM_AM::getT2SOImmVal(NumBytes) != -1) {
263 } else if (ThisVal < 4096) {
264 Opc = isSub ? ARM::t2SUBri12 : ARM::t2ADDri12;
268 // FIXME: Move this to ARMAddressingModes.h?
269 unsigned RotAmt = CountLeadingZeros_32(ThisVal);
270 ThisVal = ThisVal & ARM_AM::rotr32(0xff000000U, RotAmt);
271 NumBytes &= ~ThisVal;
272 assert(ARM_AM::getT2SOImmVal(ThisVal) != -1 &&
273 "Bit extraction didn't work?");
277 // Build the new ADD / SUB.
278 MachineInstrBuilder MIB =
279 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
280 .addReg(BaseReg, RegState::Kill)
290 negativeOffsetOpcode(unsigned opcode)
293 case ARM::t2LDRi12: return ARM::t2LDRi8;
294 case ARM::t2LDRHi12: return ARM::t2LDRHi8;
295 case ARM::t2LDRBi12: return ARM::t2LDRBi8;
296 case ARM::t2LDRSHi12: return ARM::t2LDRSHi8;
297 case ARM::t2LDRSBi12: return ARM::t2LDRSBi8;
298 case ARM::t2STRi12: return ARM::t2STRi8;
299 case ARM::t2STRBi12: return ARM::t2STRBi8;
300 case ARM::t2STRHi12: return ARM::t2STRHi8;
320 positiveOffsetOpcode(unsigned opcode)
323 case ARM::t2LDRi8: return ARM::t2LDRi12;
324 case ARM::t2LDRHi8: return ARM::t2LDRHi12;
325 case ARM::t2LDRBi8: return ARM::t2LDRBi12;
326 case ARM::t2LDRSHi8: return ARM::t2LDRSHi12;
327 case ARM::t2LDRSBi8: return ARM::t2LDRSBi12;
328 case ARM::t2STRi8: return ARM::t2STRi12;
329 case ARM::t2STRBi8: return ARM::t2STRBi12;
330 case ARM::t2STRHi8: return ARM::t2STRHi12;
335 case ARM::t2LDRSHi12:
336 case ARM::t2LDRSBi12:
350 immediateOffsetOpcode(unsigned opcode)
353 case ARM::t2LDRs: return ARM::t2LDRi12;
354 case ARM::t2LDRHs: return ARM::t2LDRHi12;
355 case ARM::t2LDRBs: return ARM::t2LDRBi12;
356 case ARM::t2LDRSHs: return ARM::t2LDRSHi12;
357 case ARM::t2LDRSBs: return ARM::t2LDRSBi12;
358 case ARM::t2STRs: return ARM::t2STRi12;
359 case ARM::t2STRBs: return ARM::t2STRBi12;
360 case ARM::t2STRHs: return ARM::t2STRHi12;
365 case ARM::t2LDRSHi12:
366 case ARM::t2LDRSBi12:
387 bool llvm::rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
388 unsigned FrameReg, int &Offset,
389 const ARMBaseInstrInfo &TII) {
390 unsigned Opcode = MI.getOpcode();
391 const TargetInstrDesc &Desc = MI.getDesc();
392 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
395 // Memory operands in inline assembly always use AddrModeT2_i12.
396 if (Opcode == ARM::INLINEASM)
397 AddrMode = ARMII::AddrModeT2_i12; // FIXME. mode for thumb2?
399 if (Opcode == ARM::t2ADDri || Opcode == ARM::t2ADDri12) {
400 Offset += MI.getOperand(FrameRegIdx+1).getImm();
403 if (Offset == 0 && getInstrPredicate(&MI, PredReg) == ARMCC::AL) {
404 // Turn it into a move.
405 MI.setDesc(TII.get(ARM::tMOVgpr2gpr));
406 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
407 // Remove offset and remaining explicit predicate operands.
408 do MI.RemoveOperand(FrameRegIdx+1);
409 while (MI.getNumOperands() > FrameRegIdx+1 &&
410 (!MI.getOperand(FrameRegIdx+1).isReg() ||
411 !MI.getOperand(FrameRegIdx+1).isImm()));
415 bool isSP = FrameReg == ARM::SP;
416 bool HasCCOut = Opcode != ARM::t2ADDri12;
421 MI.setDesc(TII.get(isSP ? ARM::t2SUBrSPi : ARM::t2SUBri));
423 MI.setDesc(TII.get(isSP ? ARM::t2ADDrSPi : ARM::t2ADDri));
426 // Common case: small offset, fits into instruction.
427 if (ARM_AM::getT2SOImmVal(Offset) != -1) {
428 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
429 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
430 // Add cc_out operand if the original instruction did not have one.
432 MI.addOperand(MachineOperand::CreateReg(0, false));
436 // Another common case: imm12.
438 (!HasCCOut || MI.getOperand(MI.getNumOperands()-1).getReg() == 0)) {
439 unsigned NewOpc = isSP
440 ? (isSub ? ARM::t2SUBrSPi12 : ARM::t2ADDrSPi12)
441 : (isSub ? ARM::t2SUBri12 : ARM::t2ADDri12);
442 MI.setDesc(TII.get(NewOpc));
443 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
444 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
445 // Remove the cc_out operand.
447 MI.RemoveOperand(MI.getNumOperands()-1);
452 // Otherwise, extract 8 adjacent bits from the immediate into this
454 unsigned RotAmt = CountLeadingZeros_32(Offset);
455 unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xff000000U, RotAmt);
457 // We will handle these bits from offset, clear them.
458 Offset &= ~ThisImmVal;
460 assert(ARM_AM::getT2SOImmVal(ThisImmVal) != -1 &&
461 "Bit extraction didn't work?");
462 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal);
463 // Add cc_out operand if the original instruction did not have one.
465 MI.addOperand(MachineOperand::CreateReg(0, false));
469 // AddrMode4 and AddrMode6 cannot handle any offset.
470 if (AddrMode == ARMII::AddrMode4 || AddrMode == ARMII::AddrMode6)
473 // AddrModeT2_so cannot handle any offset. If there is no offset
474 // register then we change to an immediate version.
475 unsigned NewOpc = Opcode;
476 if (AddrMode == ARMII::AddrModeT2_so) {
477 unsigned OffsetReg = MI.getOperand(FrameRegIdx+1).getReg();
478 if (OffsetReg != 0) {
479 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
483 MI.RemoveOperand(FrameRegIdx+1);
484 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(0);
485 NewOpc = immediateOffsetOpcode(Opcode);
486 AddrMode = ARMII::AddrModeT2_i12;
489 unsigned NumBits = 0;
491 if (AddrMode == ARMII::AddrModeT2_i8 || AddrMode == ARMII::AddrModeT2_i12) {
492 // i8 supports only negative, and i12 supports only positive, so
493 // based on Offset sign convert Opcode to the appropriate
495 Offset += MI.getOperand(FrameRegIdx+1).getImm();
497 NewOpc = negativeOffsetOpcode(Opcode);
502 NewOpc = positiveOffsetOpcode(Opcode);
505 } else if (AddrMode == ARMII::AddrMode5) {
507 const MachineOperand &OffOp = MI.getOperand(FrameRegIdx+1);
508 int InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm());
509 if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM::sub)
513 Offset += InstrOffs * 4;
514 assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
520 llvm_unreachable("Unsupported addressing mode!");
523 if (NewOpc != Opcode)
524 MI.setDesc(TII.get(NewOpc));
526 MachineOperand &ImmOp = MI.getOperand(FrameRegIdx+1);
528 // Attempt to fold address computation
529 // Common case: small offset, fits into instruction.
530 int ImmedOffset = Offset / Scale;
531 unsigned Mask = (1 << NumBits) - 1;
532 if ((unsigned)Offset <= Mask * Scale) {
533 // Replace the FrameIndex with fp/sp
534 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
536 if (AddrMode == ARMII::AddrMode5)
537 // FIXME: Not consistent.
538 ImmedOffset |= 1 << NumBits;
540 ImmedOffset = -ImmedOffset;
542 ImmOp.ChangeToImmediate(ImmedOffset);
547 // Otherwise, offset doesn't fit. Pull in what we can to simplify
548 ImmedOffset = ImmedOffset & Mask;
550 if (AddrMode == ARMII::AddrMode5)
551 // FIXME: Not consistent.
552 ImmedOffset |= 1 << NumBits;
554 ImmedOffset = -ImmedOffset;
555 if (ImmedOffset == 0)
556 // Change the opcode back if the encoded offset is zero.
557 MI.setDesc(TII.get(positiveOffsetOpcode(NewOpc)));
560 ImmOp.ChangeToImmediate(ImmedOffset);
561 Offset &= ~(Mask*Scale);
564 Offset = (isSub) ? -Offset : Offset;
568 /// scheduleTwoAddrSource - Schedule the copy / re-mat of the source of the
569 /// two-addrss instruction inserted by two-address pass.
571 Thumb2InstrInfo::scheduleTwoAddrSource(MachineInstr *SrcMI,
573 const TargetRegisterInfo &TRI) const {
574 if (SrcMI->getOpcode() != ARM::tMOVgpr2gpr ||
575 SrcMI->getOperand(1).isKill())
578 unsigned PredReg = 0;
579 ARMCC::CondCodes CC = llvm::getInstrPredicate(UseMI, PredReg);
580 if (CC == ARMCC::AL || PredReg != ARM::CPSR)
583 // Schedule the copy so it doesn't come between previous instructions
584 // and UseMI which can form an IT block.
585 unsigned SrcReg = SrcMI->getOperand(1).getReg();
586 ARMCC::CondCodes OCC = ARMCC::getOppositeCondition(CC);
587 MachineBasicBlock *MBB = UseMI->getParent();
588 MachineBasicBlock::iterator MBBI = SrcMI;
589 unsigned NumInsts = 0;
590 while (--MBBI != MBB->begin()) {
591 if (MBBI->isDebugValue())
594 MachineInstr *NMI = &*MBBI;
595 ARMCC::CondCodes NCC = llvm::getInstrPredicate(NMI, PredReg);
596 if (!(NCC == CC || NCC == OCC) ||
597 NMI->modifiesRegister(SrcReg, &TRI) ||
598 NMI->definesRegister(ARM::CPSR))
601 // Too many in a row!
607 MBB->insert(++MBBI, SrcMI);
612 llvm::getITInstrPredicate(const MachineInstr *MI, unsigned &PredReg) {
613 unsigned Opc = MI->getOpcode();
614 if (Opc == ARM::tBcc || Opc == ARM::t2Bcc)
616 return llvm::getInstrPredicate(MI, PredReg);