1 //===- Thumb2InstrInfo.cpp - Thumb-2 Instruction Information --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Thumb-2 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "ARMInstrInfo.h"
16 #include "ARMAddressingModes.h"
17 #include "ARMGenInstrInfo.inc"
18 #include "ARMMachineFunctionInfo.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/ADT/SmallVector.h"
22 #include "Thumb2InstrInfo.h"
26 Thumb2InstrInfo::Thumb2InstrInfo(const ARMSubtarget &STI) : RI(*this, STI) {
29 unsigned Thumb2InstrInfo::getUnindexedOpcode(unsigned Opc) const {
35 Thumb2InstrInfo::BlockHasNoFallThrough(const MachineBasicBlock &MBB) const {
36 if (MBB.empty()) return false;
38 switch (MBB.back().getOpcode()) {
40 case ARM::t2B: // Uncond branch.
41 case ARM::t2BR_JT: // Jumptable branch.
42 case ARM::t2TBB: // Table branch byte.
43 case ARM::t2TBH: // Table branch halfword.
44 case ARM::tBR_JTr: // Jumptable branch (16-bit version).
46 case ARM::tBX_RET_vararg:
59 Thumb2InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
60 MachineBasicBlock::iterator I,
61 unsigned DestReg, unsigned SrcReg,
62 const TargetRegisterClass *DestRC,
63 const TargetRegisterClass *SrcRC) const {
64 DebugLoc DL = DebugLoc::getUnknownLoc();
65 if (I != MBB.end()) DL = I->getDebugLoc();
67 if (DestRC == ARM::GPRRegisterClass &&
68 SrcRC == ARM::GPRRegisterClass) {
69 BuildMI(MBB, I, DL, get(ARM::tMOVgpr2gpr), DestReg).addReg(SrcReg);
71 } else if (DestRC == ARM::GPRRegisterClass &&
72 SrcRC == ARM::tGPRRegisterClass) {
73 BuildMI(MBB, I, DL, get(ARM::tMOVtgpr2gpr), DestReg).addReg(SrcReg);
75 } else if (DestRC == ARM::tGPRRegisterClass &&
76 SrcRC == ARM::GPRRegisterClass) {
77 BuildMI(MBB, I, DL, get(ARM::tMOVgpr2tgpr), DestReg).addReg(SrcReg);
81 // Handle SPR, DPR, and QPR copies.
82 return ARMBaseInstrInfo::copyRegToReg(MBB, I, DestReg, SrcReg, DestRC, SrcRC);
85 void Thumb2InstrInfo::
86 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
87 unsigned SrcReg, bool isKill, int FI,
88 const TargetRegisterClass *RC) const {
89 DebugLoc DL = DebugLoc::getUnknownLoc();
90 if (I != MBB.end()) DL = I->getDebugLoc();
92 if (RC == ARM::GPRRegisterClass) {
93 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::t2STRi12))
94 .addReg(SrcReg, getKillRegState(isKill))
95 .addFrameIndex(FI).addImm(0));
99 ARMBaseInstrInfo::storeRegToStackSlot(MBB, I, SrcReg, isKill, FI, RC);
102 void Thumb2InstrInfo::
103 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
104 unsigned DestReg, int FI,
105 const TargetRegisterClass *RC) const {
106 DebugLoc DL = DebugLoc::getUnknownLoc();
107 if (I != MBB.end()) DL = I->getDebugLoc();
109 if (RC == ARM::GPRRegisterClass) {
110 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::t2LDRi12), DestReg)
111 .addFrameIndex(FI).addImm(0));
115 ARMBaseInstrInfo::loadRegFromStackSlot(MBB, I, DestReg, FI, RC);
119 void llvm::emitT2RegPlusImmediate(MachineBasicBlock &MBB,
120 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
121 unsigned DestReg, unsigned BaseReg, int NumBytes,
122 ARMCC::CondCodes Pred, unsigned PredReg,
123 const ARMBaseInstrInfo &TII) {
124 bool isSub = NumBytes < 0;
125 if (isSub) NumBytes = -NumBytes;
127 // If profitable, use a movw or movt to materialize the offset.
128 // FIXME: Use the scavenger to grab a scratch register.
129 if (DestReg != ARM::SP && DestReg != BaseReg &&
131 ARM_AM::getT2SOImmVal(NumBytes) == -1) {
133 if (NumBytes < 65536) {
134 // Use a movw to materialize the 16-bit constant.
135 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi16), DestReg)
137 .addImm((unsigned)Pred).addReg(PredReg).addReg(0);
139 } else if ((NumBytes & 0xffff) == 0) {
140 // Use a movt to materialize the 32-bit constant.
141 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVTi16), DestReg)
143 .addImm(NumBytes >> 16)
144 .addImm((unsigned)Pred).addReg(PredReg).addReg(0);
150 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2SUBrr), DestReg)
151 .addReg(BaseReg, RegState::Kill)
152 .addReg(DestReg, RegState::Kill)
153 .addImm((unsigned)Pred).addReg(PredReg).addReg(0);
155 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2ADDrr), DestReg)
156 .addReg(DestReg, RegState::Kill)
157 .addReg(BaseReg, RegState::Kill)
158 .addImm((unsigned)Pred).addReg(PredReg).addReg(0);
165 unsigned ThisVal = NumBytes;
167 if (DestReg == ARM::SP && BaseReg != ARM::SP) {
168 // mov sp, rn. Note t2MOVr cannot be used.
169 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr),DestReg).addReg(BaseReg);
174 if (BaseReg == ARM::SP) {
176 if (DestReg == ARM::SP && (ThisVal < ((1 << 7)-1) * 4)) {
177 assert((ThisVal & 3) == 0 && "Stack update is not multiple of 4?");
178 Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
179 // FIXME: Fix Thumb1 immediate encoding.
180 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
181 .addReg(BaseReg).addImm(ThisVal/4);
186 // sub rd, sp, so_imm
187 Opc = isSub ? ARM::t2SUBrSPi : ARM::t2ADDrSPi;
188 if (ARM_AM::getT2SOImmVal(NumBytes) != -1) {
191 // FIXME: Move this to ARMAddressingModes.h?
192 unsigned RotAmt = CountLeadingZeros_32(ThisVal);
193 ThisVal = ThisVal & ARM_AM::rotr32(0xff000000U, RotAmt);
194 NumBytes &= ~ThisVal;
195 assert(ARM_AM::getT2SOImmVal(ThisVal) != -1 &&
196 "Bit extraction didn't work?");
199 assert(DestReg != ARM::SP && BaseReg != ARM::SP);
200 Opc = isSub ? ARM::t2SUBri : ARM::t2ADDri;
201 if (ARM_AM::getT2SOImmVal(NumBytes) != -1) {
203 } else if (ThisVal < 4096) {
204 Opc = isSub ? ARM::t2SUBri12 : ARM::t2ADDri12;
207 // FIXME: Move this to ARMAddressingModes.h?
208 unsigned RotAmt = CountLeadingZeros_32(ThisVal);
209 ThisVal = ThisVal & ARM_AM::rotr32(0xff000000U, RotAmt);
210 NumBytes &= ~ThisVal;
211 assert(ARM_AM::getT2SOImmVal(ThisVal) != -1 &&
212 "Bit extraction didn't work?");
216 // Build the new ADD / SUB.
217 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
218 .addReg(BaseReg, RegState::Kill)
226 negativeOffsetOpcode(unsigned opcode)
229 case ARM::t2LDRi12: return ARM::t2LDRi8;
230 case ARM::t2LDRHi12: return ARM::t2LDRHi8;
231 case ARM::t2LDRBi12: return ARM::t2LDRBi8;
232 case ARM::t2LDRSHi12: return ARM::t2LDRSHi8;
233 case ARM::t2LDRSBi12: return ARM::t2LDRSBi8;
234 case ARM::t2STRi12: return ARM::t2STRi8;
235 case ARM::t2STRBi12: return ARM::t2STRBi8;
236 case ARM::t2STRHi12: return ARM::t2STRHi8;
256 positiveOffsetOpcode(unsigned opcode)
259 case ARM::t2LDRi8: return ARM::t2LDRi12;
260 case ARM::t2LDRHi8: return ARM::t2LDRHi12;
261 case ARM::t2LDRBi8: return ARM::t2LDRBi12;
262 case ARM::t2LDRSHi8: return ARM::t2LDRSHi12;
263 case ARM::t2LDRSBi8: return ARM::t2LDRSBi12;
264 case ARM::t2STRi8: return ARM::t2STRi12;
265 case ARM::t2STRBi8: return ARM::t2STRBi12;
266 case ARM::t2STRHi8: return ARM::t2STRHi12;
271 case ARM::t2LDRSHi12:
272 case ARM::t2LDRSBi12:
286 immediateOffsetOpcode(unsigned opcode)
289 case ARM::t2LDRs: return ARM::t2LDRi12;
290 case ARM::t2LDRHs: return ARM::t2LDRHi12;
291 case ARM::t2LDRBs: return ARM::t2LDRBi12;
292 case ARM::t2LDRSHs: return ARM::t2LDRSHi12;
293 case ARM::t2LDRSBs: return ARM::t2LDRSBi12;
294 case ARM::t2STRs: return ARM::t2STRi12;
295 case ARM::t2STRBs: return ARM::t2STRBi12;
296 case ARM::t2STRHs: return ARM::t2STRHi12;
301 case ARM::t2LDRSHi12:
302 case ARM::t2LDRSBi12:
323 bool llvm::rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
324 unsigned FrameReg, int &Offset,
325 const ARMBaseInstrInfo &TII) {
326 unsigned Opcode = MI.getOpcode();
327 const TargetInstrDesc &Desc = MI.getDesc();
328 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
331 // Memory operands in inline assembly always use AddrModeT2_i12.
332 if (Opcode == ARM::INLINEASM)
333 AddrMode = ARMII::AddrModeT2_i12; // FIXME. mode for thumb2?
335 if (Opcode == ARM::t2ADDri || Opcode == ARM::t2ADDri12) {
336 Offset += MI.getOperand(FrameRegIdx+1).getImm();
338 bool isSP = FrameReg == ARM::SP;
340 // Turn it into a move.
341 MI.setDesc(TII.get(ARM::tMOVgpr2gpr));
342 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
343 MI.RemoveOperand(FrameRegIdx+1);
351 MI.setDesc(TII.get(isSP ? ARM::t2SUBrSPi : ARM::t2SUBri));
353 MI.setDesc(TII.get(isSP ? ARM::t2ADDrSPi : ARM::t2ADDri));
356 // Common case: small offset, fits into instruction.
357 if (ARM_AM::getT2SOImmVal(Offset) != -1) {
358 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
359 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
363 // Another common case: imm12.
365 unsigned NewOpc = isSP
366 ? (isSub ? ARM::t2SUBrSPi12 : ARM::t2ADDrSPi12)
367 : (isSub ? ARM::t2SUBri12 : ARM::t2ADDri12);
368 MI.setDesc(TII.get(NewOpc));
369 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
370 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
375 // Otherwise, extract 8 adjacent bits from the immediate into this
377 unsigned RotAmt = CountLeadingZeros_32(Offset);
378 unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xff000000U, RotAmt);
380 // We will handle these bits from offset, clear them.
381 Offset &= ~ThisImmVal;
383 assert(ARM_AM::getT2SOImmVal(ThisImmVal) != -1 &&
384 "Bit extraction didn't work?");
385 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal);
388 // AddrMode4 cannot handle any offset.
389 if (AddrMode == ARMII::AddrMode4)
392 // AddrModeT2_so cannot handle any offset. If there is no offset
393 // register then we change to an immediate version.
394 unsigned NewOpc = Opcode;
395 if (AddrMode == ARMII::AddrModeT2_so) {
396 unsigned OffsetReg = MI.getOperand(FrameRegIdx+1).getReg();
397 if (OffsetReg != 0) {
398 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
402 MI.RemoveOperand(FrameRegIdx+1);
403 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(0);
404 NewOpc = immediateOffsetOpcode(Opcode);
405 AddrMode = ARMII::AddrModeT2_i12;
408 unsigned NumBits = 0;
410 if (AddrMode == ARMII::AddrModeT2_i8 || AddrMode == ARMII::AddrModeT2_i12) {
411 // i8 supports only negative, and i12 supports only positive, so
412 // based on Offset sign convert Opcode to the appropriate
414 Offset += MI.getOperand(FrameRegIdx+1).getImm();
416 NewOpc = negativeOffsetOpcode(Opcode);
421 NewOpc = positiveOffsetOpcode(Opcode);
425 // VFP and NEON address modes.
427 if (AddrMode == ARMII::AddrMode5) {
428 const MachineOperand &OffOp = MI.getOperand(FrameRegIdx+1);
429 InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm());
430 if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM::sub)
435 Offset += InstrOffs * 4;
436 assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
443 if (NewOpc != Opcode)
444 MI.setDesc(TII.get(NewOpc));
446 MachineOperand &ImmOp = MI.getOperand(FrameRegIdx+1);
448 // Attempt to fold address computation
449 // Common case: small offset, fits into instruction.
450 int ImmedOffset = Offset / Scale;
451 unsigned Mask = (1 << NumBits) - 1;
452 if ((unsigned)Offset <= Mask * Scale) {
453 // Replace the FrameIndex with fp/sp
454 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
456 if (AddrMode == ARMII::AddrMode5)
457 // FIXME: Not consistent.
458 ImmedOffset |= 1 << NumBits;
460 ImmedOffset = -ImmedOffset;
462 ImmOp.ChangeToImmediate(ImmedOffset);
467 // Otherwise, offset doesn't fit. Pull in what we can to simplify
468 ImmedOffset = ImmedOffset & Mask;
470 if (AddrMode == ARMII::AddrMode5)
471 // FIXME: Not consistent.
472 ImmedOffset |= 1 << NumBits;
474 ImmedOffset = -ImmedOffset;
475 if (ImmedOffset == 0)
476 // Change the opcode back if the encoded offset is zero.
477 MI.setDesc(TII.get(positiveOffsetOpcode(NewOpc)));
480 ImmOp.ChangeToImmediate(ImmedOffset);
481 Offset &= ~(Mask*Scale);
484 Offset = (isSub) ? -Offset : Offset;