1 //===- Thumb2InstrInfo.cpp - Thumb-2 Instruction Information ----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Thumb-2 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "Thumb2InstrInfo.h"
16 #include "ARMConstantPoolValue.h"
17 #include "ARMMachineFunctionInfo.h"
18 #include "Thumb2InstrInfo.h"
19 #include "MCTargetDesc/ARMAddressingModes.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineMemOperand.h"
23 #include "llvm/ADT/SmallVector.h"
24 #include "llvm/Support/CommandLine.h"
29 OldT2IfCvt("old-thumb2-ifcvt", cl::Hidden,
30 cl::desc("Use old-style Thumb2 if-conversion heuristics"),
33 Thumb2InstrInfo::Thumb2InstrInfo(const ARMSubtarget &STI)
34 : ARMBaseInstrInfo(STI), RI(*this, STI) {
37 unsigned Thumb2InstrInfo::getUnindexedOpcode(unsigned Opc) const {
43 Thumb2InstrInfo::ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail,
44 MachineBasicBlock *NewDest) const {
45 MachineBasicBlock *MBB = Tail->getParent();
46 ARMFunctionInfo *AFI = MBB->getParent()->getInfo<ARMFunctionInfo>();
47 if (!AFI->hasITBlocks()) {
48 TargetInstrInfoImpl::ReplaceTailWithBranchTo(Tail, NewDest);
52 // If the first instruction of Tail is predicated, we may have to update
53 // the IT instruction.
55 ARMCC::CondCodes CC = llvm::getInstrPredicate(Tail, PredReg);
56 MachineBasicBlock::iterator MBBI = Tail;
58 // Expecting at least the t2IT instruction before it.
61 // Actually replace the tail.
62 TargetInstrInfoImpl::ReplaceTailWithBranchTo(Tail, NewDest);
65 if (CC != ARMCC::AL) {
66 MachineBasicBlock::iterator E = MBB->begin();
67 unsigned Count = 4; // At most 4 instructions in an IT block.
68 while (Count && MBBI != E) {
69 if (MBBI->isDebugValue()) {
73 if (MBBI->getOpcode() == ARM::t2IT) {
74 unsigned Mask = MBBI->getOperand(1).getImm();
76 MBBI->eraseFromParent();
78 unsigned MaskOn = 1 << Count;
79 unsigned MaskOff = ~(MaskOn - 1);
80 MBBI->getOperand(1).setImm((Mask & MaskOff) | MaskOn);
88 // Ctrl flow can reach here if branch folding is run before IT block
94 Thumb2InstrInfo::isLegalToSplitMBBAt(MachineBasicBlock &MBB,
95 MachineBasicBlock::iterator MBBI) const {
96 while (MBBI->isDebugValue()) {
98 if (MBBI == MBB.end())
102 unsigned PredReg = 0;
103 return llvm::getITInstrPredicate(MBBI, PredReg) == ARMCC::AL;
106 void Thumb2InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
107 MachineBasicBlock::iterator I, DebugLoc DL,
108 unsigned DestReg, unsigned SrcReg,
109 bool KillSrc) const {
110 // Handle SPR, DPR, and QPR copies.
111 if (!ARM::GPRRegClass.contains(DestReg, SrcReg))
112 return ARMBaseInstrInfo::copyPhysReg(MBB, I, DL, DestReg, SrcReg, KillSrc);
114 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg)
115 .addReg(SrcReg, getKillRegState(KillSrc)));
118 void Thumb2InstrInfo::
119 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
120 unsigned SrcReg, bool isKill, int FI,
121 const TargetRegisterClass *RC,
122 const TargetRegisterInfo *TRI) const {
123 if (RC == ARM::GPRRegisterClass || RC == ARM::tGPRRegisterClass ||
124 RC == ARM::tcGPRRegisterClass || RC == ARM::rGPRRegisterClass ||
125 RC == ARM::GPRnopcRegisterClass) {
127 if (I != MBB.end()) DL = I->getDebugLoc();
129 MachineFunction &MF = *MBB.getParent();
130 MachineFrameInfo &MFI = *MF.getFrameInfo();
131 MachineMemOperand *MMO =
132 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
133 MachineMemOperand::MOStore,
134 MFI.getObjectSize(FI),
135 MFI.getObjectAlignment(FI));
136 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::t2STRi12))
137 .addReg(SrcReg, getKillRegState(isKill))
138 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
142 ARMBaseInstrInfo::storeRegToStackSlot(MBB, I, SrcReg, isKill, FI, RC, TRI);
145 void Thumb2InstrInfo::
146 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
147 unsigned DestReg, int FI,
148 const TargetRegisterClass *RC,
149 const TargetRegisterInfo *TRI) const {
150 if (RC == ARM::GPRRegisterClass || RC == ARM::tGPRRegisterClass ||
151 RC == ARM::tcGPRRegisterClass || RC == ARM::rGPRRegisterClass ||
152 RC == ARM::GPRnopcRegisterClass) {
154 if (I != MBB.end()) DL = I->getDebugLoc();
156 MachineFunction &MF = *MBB.getParent();
157 MachineFrameInfo &MFI = *MF.getFrameInfo();
158 MachineMemOperand *MMO =
159 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
160 MachineMemOperand::MOLoad,
161 MFI.getObjectSize(FI),
162 MFI.getObjectAlignment(FI));
163 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::t2LDRi12), DestReg)
164 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
168 ARMBaseInstrInfo::loadRegFromStackSlot(MBB, I, DestReg, FI, RC, TRI);
171 void llvm::emitT2RegPlusImmediate(MachineBasicBlock &MBB,
172 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
173 unsigned DestReg, unsigned BaseReg, int NumBytes,
174 ARMCC::CondCodes Pred, unsigned PredReg,
175 const ARMBaseInstrInfo &TII, unsigned MIFlags) {
176 bool isSub = NumBytes < 0;
177 if (isSub) NumBytes = -NumBytes;
179 // If profitable, use a movw or movt to materialize the offset.
180 // FIXME: Use the scavenger to grab a scratch register.
181 if (DestReg != ARM::SP && DestReg != BaseReg &&
183 ARM_AM::getT2SOImmVal(NumBytes) == -1) {
185 if (NumBytes < 65536) {
186 // Use a movw to materialize the 16-bit constant.
187 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi16), DestReg)
189 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags);
191 } else if ((NumBytes & 0xffff) == 0) {
192 // Use a movt to materialize the 32-bit constant.
193 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVTi16), DestReg)
195 .addImm(NumBytes >> 16)
196 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags);
202 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2SUBrr), DestReg)
203 .addReg(BaseReg, RegState::Kill)
204 .addReg(DestReg, RegState::Kill)
205 .addImm((unsigned)Pred).addReg(PredReg).addReg(0)
206 .setMIFlags(MIFlags);
208 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2ADDrr), DestReg)
209 .addReg(DestReg, RegState::Kill)
210 .addReg(BaseReg, RegState::Kill)
211 .addImm((unsigned)Pred).addReg(PredReg).addReg(0)
212 .setMIFlags(MIFlags);
219 unsigned ThisVal = NumBytes;
221 if (DestReg == ARM::SP && BaseReg != ARM::SP) {
222 // mov sp, rn. Note t2MOVr cannot be used.
223 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),DestReg)
224 .addReg(BaseReg).setMIFlags(MIFlags));
229 bool HasCCOut = true;
230 if (BaseReg == ARM::SP) {
232 if (DestReg == ARM::SP && (ThisVal < ((1 << 7)-1) * 4)) {
233 assert((ThisVal & 3) == 0 && "Stack update is not multiple of 4?");
234 Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
235 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
236 .addReg(BaseReg).addImm(ThisVal/4).setMIFlags(MIFlags));
241 // sub rd, sp, so_imm
242 Opc = isSub ? ARM::t2SUBri : ARM::t2ADDri;
243 if (ARM_AM::getT2SOImmVal(NumBytes) != -1) {
246 // FIXME: Move this to ARMAddressingModes.h?
247 unsigned RotAmt = CountLeadingZeros_32(ThisVal);
248 ThisVal = ThisVal & ARM_AM::rotr32(0xff000000U, RotAmt);
249 NumBytes &= ~ThisVal;
250 assert(ARM_AM::getT2SOImmVal(ThisVal) != -1 &&
251 "Bit extraction didn't work?");
254 assert(DestReg != ARM::SP && BaseReg != ARM::SP);
255 Opc = isSub ? ARM::t2SUBri : ARM::t2ADDri;
256 if (ARM_AM::getT2SOImmVal(NumBytes) != -1) {
258 } else if (ThisVal < 4096) {
259 Opc = isSub ? ARM::t2SUBri12 : ARM::t2ADDri12;
263 // FIXME: Move this to ARMAddressingModes.h?
264 unsigned RotAmt = CountLeadingZeros_32(ThisVal);
265 ThisVal = ThisVal & ARM_AM::rotr32(0xff000000U, RotAmt);
266 NumBytes &= ~ThisVal;
267 assert(ARM_AM::getT2SOImmVal(ThisVal) != -1 &&
268 "Bit extraction didn't work?");
272 // Build the new ADD / SUB.
273 MachineInstrBuilder MIB =
274 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
275 .addReg(BaseReg, RegState::Kill)
276 .addImm(ThisVal)).setMIFlags(MIFlags);
285 negativeOffsetOpcode(unsigned opcode)
288 case ARM::t2LDRi12: return ARM::t2LDRi8;
289 case ARM::t2LDRHi12: return ARM::t2LDRHi8;
290 case ARM::t2LDRBi12: return ARM::t2LDRBi8;
291 case ARM::t2LDRSHi12: return ARM::t2LDRSHi8;
292 case ARM::t2LDRSBi12: return ARM::t2LDRSBi8;
293 case ARM::t2STRi12: return ARM::t2STRi8;
294 case ARM::t2STRBi12: return ARM::t2STRBi8;
295 case ARM::t2STRHi12: return ARM::t2STRHi8;
315 positiveOffsetOpcode(unsigned opcode)
318 case ARM::t2LDRi8: return ARM::t2LDRi12;
319 case ARM::t2LDRHi8: return ARM::t2LDRHi12;
320 case ARM::t2LDRBi8: return ARM::t2LDRBi12;
321 case ARM::t2LDRSHi8: return ARM::t2LDRSHi12;
322 case ARM::t2LDRSBi8: return ARM::t2LDRSBi12;
323 case ARM::t2STRi8: return ARM::t2STRi12;
324 case ARM::t2STRBi8: return ARM::t2STRBi12;
325 case ARM::t2STRHi8: return ARM::t2STRHi12;
330 case ARM::t2LDRSHi12:
331 case ARM::t2LDRSBi12:
345 immediateOffsetOpcode(unsigned opcode)
348 case ARM::t2LDRs: return ARM::t2LDRi12;
349 case ARM::t2LDRHs: return ARM::t2LDRHi12;
350 case ARM::t2LDRBs: return ARM::t2LDRBi12;
351 case ARM::t2LDRSHs: return ARM::t2LDRSHi12;
352 case ARM::t2LDRSBs: return ARM::t2LDRSBi12;
353 case ARM::t2STRs: return ARM::t2STRi12;
354 case ARM::t2STRBs: return ARM::t2STRBi12;
355 case ARM::t2STRHs: return ARM::t2STRHi12;
360 case ARM::t2LDRSHi12:
361 case ARM::t2LDRSBi12:
382 bool llvm::rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
383 unsigned FrameReg, int &Offset,
384 const ARMBaseInstrInfo &TII) {
385 unsigned Opcode = MI.getOpcode();
386 const MCInstrDesc &Desc = MI.getDesc();
387 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
390 // Memory operands in inline assembly always use AddrModeT2_i12.
391 if (Opcode == ARM::INLINEASM)
392 AddrMode = ARMII::AddrModeT2_i12; // FIXME. mode for thumb2?
394 if (Opcode == ARM::t2ADDri || Opcode == ARM::t2ADDri12) {
395 Offset += MI.getOperand(FrameRegIdx+1).getImm();
398 if (Offset == 0 && getInstrPredicate(&MI, PredReg) == ARMCC::AL) {
399 // Turn it into a move.
400 MI.setDesc(TII.get(ARM::tMOVr));
401 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
402 // Remove offset and remaining explicit predicate operands.
403 do MI.RemoveOperand(FrameRegIdx+1);
404 while (MI.getNumOperands() > FrameRegIdx+1);
405 MachineInstrBuilder MIB(&MI);
410 bool HasCCOut = Opcode != ARM::t2ADDri12;
415 MI.setDesc(TII.get(ARM::t2SUBri));
417 MI.setDesc(TII.get(ARM::t2ADDri));
420 // Common case: small offset, fits into instruction.
421 if (ARM_AM::getT2SOImmVal(Offset) != -1) {
422 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
423 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
424 // Add cc_out operand if the original instruction did not have one.
426 MI.addOperand(MachineOperand::CreateReg(0, false));
430 // Another common case: imm12.
432 (!HasCCOut || MI.getOperand(MI.getNumOperands()-1).getReg() == 0)) {
433 unsigned NewOpc = isSub ? ARM::t2SUBri12 : ARM::t2ADDri12;
434 MI.setDesc(TII.get(NewOpc));
435 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
436 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
437 // Remove the cc_out operand.
439 MI.RemoveOperand(MI.getNumOperands()-1);
444 // Otherwise, extract 8 adjacent bits from the immediate into this
446 unsigned RotAmt = CountLeadingZeros_32(Offset);
447 unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xff000000U, RotAmt);
449 // We will handle these bits from offset, clear them.
450 Offset &= ~ThisImmVal;
452 assert(ARM_AM::getT2SOImmVal(ThisImmVal) != -1 &&
453 "Bit extraction didn't work?");
454 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal);
455 // Add cc_out operand if the original instruction did not have one.
457 MI.addOperand(MachineOperand::CreateReg(0, false));
461 // AddrMode4 and AddrMode6 cannot handle any offset.
462 if (AddrMode == ARMII::AddrMode4 || AddrMode == ARMII::AddrMode6)
465 // AddrModeT2_so cannot handle any offset. If there is no offset
466 // register then we change to an immediate version.
467 unsigned NewOpc = Opcode;
468 if (AddrMode == ARMII::AddrModeT2_so) {
469 unsigned OffsetReg = MI.getOperand(FrameRegIdx+1).getReg();
470 if (OffsetReg != 0) {
471 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
475 MI.RemoveOperand(FrameRegIdx+1);
476 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(0);
477 NewOpc = immediateOffsetOpcode(Opcode);
478 AddrMode = ARMII::AddrModeT2_i12;
481 unsigned NumBits = 0;
483 if (AddrMode == ARMII::AddrModeT2_i8 || AddrMode == ARMII::AddrModeT2_i12) {
484 // i8 supports only negative, and i12 supports only positive, so
485 // based on Offset sign convert Opcode to the appropriate
487 Offset += MI.getOperand(FrameRegIdx+1).getImm();
489 NewOpc = negativeOffsetOpcode(Opcode);
494 NewOpc = positiveOffsetOpcode(Opcode);
497 } else if (AddrMode == ARMII::AddrMode5) {
499 const MachineOperand &OffOp = MI.getOperand(FrameRegIdx+1);
500 int InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm());
501 if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM::sub)
505 Offset += InstrOffs * 4;
506 assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
512 llvm_unreachable("Unsupported addressing mode!");
515 if (NewOpc != Opcode)
516 MI.setDesc(TII.get(NewOpc));
518 MachineOperand &ImmOp = MI.getOperand(FrameRegIdx+1);
520 // Attempt to fold address computation
521 // Common case: small offset, fits into instruction.
522 int ImmedOffset = Offset / Scale;
523 unsigned Mask = (1 << NumBits) - 1;
524 if ((unsigned)Offset <= Mask * Scale) {
525 // Replace the FrameIndex with fp/sp
526 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
528 if (AddrMode == ARMII::AddrMode5)
529 // FIXME: Not consistent.
530 ImmedOffset |= 1 << NumBits;
532 ImmedOffset = -ImmedOffset;
534 ImmOp.ChangeToImmediate(ImmedOffset);
539 // Otherwise, offset doesn't fit. Pull in what we can to simplify
540 ImmedOffset = ImmedOffset & Mask;
542 if (AddrMode == ARMII::AddrMode5)
543 // FIXME: Not consistent.
544 ImmedOffset |= 1 << NumBits;
546 ImmedOffset = -ImmedOffset;
547 if (ImmedOffset == 0)
548 // Change the opcode back if the encoded offset is zero.
549 MI.setDesc(TII.get(positiveOffsetOpcode(NewOpc)));
552 ImmOp.ChangeToImmediate(ImmedOffset);
553 Offset &= ~(Mask*Scale);
556 Offset = (isSub) ? -Offset : Offset;
560 /// scheduleTwoAddrSource - Schedule the copy / re-mat of the source of the
561 /// two-addrss instruction inserted by two-address pass.
563 Thumb2InstrInfo::scheduleTwoAddrSource(MachineInstr *SrcMI,
565 const TargetRegisterInfo &TRI) const {
566 if (SrcMI->getOpcode() != ARM::tMOVr || SrcMI->getOperand(1).isKill())
569 unsigned PredReg = 0;
570 ARMCC::CondCodes CC = llvm::getInstrPredicate(UseMI, PredReg);
571 if (CC == ARMCC::AL || PredReg != ARM::CPSR)
574 // Schedule the copy so it doesn't come between previous instructions
575 // and UseMI which can form an IT block.
576 unsigned SrcReg = SrcMI->getOperand(1).getReg();
577 ARMCC::CondCodes OCC = ARMCC::getOppositeCondition(CC);
578 MachineBasicBlock *MBB = UseMI->getParent();
579 MachineBasicBlock::iterator MBBI = SrcMI;
580 unsigned NumInsts = 0;
581 while (--MBBI != MBB->begin()) {
582 if (MBBI->isDebugValue())
585 MachineInstr *NMI = &*MBBI;
586 ARMCC::CondCodes NCC = llvm::getInstrPredicate(NMI, PredReg);
587 if (!(NCC == CC || NCC == OCC) ||
588 NMI->modifiesRegister(SrcReg, &TRI) ||
589 NMI->definesRegister(ARM::CPSR))
592 // Too many in a row!
598 MBB->insert(++MBBI, SrcMI);
603 llvm::getITInstrPredicate(const MachineInstr *MI, unsigned &PredReg) {
604 unsigned Opc = MI->getOpcode();
605 if (Opc == ARM::tBcc || Opc == ARM::t2Bcc)
607 return llvm::getInstrPredicate(MI, PredReg);