1 //===- Thumb2InstrInfo.cpp - Thumb-2 Instruction Information ----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Thumb-2 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "Thumb2InstrInfo.h"
16 #include "ARMConstantPoolValue.h"
17 #include "ARMMachineFunctionInfo.h"
18 #include "Thumb2InstrInfo.h"
19 #include "MCTargetDesc/ARMAddressingModes.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineMemOperand.h"
23 #include "llvm/CodeGen/PseudoSourceValue.h"
24 #include "llvm/ADT/SmallVector.h"
25 #include "llvm/Support/CommandLine.h"
30 OldT2IfCvt("old-thumb2-ifcvt", cl::Hidden,
31 cl::desc("Use old-style Thumb2 if-conversion heuristics"),
34 Thumb2InstrInfo::Thumb2InstrInfo(const ARMSubtarget &STI)
35 : ARMBaseInstrInfo(STI), RI(*this, STI) {
38 unsigned Thumb2InstrInfo::getUnindexedOpcode(unsigned Opc) const {
44 Thumb2InstrInfo::ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail,
45 MachineBasicBlock *NewDest) const {
46 MachineBasicBlock *MBB = Tail->getParent();
47 ARMFunctionInfo *AFI = MBB->getParent()->getInfo<ARMFunctionInfo>();
48 if (!AFI->hasITBlocks()) {
49 TargetInstrInfoImpl::ReplaceTailWithBranchTo(Tail, NewDest);
53 // If the first instruction of Tail is predicated, we may have to update
54 // the IT instruction.
56 ARMCC::CondCodes CC = llvm::getInstrPredicate(Tail, PredReg);
57 MachineBasicBlock::iterator MBBI = Tail;
59 // Expecting at least the t2IT instruction before it.
62 // Actually replace the tail.
63 TargetInstrInfoImpl::ReplaceTailWithBranchTo(Tail, NewDest);
66 if (CC != ARMCC::AL) {
67 MachineBasicBlock::iterator E = MBB->begin();
68 unsigned Count = 4; // At most 4 instructions in an IT block.
69 while (Count && MBBI != E) {
70 if (MBBI->isDebugValue()) {
74 if (MBBI->getOpcode() == ARM::t2IT) {
75 unsigned Mask = MBBI->getOperand(1).getImm();
77 MBBI->eraseFromParent();
79 unsigned MaskOn = 1 << Count;
80 unsigned MaskOff = ~(MaskOn - 1);
81 MBBI->getOperand(1).setImm((Mask & MaskOff) | MaskOn);
89 // Ctrl flow can reach here if branch folding is run before IT block
95 Thumb2InstrInfo::isLegalToSplitMBBAt(MachineBasicBlock &MBB,
96 MachineBasicBlock::iterator MBBI) const {
97 while (MBBI->isDebugValue()) {
99 if (MBBI == MBB.end())
103 unsigned PredReg = 0;
104 return llvm::getITInstrPredicate(MBBI, PredReg) == ARMCC::AL;
107 void Thumb2InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
108 MachineBasicBlock::iterator I, DebugLoc DL,
109 unsigned DestReg, unsigned SrcReg,
110 bool KillSrc) const {
111 // Handle SPR, DPR, and QPR copies.
112 if (!ARM::GPRRegClass.contains(DestReg, SrcReg))
113 return ARMBaseInstrInfo::copyPhysReg(MBB, I, DL, DestReg, SrcReg, KillSrc);
115 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg)
116 .addReg(SrcReg, getKillRegState(KillSrc)));
119 void Thumb2InstrInfo::
120 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
121 unsigned SrcReg, bool isKill, int FI,
122 const TargetRegisterClass *RC,
123 const TargetRegisterInfo *TRI) const {
124 if (RC == ARM::GPRRegisterClass || RC == ARM::tGPRRegisterClass ||
125 RC == ARM::tcGPRRegisterClass || RC == ARM::rGPRRegisterClass ||
126 RC == ARM::GPRnopcRegisterClass) {
128 if (I != MBB.end()) DL = I->getDebugLoc();
130 MachineFunction &MF = *MBB.getParent();
131 MachineFrameInfo &MFI = *MF.getFrameInfo();
132 MachineMemOperand *MMO =
133 MF.getMachineMemOperand(
134 MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)),
135 MachineMemOperand::MOStore,
136 MFI.getObjectSize(FI),
137 MFI.getObjectAlignment(FI));
138 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::t2STRi12))
139 .addReg(SrcReg, getKillRegState(isKill))
140 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
144 ARMBaseInstrInfo::storeRegToStackSlot(MBB, I, SrcReg, isKill, FI, RC, TRI);
147 void Thumb2InstrInfo::
148 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
149 unsigned DestReg, int FI,
150 const TargetRegisterClass *RC,
151 const TargetRegisterInfo *TRI) const {
152 if (RC == ARM::GPRRegisterClass || RC == ARM::tGPRRegisterClass ||
153 RC == ARM::tcGPRRegisterClass || RC == ARM::rGPRRegisterClass ||
154 RC == ARM::GPRnopcRegisterClass) {
156 if (I != MBB.end()) DL = I->getDebugLoc();
158 MachineFunction &MF = *MBB.getParent();
159 MachineFrameInfo &MFI = *MF.getFrameInfo();
160 MachineMemOperand *MMO =
161 MF.getMachineMemOperand(
162 MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)),
163 MachineMemOperand::MOLoad,
164 MFI.getObjectSize(FI),
165 MFI.getObjectAlignment(FI));
166 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::t2LDRi12), DestReg)
167 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
171 ARMBaseInstrInfo::loadRegFromStackSlot(MBB, I, DestReg, FI, RC, TRI);
174 void llvm::emitT2RegPlusImmediate(MachineBasicBlock &MBB,
175 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
176 unsigned DestReg, unsigned BaseReg, int NumBytes,
177 ARMCC::CondCodes Pred, unsigned PredReg,
178 const ARMBaseInstrInfo &TII, unsigned MIFlags) {
179 bool isSub = NumBytes < 0;
180 if (isSub) NumBytes = -NumBytes;
182 // If profitable, use a movw or movt to materialize the offset.
183 // FIXME: Use the scavenger to grab a scratch register.
184 if (DestReg != ARM::SP && DestReg != BaseReg &&
186 ARM_AM::getT2SOImmVal(NumBytes) == -1) {
188 if (NumBytes < 65536) {
189 // Use a movw to materialize the 16-bit constant.
190 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi16), DestReg)
192 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags);
194 } else if ((NumBytes & 0xffff) == 0) {
195 // Use a movt to materialize the 32-bit constant.
196 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVTi16), DestReg)
198 .addImm(NumBytes >> 16)
199 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags);
205 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2SUBrr), DestReg)
206 .addReg(BaseReg, RegState::Kill)
207 .addReg(DestReg, RegState::Kill)
208 .addImm((unsigned)Pred).addReg(PredReg).addReg(0)
209 .setMIFlags(MIFlags);
211 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2ADDrr), DestReg)
212 .addReg(DestReg, RegState::Kill)
213 .addReg(BaseReg, RegState::Kill)
214 .addImm((unsigned)Pred).addReg(PredReg).addReg(0)
215 .setMIFlags(MIFlags);
222 unsigned ThisVal = NumBytes;
224 if (DestReg == ARM::SP && BaseReg != ARM::SP) {
225 // mov sp, rn. Note t2MOVr cannot be used.
226 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),DestReg)
227 .addReg(BaseReg).setMIFlags(MIFlags));
232 bool HasCCOut = true;
233 if (BaseReg == ARM::SP) {
235 if (DestReg == ARM::SP && (ThisVal < ((1 << 7)-1) * 4)) {
236 assert((ThisVal & 3) == 0 && "Stack update is not multiple of 4?");
237 Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
238 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
239 .addReg(BaseReg).addImm(ThisVal/4).setMIFlags(MIFlags));
244 // sub rd, sp, so_imm
245 Opc = isSub ? ARM::t2SUBri : ARM::t2ADDri;
246 if (ARM_AM::getT2SOImmVal(NumBytes) != -1) {
249 // FIXME: Move this to ARMAddressingModes.h?
250 unsigned RotAmt = CountLeadingZeros_32(ThisVal);
251 ThisVal = ThisVal & ARM_AM::rotr32(0xff000000U, RotAmt);
252 NumBytes &= ~ThisVal;
253 assert(ARM_AM::getT2SOImmVal(ThisVal) != -1 &&
254 "Bit extraction didn't work?");
257 assert(DestReg != ARM::SP && BaseReg != ARM::SP);
258 Opc = isSub ? ARM::t2SUBri : ARM::t2ADDri;
259 if (ARM_AM::getT2SOImmVal(NumBytes) != -1) {
261 } else if (ThisVal < 4096) {
262 Opc = isSub ? ARM::t2SUBri12 : ARM::t2ADDri12;
266 // FIXME: Move this to ARMAddressingModes.h?
267 unsigned RotAmt = CountLeadingZeros_32(ThisVal);
268 ThisVal = ThisVal & ARM_AM::rotr32(0xff000000U, RotAmt);
269 NumBytes &= ~ThisVal;
270 assert(ARM_AM::getT2SOImmVal(ThisVal) != -1 &&
271 "Bit extraction didn't work?");
275 // Build the new ADD / SUB.
276 MachineInstrBuilder MIB =
277 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
278 .addReg(BaseReg, RegState::Kill)
279 .addImm(ThisVal)).setMIFlags(MIFlags);
288 negativeOffsetOpcode(unsigned opcode)
291 case ARM::t2LDRi12: return ARM::t2LDRi8;
292 case ARM::t2LDRHi12: return ARM::t2LDRHi8;
293 case ARM::t2LDRBi12: return ARM::t2LDRBi8;
294 case ARM::t2LDRSHi12: return ARM::t2LDRSHi8;
295 case ARM::t2LDRSBi12: return ARM::t2LDRSBi8;
296 case ARM::t2STRi12: return ARM::t2STRi8;
297 case ARM::t2STRBi12: return ARM::t2STRBi8;
298 case ARM::t2STRHi12: return ARM::t2STRHi8;
318 positiveOffsetOpcode(unsigned opcode)
321 case ARM::t2LDRi8: return ARM::t2LDRi12;
322 case ARM::t2LDRHi8: return ARM::t2LDRHi12;
323 case ARM::t2LDRBi8: return ARM::t2LDRBi12;
324 case ARM::t2LDRSHi8: return ARM::t2LDRSHi12;
325 case ARM::t2LDRSBi8: return ARM::t2LDRSBi12;
326 case ARM::t2STRi8: return ARM::t2STRi12;
327 case ARM::t2STRBi8: return ARM::t2STRBi12;
328 case ARM::t2STRHi8: return ARM::t2STRHi12;
333 case ARM::t2LDRSHi12:
334 case ARM::t2LDRSBi12:
348 immediateOffsetOpcode(unsigned opcode)
351 case ARM::t2LDRs: return ARM::t2LDRi12;
352 case ARM::t2LDRHs: return ARM::t2LDRHi12;
353 case ARM::t2LDRBs: return ARM::t2LDRBi12;
354 case ARM::t2LDRSHs: return ARM::t2LDRSHi12;
355 case ARM::t2LDRSBs: return ARM::t2LDRSBi12;
356 case ARM::t2STRs: return ARM::t2STRi12;
357 case ARM::t2STRBs: return ARM::t2STRBi12;
358 case ARM::t2STRHs: return ARM::t2STRHi12;
363 case ARM::t2LDRSHi12:
364 case ARM::t2LDRSBi12:
385 bool llvm::rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
386 unsigned FrameReg, int &Offset,
387 const ARMBaseInstrInfo &TII) {
388 unsigned Opcode = MI.getOpcode();
389 const MCInstrDesc &Desc = MI.getDesc();
390 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
393 // Memory operands in inline assembly always use AddrModeT2_i12.
394 if (Opcode == ARM::INLINEASM)
395 AddrMode = ARMII::AddrModeT2_i12; // FIXME. mode for thumb2?
397 if (Opcode == ARM::t2ADDri || Opcode == ARM::t2ADDri12) {
398 Offset += MI.getOperand(FrameRegIdx+1).getImm();
401 if (Offset == 0 && getInstrPredicate(&MI, PredReg) == ARMCC::AL) {
402 // Turn it into a move.
403 MI.setDesc(TII.get(ARM::tMOVr));
404 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
405 // Remove offset and remaining explicit predicate operands.
406 do MI.RemoveOperand(FrameRegIdx+1);
407 while (MI.getNumOperands() > FrameRegIdx+1);
408 MachineInstrBuilder MIB(&MI);
413 bool HasCCOut = Opcode != ARM::t2ADDri12;
418 MI.setDesc(TII.get(ARM::t2SUBri));
420 MI.setDesc(TII.get(ARM::t2ADDri));
423 // Common case: small offset, fits into instruction.
424 if (ARM_AM::getT2SOImmVal(Offset) != -1) {
425 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
426 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
427 // Add cc_out operand if the original instruction did not have one.
429 MI.addOperand(MachineOperand::CreateReg(0, false));
433 // Another common case: imm12.
435 (!HasCCOut || MI.getOperand(MI.getNumOperands()-1).getReg() == 0)) {
436 unsigned NewOpc = isSub ? ARM::t2SUBri12 : ARM::t2ADDri12;
437 MI.setDesc(TII.get(NewOpc));
438 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
439 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
440 // Remove the cc_out operand.
442 MI.RemoveOperand(MI.getNumOperands()-1);
447 // Otherwise, extract 8 adjacent bits from the immediate into this
449 unsigned RotAmt = CountLeadingZeros_32(Offset);
450 unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xff000000U, RotAmt);
452 // We will handle these bits from offset, clear them.
453 Offset &= ~ThisImmVal;
455 assert(ARM_AM::getT2SOImmVal(ThisImmVal) != -1 &&
456 "Bit extraction didn't work?");
457 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal);
458 // Add cc_out operand if the original instruction did not have one.
460 MI.addOperand(MachineOperand::CreateReg(0, false));
464 // AddrMode4 and AddrMode6 cannot handle any offset.
465 if (AddrMode == ARMII::AddrMode4 || AddrMode == ARMII::AddrMode6)
468 // AddrModeT2_so cannot handle any offset. If there is no offset
469 // register then we change to an immediate version.
470 unsigned NewOpc = Opcode;
471 if (AddrMode == ARMII::AddrModeT2_so) {
472 unsigned OffsetReg = MI.getOperand(FrameRegIdx+1).getReg();
473 if (OffsetReg != 0) {
474 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
478 MI.RemoveOperand(FrameRegIdx+1);
479 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(0);
480 NewOpc = immediateOffsetOpcode(Opcode);
481 AddrMode = ARMII::AddrModeT2_i12;
484 unsigned NumBits = 0;
486 if (AddrMode == ARMII::AddrModeT2_i8 || AddrMode == ARMII::AddrModeT2_i12) {
487 // i8 supports only negative, and i12 supports only positive, so
488 // based on Offset sign convert Opcode to the appropriate
490 Offset += MI.getOperand(FrameRegIdx+1).getImm();
492 NewOpc = negativeOffsetOpcode(Opcode);
497 NewOpc = positiveOffsetOpcode(Opcode);
500 } else if (AddrMode == ARMII::AddrMode5) {
502 const MachineOperand &OffOp = MI.getOperand(FrameRegIdx+1);
503 int InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm());
504 if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM::sub)
508 Offset += InstrOffs * 4;
509 assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
515 llvm_unreachable("Unsupported addressing mode!");
518 if (NewOpc != Opcode)
519 MI.setDesc(TII.get(NewOpc));
521 MachineOperand &ImmOp = MI.getOperand(FrameRegIdx+1);
523 // Attempt to fold address computation
524 // Common case: small offset, fits into instruction.
525 int ImmedOffset = Offset / Scale;
526 unsigned Mask = (1 << NumBits) - 1;
527 if ((unsigned)Offset <= Mask * Scale) {
528 // Replace the FrameIndex with fp/sp
529 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
531 if (AddrMode == ARMII::AddrMode5)
532 // FIXME: Not consistent.
533 ImmedOffset |= 1 << NumBits;
535 ImmedOffset = -ImmedOffset;
537 ImmOp.ChangeToImmediate(ImmedOffset);
542 // Otherwise, offset doesn't fit. Pull in what we can to simplify
543 ImmedOffset = ImmedOffset & Mask;
545 if (AddrMode == ARMII::AddrMode5)
546 // FIXME: Not consistent.
547 ImmedOffset |= 1 << NumBits;
549 ImmedOffset = -ImmedOffset;
550 if (ImmedOffset == 0)
551 // Change the opcode back if the encoded offset is zero.
552 MI.setDesc(TII.get(positiveOffsetOpcode(NewOpc)));
555 ImmOp.ChangeToImmediate(ImmedOffset);
556 Offset &= ~(Mask*Scale);
559 Offset = (isSub) ? -Offset : Offset;
563 /// scheduleTwoAddrSource - Schedule the copy / re-mat of the source of the
564 /// two-addrss instruction inserted by two-address pass.
566 Thumb2InstrInfo::scheduleTwoAddrSource(MachineInstr *SrcMI,
568 const TargetRegisterInfo &TRI) const {
569 if (SrcMI->getOpcode() != ARM::tMOVr || SrcMI->getOperand(1).isKill())
572 unsigned PredReg = 0;
573 ARMCC::CondCodes CC = llvm::getInstrPredicate(UseMI, PredReg);
574 if (CC == ARMCC::AL || PredReg != ARM::CPSR)
577 // Schedule the copy so it doesn't come between previous instructions
578 // and UseMI which can form an IT block.
579 unsigned SrcReg = SrcMI->getOperand(1).getReg();
580 ARMCC::CondCodes OCC = ARMCC::getOppositeCondition(CC);
581 MachineBasicBlock *MBB = UseMI->getParent();
582 MachineBasicBlock::iterator MBBI = SrcMI;
583 unsigned NumInsts = 0;
584 while (--MBBI != MBB->begin()) {
585 if (MBBI->isDebugValue())
588 MachineInstr *NMI = &*MBBI;
589 ARMCC::CondCodes NCC = llvm::getInstrPredicate(NMI, PredReg);
590 if (!(NCC == CC || NCC == OCC) ||
591 NMI->modifiesRegister(SrcReg, &TRI) ||
592 NMI->definesRegister(ARM::CPSR))
595 // Too many in a row!
601 MBB->insert(++MBBI, SrcMI);
606 llvm::getITInstrPredicate(const MachineInstr *MI, unsigned &PredReg) {
607 unsigned Opc = MI->getOpcode();
608 if (Opc == ARM::tBcc || Opc == ARM::t2Bcc)
610 return llvm::getInstrPredicate(MI, PredReg);