1 //===- Thumb2InstrInfo.cpp - Thumb-2 Instruction Information ----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Thumb-2 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "Thumb2InstrInfo.h"
16 #include "ARMConstantPoolValue.h"
17 #include "ARMAddressingModes.h"
18 #include "ARMGenInstrInfo.inc"
19 #include "ARMMachineFunctionInfo.h"
20 #include "Thumb2InstrInfo.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineMemOperand.h"
24 #include "llvm/CodeGen/PseudoSourceValue.h"
25 #include "llvm/ADT/SmallVector.h"
26 #include "llvm/Support/CommandLine.h"
31 OldT2IfCvt("old-thumb2-ifcvt", cl::Hidden,
32 cl::desc("Use old-style Thumb2 if-conversion heuristics"),
35 Thumb2InstrInfo::Thumb2InstrInfo(const ARMSubtarget &STI)
36 : ARMBaseInstrInfo(STI), RI(*this, STI) {
39 unsigned Thumb2InstrInfo::getUnindexedOpcode(unsigned Opc) const {
45 Thumb2InstrInfo::ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail,
46 MachineBasicBlock *NewDest) const {
47 MachineBasicBlock *MBB = Tail->getParent();
48 ARMFunctionInfo *AFI = MBB->getParent()->getInfo<ARMFunctionInfo>();
49 if (!AFI->hasITBlocks()) {
50 TargetInstrInfoImpl::ReplaceTailWithBranchTo(Tail, NewDest);
54 // If the first instruction of Tail is predicated, we may have to update
55 // the IT instruction.
57 ARMCC::CondCodes CC = llvm::getInstrPredicate(Tail, PredReg);
58 MachineBasicBlock::iterator MBBI = Tail;
60 // Expecting at least the t2IT instruction before it.
63 // Actually replace the tail.
64 TargetInstrInfoImpl::ReplaceTailWithBranchTo(Tail, NewDest);
67 if (CC != ARMCC::AL) {
68 MachineBasicBlock::iterator E = MBB->begin();
69 unsigned Count = 4; // At most 4 instructions in an IT block.
70 while (Count && MBBI != E) {
71 if (MBBI->isDebugValue()) {
75 if (MBBI->getOpcode() == ARM::t2IT) {
76 unsigned Mask = MBBI->getOperand(1).getImm();
78 MBBI->eraseFromParent();
80 unsigned MaskOn = 1 << Count;
81 unsigned MaskOff = ~(MaskOn - 1);
82 MBBI->getOperand(1).setImm((Mask & MaskOff) | MaskOn);
90 // Ctrl flow can reach here if branch folding is run before IT block
96 Thumb2InstrInfo::isLegalToSplitMBBAt(MachineBasicBlock &MBB,
97 MachineBasicBlock::iterator MBBI) const {
98 while (MBBI->isDebugValue()) {
100 if (MBBI == MBB.end())
104 unsigned PredReg = 0;
105 return llvm::getITInstrPredicate(MBBI, PredReg) == ARMCC::AL;
108 void Thumb2InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
109 MachineBasicBlock::iterator I, DebugLoc DL,
110 unsigned DestReg, unsigned SrcReg,
111 bool KillSrc) const {
112 // Handle SPR, DPR, and QPR copies.
113 if (!ARM::GPRRegClass.contains(DestReg, SrcReg))
114 return ARMBaseInstrInfo::copyPhysReg(MBB, I, DL, DestReg, SrcReg, KillSrc);
116 bool tDest = ARM::tGPRRegClass.contains(DestReg);
117 bool tSrc = ARM::tGPRRegClass.contains(SrcReg);
118 unsigned Opc = ARM::tMOVgpr2gpr;
122 Opc = ARM::tMOVtgpr2gpr;
124 Opc = ARM::tMOVgpr2tgpr;
126 BuildMI(MBB, I, DL, get(Opc), DestReg)
127 .addReg(SrcReg, getKillRegState(KillSrc));
130 void Thumb2InstrInfo::
131 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
132 unsigned SrcReg, bool isKill, int FI,
133 const TargetRegisterClass *RC,
134 const TargetRegisterInfo *TRI) const {
135 if (RC == ARM::GPRRegisterClass || RC == ARM::tGPRRegisterClass ||
136 RC == ARM::tcGPRRegisterClass || RC == ARM::rGPRRegisterClass) {
138 if (I != MBB.end()) DL = I->getDebugLoc();
140 MachineFunction &MF = *MBB.getParent();
141 MachineFrameInfo &MFI = *MF.getFrameInfo();
142 MachineMemOperand *MMO =
143 MF.getMachineMemOperand(
144 MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)),
145 MachineMemOperand::MOStore,
146 MFI.getObjectSize(FI),
147 MFI.getObjectAlignment(FI));
148 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::t2STRi12))
149 .addReg(SrcReg, getKillRegState(isKill))
150 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
154 ARMBaseInstrInfo::storeRegToStackSlot(MBB, I, SrcReg, isKill, FI, RC, TRI);
157 void Thumb2InstrInfo::
158 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
159 unsigned DestReg, int FI,
160 const TargetRegisterClass *RC,
161 const TargetRegisterInfo *TRI) const {
162 if (RC == ARM::GPRRegisterClass || RC == ARM::tGPRRegisterClass ||
163 RC == ARM::tcGPRRegisterClass || RC == ARM::rGPRRegisterClass) {
165 if (I != MBB.end()) DL = I->getDebugLoc();
167 MachineFunction &MF = *MBB.getParent();
168 MachineFrameInfo &MFI = *MF.getFrameInfo();
169 MachineMemOperand *MMO =
170 MF.getMachineMemOperand(
171 MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)),
172 MachineMemOperand::MOLoad,
173 MFI.getObjectSize(FI),
174 MFI.getObjectAlignment(FI));
175 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::t2LDRi12), DestReg)
176 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
180 ARMBaseInstrInfo::loadRegFromStackSlot(MBB, I, DestReg, FI, RC, TRI);
183 void llvm::emitT2RegPlusImmediate(MachineBasicBlock &MBB,
184 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
185 unsigned DestReg, unsigned BaseReg, int NumBytes,
186 ARMCC::CondCodes Pred, unsigned PredReg,
187 const ARMBaseInstrInfo &TII, unsigned MIFlags) {
188 bool isSub = NumBytes < 0;
189 if (isSub) NumBytes = -NumBytes;
191 // If profitable, use a movw or movt to materialize the offset.
192 // FIXME: Use the scavenger to grab a scratch register.
193 if (DestReg != ARM::SP && DestReg != BaseReg &&
195 ARM_AM::getT2SOImmVal(NumBytes) == -1) {
197 if (NumBytes < 65536) {
198 // Use a movw to materialize the 16-bit constant.
199 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi16), DestReg)
201 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags);
203 } else if ((NumBytes & 0xffff) == 0) {
204 // Use a movt to materialize the 32-bit constant.
205 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVTi16), DestReg)
207 .addImm(NumBytes >> 16)
208 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags);
214 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2SUBrr), DestReg)
215 .addReg(BaseReg, RegState::Kill)
216 .addReg(DestReg, RegState::Kill)
217 .addImm((unsigned)Pred).addReg(PredReg).addReg(0)
218 .setMIFlags(MIFlags);
220 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2ADDrr), DestReg)
221 .addReg(DestReg, RegState::Kill)
222 .addReg(BaseReg, RegState::Kill)
223 .addImm((unsigned)Pred).addReg(PredReg).addReg(0)
224 .setMIFlags(MIFlags);
231 unsigned ThisVal = NumBytes;
233 if (DestReg == ARM::SP && BaseReg != ARM::SP) {
234 // mov sp, rn. Note t2MOVr cannot be used.
235 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr),DestReg)
236 .addReg(BaseReg).setMIFlags(MIFlags);
241 bool HasCCOut = true;
242 if (BaseReg == ARM::SP) {
244 if (DestReg == ARM::SP && (ThisVal < ((1 << 7)-1) * 4)) {
245 assert((ThisVal & 3) == 0 && "Stack update is not multiple of 4?");
246 Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
247 // FIXME: Fix Thumb1 immediate encoding.
248 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
249 .addReg(BaseReg).addImm(ThisVal/4).setMIFlags(MIFlags);
254 // sub rd, sp, so_imm
255 Opc = isSub ? ARM::t2SUBrSPi : ARM::t2ADDrSPi;
256 if (ARM_AM::getT2SOImmVal(NumBytes) != -1) {
259 // FIXME: Move this to ARMAddressingModes.h?
260 unsigned RotAmt = CountLeadingZeros_32(ThisVal);
261 ThisVal = ThisVal & ARM_AM::rotr32(0xff000000U, RotAmt);
262 NumBytes &= ~ThisVal;
263 assert(ARM_AM::getT2SOImmVal(ThisVal) != -1 &&
264 "Bit extraction didn't work?");
267 assert(DestReg != ARM::SP && BaseReg != ARM::SP);
268 Opc = isSub ? ARM::t2SUBri : ARM::t2ADDri;
269 if (ARM_AM::getT2SOImmVal(NumBytes) != -1) {
271 } else if (ThisVal < 4096) {
272 Opc = isSub ? ARM::t2SUBri12 : ARM::t2ADDri12;
276 // FIXME: Move this to ARMAddressingModes.h?
277 unsigned RotAmt = CountLeadingZeros_32(ThisVal);
278 ThisVal = ThisVal & ARM_AM::rotr32(0xff000000U, RotAmt);
279 NumBytes &= ~ThisVal;
280 assert(ARM_AM::getT2SOImmVal(ThisVal) != -1 &&
281 "Bit extraction didn't work?");
285 // Build the new ADD / SUB.
286 MachineInstrBuilder MIB =
287 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
288 .addReg(BaseReg, RegState::Kill)
289 .addImm(ThisVal)).setMIFlags(MIFlags);
298 negativeOffsetOpcode(unsigned opcode)
301 case ARM::t2LDRi12: return ARM::t2LDRi8;
302 case ARM::t2LDRHi12: return ARM::t2LDRHi8;
303 case ARM::t2LDRBi12: return ARM::t2LDRBi8;
304 case ARM::t2LDRSHi12: return ARM::t2LDRSHi8;
305 case ARM::t2LDRSBi12: return ARM::t2LDRSBi8;
306 case ARM::t2STRi12: return ARM::t2STRi8;
307 case ARM::t2STRBi12: return ARM::t2STRBi8;
308 case ARM::t2STRHi12: return ARM::t2STRHi8;
328 positiveOffsetOpcode(unsigned opcode)
331 case ARM::t2LDRi8: return ARM::t2LDRi12;
332 case ARM::t2LDRHi8: return ARM::t2LDRHi12;
333 case ARM::t2LDRBi8: return ARM::t2LDRBi12;
334 case ARM::t2LDRSHi8: return ARM::t2LDRSHi12;
335 case ARM::t2LDRSBi8: return ARM::t2LDRSBi12;
336 case ARM::t2STRi8: return ARM::t2STRi12;
337 case ARM::t2STRBi8: return ARM::t2STRBi12;
338 case ARM::t2STRHi8: return ARM::t2STRHi12;
343 case ARM::t2LDRSHi12:
344 case ARM::t2LDRSBi12:
358 immediateOffsetOpcode(unsigned opcode)
361 case ARM::t2LDRs: return ARM::t2LDRi12;
362 case ARM::t2LDRHs: return ARM::t2LDRHi12;
363 case ARM::t2LDRBs: return ARM::t2LDRBi12;
364 case ARM::t2LDRSHs: return ARM::t2LDRSHi12;
365 case ARM::t2LDRSBs: return ARM::t2LDRSBi12;
366 case ARM::t2STRs: return ARM::t2STRi12;
367 case ARM::t2STRBs: return ARM::t2STRBi12;
368 case ARM::t2STRHs: return ARM::t2STRHi12;
373 case ARM::t2LDRSHi12:
374 case ARM::t2LDRSBi12:
395 bool llvm::rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
396 unsigned FrameReg, int &Offset,
397 const ARMBaseInstrInfo &TII) {
398 unsigned Opcode = MI.getOpcode();
399 const TargetInstrDesc &Desc = MI.getDesc();
400 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
403 // Memory operands in inline assembly always use AddrModeT2_i12.
404 if (Opcode == ARM::INLINEASM)
405 AddrMode = ARMII::AddrModeT2_i12; // FIXME. mode for thumb2?
407 if (Opcode == ARM::t2ADDri || Opcode == ARM::t2ADDri12) {
408 Offset += MI.getOperand(FrameRegIdx+1).getImm();
411 if (Offset == 0 && getInstrPredicate(&MI, PredReg) == ARMCC::AL) {
412 // Turn it into a move.
413 MI.setDesc(TII.get(ARM::tMOVgpr2gpr));
414 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
415 // Remove offset and remaining explicit predicate operands.
416 do MI.RemoveOperand(FrameRegIdx+1);
417 while (MI.getNumOperands() > FrameRegIdx+1 &&
418 (!MI.getOperand(FrameRegIdx+1).isReg() ||
419 !MI.getOperand(FrameRegIdx+1).isImm()));
423 bool isSP = FrameReg == ARM::SP;
424 bool HasCCOut = Opcode != ARM::t2ADDri12;
429 MI.setDesc(TII.get(isSP ? ARM::t2SUBrSPi : ARM::t2SUBri));
431 MI.setDesc(TII.get(isSP ? ARM::t2ADDrSPi : ARM::t2ADDri));
434 // Common case: small offset, fits into instruction.
435 if (ARM_AM::getT2SOImmVal(Offset) != -1) {
436 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
437 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
438 // Add cc_out operand if the original instruction did not have one.
440 MI.addOperand(MachineOperand::CreateReg(0, false));
444 // Another common case: imm12.
446 (!HasCCOut || MI.getOperand(MI.getNumOperands()-1).getReg() == 0)) {
447 unsigned NewOpc = isSP
448 ? (isSub ? ARM::t2SUBrSPi12 : ARM::t2ADDrSPi12)
449 : (isSub ? ARM::t2SUBri12 : ARM::t2ADDri12);
450 MI.setDesc(TII.get(NewOpc));
451 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
452 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
453 // Remove the cc_out operand.
455 MI.RemoveOperand(MI.getNumOperands()-1);
460 // Otherwise, extract 8 adjacent bits from the immediate into this
462 unsigned RotAmt = CountLeadingZeros_32(Offset);
463 unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xff000000U, RotAmt);
465 // We will handle these bits from offset, clear them.
466 Offset &= ~ThisImmVal;
468 assert(ARM_AM::getT2SOImmVal(ThisImmVal) != -1 &&
469 "Bit extraction didn't work?");
470 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal);
471 // Add cc_out operand if the original instruction did not have one.
473 MI.addOperand(MachineOperand::CreateReg(0, false));
477 // AddrMode4 and AddrMode6 cannot handle any offset.
478 if (AddrMode == ARMII::AddrMode4 || AddrMode == ARMII::AddrMode6)
481 // AddrModeT2_so cannot handle any offset. If there is no offset
482 // register then we change to an immediate version.
483 unsigned NewOpc = Opcode;
484 if (AddrMode == ARMII::AddrModeT2_so) {
485 unsigned OffsetReg = MI.getOperand(FrameRegIdx+1).getReg();
486 if (OffsetReg != 0) {
487 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
491 MI.RemoveOperand(FrameRegIdx+1);
492 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(0);
493 NewOpc = immediateOffsetOpcode(Opcode);
494 AddrMode = ARMII::AddrModeT2_i12;
497 unsigned NumBits = 0;
499 if (AddrMode == ARMII::AddrModeT2_i8 || AddrMode == ARMII::AddrModeT2_i12) {
500 // i8 supports only negative, and i12 supports only positive, so
501 // based on Offset sign convert Opcode to the appropriate
503 Offset += MI.getOperand(FrameRegIdx+1).getImm();
505 NewOpc = negativeOffsetOpcode(Opcode);
510 NewOpc = positiveOffsetOpcode(Opcode);
513 } else if (AddrMode == ARMII::AddrMode5) {
515 const MachineOperand &OffOp = MI.getOperand(FrameRegIdx+1);
516 int InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm());
517 if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM::sub)
521 Offset += InstrOffs * 4;
522 assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
528 llvm_unreachable("Unsupported addressing mode!");
531 if (NewOpc != Opcode)
532 MI.setDesc(TII.get(NewOpc));
534 MachineOperand &ImmOp = MI.getOperand(FrameRegIdx+1);
536 // Attempt to fold address computation
537 // Common case: small offset, fits into instruction.
538 int ImmedOffset = Offset / Scale;
539 unsigned Mask = (1 << NumBits) - 1;
540 if ((unsigned)Offset <= Mask * Scale) {
541 // Replace the FrameIndex with fp/sp
542 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
544 if (AddrMode == ARMII::AddrMode5)
545 // FIXME: Not consistent.
546 ImmedOffset |= 1 << NumBits;
548 ImmedOffset = -ImmedOffset;
550 ImmOp.ChangeToImmediate(ImmedOffset);
555 // Otherwise, offset doesn't fit. Pull in what we can to simplify
556 ImmedOffset = ImmedOffset & Mask;
558 if (AddrMode == ARMII::AddrMode5)
559 // FIXME: Not consistent.
560 ImmedOffset |= 1 << NumBits;
562 ImmedOffset = -ImmedOffset;
563 if (ImmedOffset == 0)
564 // Change the opcode back if the encoded offset is zero.
565 MI.setDesc(TII.get(positiveOffsetOpcode(NewOpc)));
568 ImmOp.ChangeToImmediate(ImmedOffset);
569 Offset &= ~(Mask*Scale);
572 Offset = (isSub) ? -Offset : Offset;
576 /// scheduleTwoAddrSource - Schedule the copy / re-mat of the source of the
577 /// two-addrss instruction inserted by two-address pass.
579 Thumb2InstrInfo::scheduleTwoAddrSource(MachineInstr *SrcMI,
581 const TargetRegisterInfo &TRI) const {
582 if (SrcMI->getOpcode() != ARM::tMOVgpr2gpr ||
583 SrcMI->getOperand(1).isKill())
586 unsigned PredReg = 0;
587 ARMCC::CondCodes CC = llvm::getInstrPredicate(UseMI, PredReg);
588 if (CC == ARMCC::AL || PredReg != ARM::CPSR)
591 // Schedule the copy so it doesn't come between previous instructions
592 // and UseMI which can form an IT block.
593 unsigned SrcReg = SrcMI->getOperand(1).getReg();
594 ARMCC::CondCodes OCC = ARMCC::getOppositeCondition(CC);
595 MachineBasicBlock *MBB = UseMI->getParent();
596 MachineBasicBlock::iterator MBBI = SrcMI;
597 unsigned NumInsts = 0;
598 while (--MBBI != MBB->begin()) {
599 if (MBBI->isDebugValue())
602 MachineInstr *NMI = &*MBBI;
603 ARMCC::CondCodes NCC = llvm::getInstrPredicate(NMI, PredReg);
604 if (!(NCC == CC || NCC == OCC) ||
605 NMI->modifiesRegister(SrcReg, &TRI) ||
606 NMI->definesRegister(ARM::CPSR))
609 // Too many in a row!
615 MBB->insert(++MBBI, SrcMI);
620 llvm::getITInstrPredicate(const MachineInstr *MI, unsigned &PredReg) {
621 unsigned Opc = MI->getOpcode();
622 if (Opc == ARM::tBcc || Opc == ARM::t2Bcc)
624 return llvm::getInstrPredicate(MI, PredReg);