1 //===- Thumb2InstrInfo.cpp - Thumb-2 Instruction Information ----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Thumb-2 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "Thumb2InstrInfo.h"
16 #include "ARMConstantPoolValue.h"
17 #include "ARMAddressingModes.h"
18 #include "ARMGenInstrInfo.inc"
19 #include "ARMMachineFunctionInfo.h"
20 #include "Thumb2HazardRecognizer.h"
21 #include "Thumb2InstrInfo.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineMemOperand.h"
25 #include "llvm/CodeGen/PseudoSourceValue.h"
26 #include "llvm/ADT/SmallVector.h"
27 #include "llvm/Support/CommandLine.h"
31 static cl::opt<unsigned>
32 IfCvtLimit("thumb2-ifcvt-limit (default 3)",
33 cl::Hidden, cl::init(3));
35 static cl::opt<unsigned>
36 IfCvtDiamondLimit("thumb2-ifcvt-diamond-limit (default 3)",
37 cl::Hidden, cl::init(3));
39 Thumb2InstrInfo::Thumb2InstrInfo(const ARMSubtarget &STI)
40 : ARMBaseInstrInfo(STI), RI(*this, STI) {
43 unsigned Thumb2InstrInfo::getUnindexedOpcode(unsigned Opc) const {
49 Thumb2InstrInfo::ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail,
50 MachineBasicBlock *NewDest) const {
51 MachineBasicBlock *MBB = Tail->getParent();
52 ARMFunctionInfo *AFI = MBB->getParent()->getInfo<ARMFunctionInfo>();
53 if (!AFI->hasITBlocks()) {
54 TargetInstrInfoImpl::ReplaceTailWithBranchTo(Tail, NewDest);
58 // If the first instruction of Tail is predicated, we may have to update
59 // the IT instruction.
61 ARMCC::CondCodes CC = llvm::getInstrPredicate(Tail, PredReg);
62 MachineBasicBlock::iterator MBBI = Tail;
64 // Expecting at least the t2IT instruction before it.
67 // Actually replace the tail.
68 TargetInstrInfoImpl::ReplaceTailWithBranchTo(Tail, NewDest);
71 if (CC != ARMCC::AL) {
72 MachineBasicBlock::iterator E = MBB->begin();
73 unsigned Count = 4; // At most 4 instructions in an IT block.
74 while (Count && MBBI != E) {
75 if (MBBI->isDebugValue()) {
79 if (MBBI->getOpcode() == ARM::t2IT) {
80 unsigned Mask = MBBI->getOperand(1).getImm();
82 MBBI->eraseFromParent();
84 unsigned MaskOn = 1 << Count;
85 unsigned MaskOff = ~(MaskOn - 1);
86 MBBI->getOperand(1).setImm((Mask & MaskOff) | MaskOn);
94 // Ctrl flow can reach here if branch folding is run before IT block
100 Thumb2InstrInfo::isLegalToSplitMBBAt(MachineBasicBlock &MBB,
101 MachineBasicBlock::iterator MBBI) const {
102 unsigned PredReg = 0;
103 return llvm::getITInstrPredicate(MBBI, PredReg) == ARMCC::AL;
106 bool Thumb2InstrInfo::isProfitableToIfCvt(MachineBasicBlock &MBB,
107 unsigned NumInstrs) const {
108 return NumInstrs && NumInstrs <= IfCvtLimit;
111 bool Thumb2InstrInfo::
112 isProfitableToIfCvt(MachineBasicBlock &TMBB, unsigned NumT,
113 MachineBasicBlock &FMBB, unsigned NumF) const {
114 // FIXME: Catch optimization such as:
117 return NumT && NumF &&
118 NumT <= (IfCvtDiamondLimit) && NumF <= (IfCvtDiamondLimit);
122 Thumb2InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
123 MachineBasicBlock::iterator I,
124 unsigned DestReg, unsigned SrcReg,
125 const TargetRegisterClass *DestRC,
126 const TargetRegisterClass *SrcRC,
128 if (DestRC == ARM::GPRRegisterClass || DestRC == ARM::tcGPRRegisterClass) {
129 if (SrcRC == ARM::GPRRegisterClass || SrcRC == ARM::tcGPRRegisterClass) {
130 BuildMI(MBB, I, DL, get(ARM::tMOVgpr2gpr), DestReg).addReg(SrcReg);
132 } else if (SrcRC == ARM::tGPRRegisterClass) {
133 BuildMI(MBB, I, DL, get(ARM::tMOVtgpr2gpr), DestReg).addReg(SrcReg);
136 } else if (DestRC == ARM::tGPRRegisterClass) {
137 if (SrcRC == ARM::GPRRegisterClass || SrcRC == ARM::tcGPRRegisterClass) {
138 BuildMI(MBB, I, DL, get(ARM::tMOVgpr2tgpr), DestReg).addReg(SrcReg);
140 } else if (SrcRC == ARM::tGPRRegisterClass) {
141 BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg).addReg(SrcReg);
146 // Handle SPR, DPR, and QPR copies.
147 return ARMBaseInstrInfo::copyRegToReg(MBB, I, DestReg, SrcReg, DestRC,
151 void Thumb2InstrInfo::
152 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
153 unsigned SrcReg, bool isKill, int FI,
154 const TargetRegisterClass *RC,
155 const TargetRegisterInfo *TRI) const {
156 if (RC == ARM::GPRRegisterClass || RC == ARM::tGPRRegisterClass ||
157 RC == ARM::tcGPRRegisterClass) {
159 if (I != MBB.end()) DL = I->getDebugLoc();
161 MachineFunction &MF = *MBB.getParent();
162 MachineFrameInfo &MFI = *MF.getFrameInfo();
163 MachineMemOperand *MMO =
164 MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI),
165 MachineMemOperand::MOStore, 0,
166 MFI.getObjectSize(FI),
167 MFI.getObjectAlignment(FI));
168 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::t2STRi12))
169 .addReg(SrcReg, getKillRegState(isKill))
170 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
174 ARMBaseInstrInfo::storeRegToStackSlot(MBB, I, SrcReg, isKill, FI, RC, TRI);
177 void Thumb2InstrInfo::
178 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
179 unsigned DestReg, int FI,
180 const TargetRegisterClass *RC,
181 const TargetRegisterInfo *TRI) const {
182 if (RC == ARM::GPRRegisterClass || RC == ARM::tGPRRegisterClass ||
183 RC == ARM::tcGPRRegisterClass) {
185 if (I != MBB.end()) DL = I->getDebugLoc();
187 MachineFunction &MF = *MBB.getParent();
188 MachineFrameInfo &MFI = *MF.getFrameInfo();
189 MachineMemOperand *MMO =
190 MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI),
191 MachineMemOperand::MOLoad, 0,
192 MFI.getObjectSize(FI),
193 MFI.getObjectAlignment(FI));
194 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::t2LDRi12), DestReg)
195 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
199 ARMBaseInstrInfo::loadRegFromStackSlot(MBB, I, DestReg, FI, RC, TRI);
202 ScheduleHazardRecognizer *Thumb2InstrInfo::
203 CreateTargetPostRAHazardRecognizer(const InstrItineraryData &II) const {
204 return (ScheduleHazardRecognizer *)new Thumb2HazardRecognizer(II);
207 void llvm::emitT2RegPlusImmediate(MachineBasicBlock &MBB,
208 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
209 unsigned DestReg, unsigned BaseReg, int NumBytes,
210 ARMCC::CondCodes Pred, unsigned PredReg,
211 const ARMBaseInstrInfo &TII) {
212 bool isSub = NumBytes < 0;
213 if (isSub) NumBytes = -NumBytes;
215 // If profitable, use a movw or movt to materialize the offset.
216 // FIXME: Use the scavenger to grab a scratch register.
217 if (DestReg != ARM::SP && DestReg != BaseReg &&
219 ARM_AM::getT2SOImmVal(NumBytes) == -1) {
221 if (NumBytes < 65536) {
222 // Use a movw to materialize the 16-bit constant.
223 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi16), DestReg)
225 .addImm((unsigned)Pred).addReg(PredReg).addReg(0);
227 } else if ((NumBytes & 0xffff) == 0) {
228 // Use a movt to materialize the 32-bit constant.
229 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVTi16), DestReg)
231 .addImm(NumBytes >> 16)
232 .addImm((unsigned)Pred).addReg(PredReg).addReg(0);
238 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2SUBrr), DestReg)
239 .addReg(BaseReg, RegState::Kill)
240 .addReg(DestReg, RegState::Kill)
241 .addImm((unsigned)Pred).addReg(PredReg).addReg(0);
243 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2ADDrr), DestReg)
244 .addReg(DestReg, RegState::Kill)
245 .addReg(BaseReg, RegState::Kill)
246 .addImm((unsigned)Pred).addReg(PredReg).addReg(0);
253 unsigned ThisVal = NumBytes;
255 if (DestReg == ARM::SP && BaseReg != ARM::SP) {
256 // mov sp, rn. Note t2MOVr cannot be used.
257 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr),DestReg).addReg(BaseReg);
262 bool HasCCOut = true;
263 if (BaseReg == ARM::SP) {
265 if (DestReg == ARM::SP && (ThisVal < ((1 << 7)-1) * 4)) {
266 assert((ThisVal & 3) == 0 && "Stack update is not multiple of 4?");
267 Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
268 // FIXME: Fix Thumb1 immediate encoding.
269 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
270 .addReg(BaseReg).addImm(ThisVal/4);
275 // sub rd, sp, so_imm
276 Opc = isSub ? ARM::t2SUBrSPi : ARM::t2ADDrSPi;
277 if (ARM_AM::getT2SOImmVal(NumBytes) != -1) {
280 // FIXME: Move this to ARMAddressingModes.h?
281 unsigned RotAmt = CountLeadingZeros_32(ThisVal);
282 ThisVal = ThisVal & ARM_AM::rotr32(0xff000000U, RotAmt);
283 NumBytes &= ~ThisVal;
284 assert(ARM_AM::getT2SOImmVal(ThisVal) != -1 &&
285 "Bit extraction didn't work?");
288 assert(DestReg != ARM::SP && BaseReg != ARM::SP);
289 Opc = isSub ? ARM::t2SUBri : ARM::t2ADDri;
290 if (ARM_AM::getT2SOImmVal(NumBytes) != -1) {
292 } else if (ThisVal < 4096) {
293 Opc = isSub ? ARM::t2SUBri12 : ARM::t2ADDri12;
297 // FIXME: Move this to ARMAddressingModes.h?
298 unsigned RotAmt = CountLeadingZeros_32(ThisVal);
299 ThisVal = ThisVal & ARM_AM::rotr32(0xff000000U, RotAmt);
300 NumBytes &= ~ThisVal;
301 assert(ARM_AM::getT2SOImmVal(ThisVal) != -1 &&
302 "Bit extraction didn't work?");
306 // Build the new ADD / SUB.
307 MachineInstrBuilder MIB =
308 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
309 .addReg(BaseReg, RegState::Kill)
319 negativeOffsetOpcode(unsigned opcode)
322 case ARM::t2LDRi12: return ARM::t2LDRi8;
323 case ARM::t2LDRHi12: return ARM::t2LDRHi8;
324 case ARM::t2LDRBi12: return ARM::t2LDRBi8;
325 case ARM::t2LDRSHi12: return ARM::t2LDRSHi8;
326 case ARM::t2LDRSBi12: return ARM::t2LDRSBi8;
327 case ARM::t2STRi12: return ARM::t2STRi8;
328 case ARM::t2STRBi12: return ARM::t2STRBi8;
329 case ARM::t2STRHi12: return ARM::t2STRHi8;
349 positiveOffsetOpcode(unsigned opcode)
352 case ARM::t2LDRi8: return ARM::t2LDRi12;
353 case ARM::t2LDRHi8: return ARM::t2LDRHi12;
354 case ARM::t2LDRBi8: return ARM::t2LDRBi12;
355 case ARM::t2LDRSHi8: return ARM::t2LDRSHi12;
356 case ARM::t2LDRSBi8: return ARM::t2LDRSBi12;
357 case ARM::t2STRi8: return ARM::t2STRi12;
358 case ARM::t2STRBi8: return ARM::t2STRBi12;
359 case ARM::t2STRHi8: return ARM::t2STRHi12;
364 case ARM::t2LDRSHi12:
365 case ARM::t2LDRSBi12:
379 immediateOffsetOpcode(unsigned opcode)
382 case ARM::t2LDRs: return ARM::t2LDRi12;
383 case ARM::t2LDRHs: return ARM::t2LDRHi12;
384 case ARM::t2LDRBs: return ARM::t2LDRBi12;
385 case ARM::t2LDRSHs: return ARM::t2LDRSHi12;
386 case ARM::t2LDRSBs: return ARM::t2LDRSBi12;
387 case ARM::t2STRs: return ARM::t2STRi12;
388 case ARM::t2STRBs: return ARM::t2STRBi12;
389 case ARM::t2STRHs: return ARM::t2STRHi12;
394 case ARM::t2LDRSHi12:
395 case ARM::t2LDRSBi12:
416 bool llvm::rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
417 unsigned FrameReg, int &Offset,
418 const ARMBaseInstrInfo &TII) {
419 unsigned Opcode = MI.getOpcode();
420 const TargetInstrDesc &Desc = MI.getDesc();
421 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
424 // Memory operands in inline assembly always use AddrModeT2_i12.
425 if (Opcode == ARM::INLINEASM)
426 AddrMode = ARMII::AddrModeT2_i12; // FIXME. mode for thumb2?
428 if (Opcode == ARM::t2ADDri || Opcode == ARM::t2ADDri12) {
429 Offset += MI.getOperand(FrameRegIdx+1).getImm();
432 if (Offset == 0 && getInstrPredicate(&MI, PredReg) == ARMCC::AL) {
433 // Turn it into a move.
434 MI.setDesc(TII.get(ARM::tMOVgpr2gpr));
435 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
436 // Remove offset and remaining explicit predicate operands.
437 do MI.RemoveOperand(FrameRegIdx+1);
438 while (MI.getNumOperands() > FrameRegIdx+1 &&
439 (!MI.getOperand(FrameRegIdx+1).isReg() ||
440 !MI.getOperand(FrameRegIdx+1).isImm()));
444 bool isSP = FrameReg == ARM::SP;
445 bool HasCCOut = Opcode != ARM::t2ADDri12;
450 MI.setDesc(TII.get(isSP ? ARM::t2SUBrSPi : ARM::t2SUBri));
452 MI.setDesc(TII.get(isSP ? ARM::t2ADDrSPi : ARM::t2ADDri));
455 // Common case: small offset, fits into instruction.
456 if (ARM_AM::getT2SOImmVal(Offset) != -1) {
457 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
458 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
459 // Add cc_out operand if the original instruction did not have one.
461 MI.addOperand(MachineOperand::CreateReg(0, false));
465 // Another common case: imm12.
467 (!HasCCOut || MI.getOperand(MI.getNumOperands()-1).getReg() == 0)) {
468 unsigned NewOpc = isSP
469 ? (isSub ? ARM::t2SUBrSPi12 : ARM::t2ADDrSPi12)
470 : (isSub ? ARM::t2SUBri12 : ARM::t2ADDri12);
471 MI.setDesc(TII.get(NewOpc));
472 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
473 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
474 // Remove the cc_out operand.
476 MI.RemoveOperand(MI.getNumOperands()-1);
481 // Otherwise, extract 8 adjacent bits from the immediate into this
483 unsigned RotAmt = CountLeadingZeros_32(Offset);
484 unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xff000000U, RotAmt);
486 // We will handle these bits from offset, clear them.
487 Offset &= ~ThisImmVal;
489 assert(ARM_AM::getT2SOImmVal(ThisImmVal) != -1 &&
490 "Bit extraction didn't work?");
491 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal);
492 // Add cc_out operand if the original instruction did not have one.
494 MI.addOperand(MachineOperand::CreateReg(0, false));
498 // AddrMode4 and AddrMode6 cannot handle any offset.
499 if (AddrMode == ARMII::AddrMode4 || AddrMode == ARMII::AddrMode6)
502 // AddrModeT2_so cannot handle any offset. If there is no offset
503 // register then we change to an immediate version.
504 unsigned NewOpc = Opcode;
505 if (AddrMode == ARMII::AddrModeT2_so) {
506 unsigned OffsetReg = MI.getOperand(FrameRegIdx+1).getReg();
507 if (OffsetReg != 0) {
508 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
512 MI.RemoveOperand(FrameRegIdx+1);
513 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(0);
514 NewOpc = immediateOffsetOpcode(Opcode);
515 AddrMode = ARMII::AddrModeT2_i12;
518 unsigned NumBits = 0;
520 if (AddrMode == ARMII::AddrModeT2_i8 || AddrMode == ARMII::AddrModeT2_i12) {
521 // i8 supports only negative, and i12 supports only positive, so
522 // based on Offset sign convert Opcode to the appropriate
524 Offset += MI.getOperand(FrameRegIdx+1).getImm();
526 NewOpc = negativeOffsetOpcode(Opcode);
531 NewOpc = positiveOffsetOpcode(Opcode);
534 } else if (AddrMode == ARMII::AddrMode5) {
536 const MachineOperand &OffOp = MI.getOperand(FrameRegIdx+1);
537 int InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm());
538 if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM::sub)
542 Offset += InstrOffs * 4;
543 assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
549 llvm_unreachable("Unsupported addressing mode!");
552 if (NewOpc != Opcode)
553 MI.setDesc(TII.get(NewOpc));
555 MachineOperand &ImmOp = MI.getOperand(FrameRegIdx+1);
557 // Attempt to fold address computation
558 // Common case: small offset, fits into instruction.
559 int ImmedOffset = Offset / Scale;
560 unsigned Mask = (1 << NumBits) - 1;
561 if ((unsigned)Offset <= Mask * Scale) {
562 // Replace the FrameIndex with fp/sp
563 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
565 if (AddrMode == ARMII::AddrMode5)
566 // FIXME: Not consistent.
567 ImmedOffset |= 1 << NumBits;
569 ImmedOffset = -ImmedOffset;
571 ImmOp.ChangeToImmediate(ImmedOffset);
576 // Otherwise, offset doesn't fit. Pull in what we can to simplify
577 ImmedOffset = ImmedOffset & Mask;
579 if (AddrMode == ARMII::AddrMode5)
580 // FIXME: Not consistent.
581 ImmedOffset |= 1 << NumBits;
583 ImmedOffset = -ImmedOffset;
584 if (ImmedOffset == 0)
585 // Change the opcode back if the encoded offset is zero.
586 MI.setDesc(TII.get(positiveOffsetOpcode(NewOpc)));
589 ImmOp.ChangeToImmediate(ImmedOffset);
590 Offset &= ~(Mask*Scale);
593 Offset = (isSub) ? -Offset : Offset;
597 /// scheduleTwoAddrSource - Schedule the copy / re-mat of the source of the
598 /// two-addrss instruction inserted by two-address pass.
600 Thumb2InstrInfo::scheduleTwoAddrSource(MachineInstr *SrcMI,
602 const TargetRegisterInfo &TRI) const {
603 if (SrcMI->getOpcode() != ARM::tMOVgpr2gpr ||
604 SrcMI->getOperand(1).isKill())
607 unsigned PredReg = 0;
608 ARMCC::CondCodes CC = llvm::getInstrPredicate(UseMI, PredReg);
609 if (CC == ARMCC::AL || PredReg != ARM::CPSR)
612 // Schedule the copy so it doesn't come between previous instructions
613 // and UseMI which can form an IT block.
614 unsigned SrcReg = SrcMI->getOperand(1).getReg();
615 ARMCC::CondCodes OCC = ARMCC::getOppositeCondition(CC);
616 MachineBasicBlock *MBB = UseMI->getParent();
617 MachineBasicBlock::iterator MBBI = SrcMI;
618 unsigned NumInsts = 0;
619 while (--MBBI != MBB->begin()) {
620 if (MBBI->isDebugValue())
623 MachineInstr *NMI = &*MBBI;
624 ARMCC::CondCodes NCC = llvm::getInstrPredicate(NMI, PredReg);
625 if (!(NCC == CC || NCC == OCC) ||
626 NMI->modifiesRegister(SrcReg, &TRI) ||
627 NMI->definesRegister(ARM::CPSR))
630 // Too many in a row!
636 MBB->insert(++MBBI, SrcMI);
641 llvm::getITInstrPredicate(const MachineInstr *MI, unsigned &PredReg) {
642 unsigned Opc = MI->getOpcode();
643 if (Opc == ARM::tBcc || Opc == ARM::t2Bcc)
645 return llvm::getInstrPredicate(MI, PredReg);