1 //===- Thumb2InstrInfo.cpp - Thumb-2 Instruction Information --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Thumb-2 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "ARMInstrInfo.h"
16 #include "ARMGenInstrInfo.inc"
17 #include "ARMMachineFunctionInfo.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/ADT/SmallVector.h"
21 #include "Thumb2InstrInfo.h"
25 Thumb2InstrInfo::Thumb2InstrInfo(const ARMSubtarget &STI)
26 : ARMBaseInstrInfo(STI), RI(*this, STI) {
29 unsigned Thumb2InstrInfo::getUnindexedOpcode(unsigned Opc) const {
34 unsigned Thumb2InstrInfo::getOpcode(ARMII::Op Op) const {
36 case ARMII::ADDri: return ARM::t2ADDri;
37 case ARMII::MOVr: return ARM::t2MOVr;
38 case ARMII::SUBri: return ARM::t2SUBri;
47 Thumb2InstrInfo::BlockHasNoFallThrough(const MachineBasicBlock &MBB) const {
48 if (MBB.empty()) return false;
50 switch (MBB.back().getOpcode()) {
52 case ARM::t2B: // Uncond branch.
53 case ARM::t2BR_JT: // Jumptable branch.
54 case ARM::tBR_JTr: // Jumptable branch (16-bit version).
56 case ARM::tBX_RET_vararg:
68 Thumb2InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
69 MachineBasicBlock::iterator I,
70 unsigned DestReg, unsigned SrcReg,
71 const TargetRegisterClass *DestRC,
72 const TargetRegisterClass *SrcRC) const {
73 DebugLoc DL = DebugLoc::getUnknownLoc();
74 if (I != MBB.end()) DL = I->getDebugLoc();
76 if (DestRC == ARM::GPRRegisterClass &&
77 SrcRC == ARM::GPRRegisterClass) {
78 AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::t2MOVr),
79 DestReg).addReg(SrcReg)));
81 } else if (DestRC == ARM::GPRRegisterClass &&
82 SrcRC == ARM::tGPRRegisterClass) {
83 BuildMI(MBB, I, DL, get(ARM::tMOVtgpr2gpr), DestReg).addReg(SrcReg);
85 } else if (DestRC == ARM::tGPRRegisterClass &&
86 SrcRC == ARM::GPRRegisterClass) {
87 BuildMI(MBB, I, DL, get(ARM::tMOVgpr2tgpr), DestReg).addReg(SrcReg);
91 // Handle SPR, DPR, and QPR copies.
92 return ARMBaseInstrInfo::copyRegToReg(MBB, I, DestReg, SrcReg, DestRC, SrcRC);
95 void Thumb2InstrInfo::
96 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
97 unsigned SrcReg, bool isKill, int FI,
98 const TargetRegisterClass *RC) const {
99 DebugLoc DL = DebugLoc::getUnknownLoc();
100 if (I != MBB.end()) DL = I->getDebugLoc();
102 if (RC == ARM::GPRRegisterClass) {
103 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::t2STRi12))
104 .addReg(SrcReg, getKillRegState(isKill))
105 .addFrameIndex(FI).addImm(0));
109 ARMBaseInstrInfo::storeRegToStackSlot(MBB, I, SrcReg, isKill, FI, RC);
112 void Thumb2InstrInfo::
113 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
114 unsigned DestReg, int FI,
115 const TargetRegisterClass *RC) const {
116 DebugLoc DL = DebugLoc::getUnknownLoc();
117 if (I != MBB.end()) DL = I->getDebugLoc();
119 if (RC == ARM::GPRRegisterClass) {
120 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::t2LDRi12), DestReg)
121 .addFrameIndex(FI).addImm(0));
125 ARMBaseInstrInfo::loadRegFromStackSlot(MBB, I, DestReg, FI, RC);